1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import utility._ 24import utils._ 25import xiangshan._ 26import xiangshan.backend.Bundles.{DynInst, MemExuInput} 27import xiangshan.backend.rob.RobPtr 28import xiangshan.cache._ 29import xiangshan.backend.fu.FenceToSbuffer 30import xiangshan.cache.wpu.ReplayCarry 31import xiangshan.mem.prefetch.PrefetchReqBundle 32 33object genWmask { 34 def apply(addr: UInt, sizeEncode: UInt): UInt = { 35 (LookupTree(sizeEncode, List( 36 "b00".U -> 0x1.U, //0001 << addr(2:0) 37 "b01".U -> 0x3.U, //0011 38 "b10".U -> 0xf.U, //1111 39 "b11".U -> 0xff.U //11111111 40 )) << addr(2, 0)).asUInt 41 } 42} 43 44object genVWmask { 45 def apply(addr: UInt, sizeEncode: UInt): UInt = { 46 (LookupTree(sizeEncode, List( 47 "b00".U -> 0x1.U, //0001 << addr(2:0) 48 "b01".U -> 0x3.U, //0011 49 "b10".U -> 0xf.U, //1111 50 "b11".U -> 0xff.U //11111111 51 )) << addr(3, 0)).asUInt 52 } 53} 54 55object genWdata { 56 def apply(data: UInt, sizeEncode: UInt): UInt = { 57 LookupTree(sizeEncode, List( 58 "b00".U -> Fill(16, data(7, 0)), 59 "b01".U -> Fill(8, data(15, 0)), 60 "b10".U -> Fill(4, data(31, 0)), 61 "b11".U -> Fill(2, data(63,0)) 62 )) 63 } 64} 65 66object shiftDataToLow { 67 def apply(addr: UInt,data : UInt): UInt = { 68 Mux(addr(3), (data >> 64).asUInt,data) 69 } 70} 71object shiftMaskToLow { 72 def apply(addr: UInt,mask: UInt): UInt = { 73 Mux(addr(3),(mask >> 8).asUInt,mask) 74 } 75} 76 77class LsPipelineBundle(implicit p: Parameters) extends XSBundle 78 with HasDCacheParameters 79 with HasVLSUParameters { 80 val uop = new DynInst 81 val vaddr = UInt(VAddrBits.W) 82 val paddr = UInt(PAddrBits.W) 83 // val func = UInt(6.W) 84 val mask = UInt((VLEN/8).W) 85 val data = UInt((VLEN+1).W) 86 val wlineflag = Bool() // store write the whole cache line 87 88 val miss = Bool() 89 val tlbMiss = Bool() 90 val ptwBack = Bool() 91 val mmio = Bool() 92 val atomic = Bool() 93 val rsIdx = UInt(log2Up(MemIQSizeMax).W) 94 95 val forwardMask = Vec(VLEN/8, Bool()) 96 val forwardData = Vec(VLEN/8, UInt(8.W)) 97 98 // prefetch 99 val isPrefetch = Bool() 100 val isHWPrefetch = Bool() 101 def isSWPrefetch = isPrefetch && !isHWPrefetch 102 103 // vector 104 val isvec = Bool() 105 val isLastElem = Bool() 106 val is128bit = Bool() 107 val uop_unit_stride_fof = Bool() 108 // val rob_idx_valid = Vec(2,Bool()) 109 // val inner_idx = Vec(2,UInt(3.W)) 110 // val rob_idx = Vec(2,new RobPtr) 111 val reg_offset = UInt(vOffsetBits.W) 112 // val offset = Vec(2,UInt(4.W)) 113 val vecActive = Bool() // 1: vector active element or scala mem operation, 0: vector not active element 114 val is_first_ele = Bool() 115 val flowPtr = new VlflowPtr() // VLFlowQueue ptr 116 val sflowPtr = new VsFlowPtr() // VSFlowQueue ptr 117 118 // For debug usage 119 val isFirstIssue = Bool() 120 val hasROBEntry = Bool() 121 122 // For load replay 123 val isLoadReplay = Bool() 124 val isFastPath = Bool() 125 val isFastReplay = Bool() 126 val replayCarry = new ReplayCarry(nWays) 127 128 // For dcache miss load 129 val mshrid = UInt(log2Up(cfg.nMissEntries).W) 130 val handledByMSHR = Bool() 131 val replacementUpdated = Bool() 132 val missDbUpdated = Bool() 133 134 val forward_tlDchannel = Bool() 135 val dcacheRequireReplay = Bool() 136 val delayedLoadError = Bool() 137 val lateKill = Bool() 138 val feedbacked = Bool() 139 val ldCancel = ValidUndirectioned(UInt(log2Ceil(LoadPipelineWidth).W)) 140 // loadQueueReplay index. 141 val schedIndex = UInt(log2Up(LoadQueueReplaySize).W) 142} 143 144class LdPrefetchTrainBundle(implicit p: Parameters) extends LsPipelineBundle { 145 val meta_prefetch = UInt(L1PfSourceBits.W) 146 val meta_access = Bool() 147 148 def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false) = { 149 if (latch) vaddr := RegNext(input.vaddr) else vaddr := input.vaddr 150 if (latch) paddr := RegNext(input.paddr) else paddr := input.paddr 151 if (latch) mask := RegNext(input.mask) else mask := input.mask 152 if (latch) data := RegNext(input.data) else data := input.data 153 if (latch) uop := RegNext(input.uop) else uop := input.uop 154 if (latch) wlineflag := RegNext(input.wlineflag) else wlineflag := input.wlineflag 155 if (latch) miss := RegNext(input.miss) else miss := input.miss 156 if (latch) tlbMiss := RegNext(input.tlbMiss) else tlbMiss := input.tlbMiss 157 if (latch) ptwBack := RegNext(input.ptwBack) else ptwBack := input.ptwBack 158 if (latch) mmio := RegNext(input.mmio) else mmio := input.mmio 159 if (latch) rsIdx := RegNext(input.rsIdx) else rsIdx := input.rsIdx 160 if (latch) forwardMask := RegNext(input.forwardMask) else forwardMask := input.forwardMask 161 if (latch) forwardData := RegNext(input.forwardData) else forwardData := input.forwardData 162 if (latch) isPrefetch := RegNext(input.isPrefetch) else isPrefetch := input.isPrefetch 163 if (latch) isHWPrefetch := RegNext(input.isHWPrefetch) else isHWPrefetch := input.isHWPrefetch 164 if (latch) isFirstIssue := RegNext(input.isFirstIssue) else isFirstIssue := input.isFirstIssue 165 if (latch) hasROBEntry := RegNext(input.hasROBEntry) else hasROBEntry := input.hasROBEntry 166 if (latch) dcacheRequireReplay := RegNext(input.dcacheRequireReplay) else dcacheRequireReplay := input.dcacheRequireReplay 167 if (latch) schedIndex := RegNext(input.schedIndex) else schedIndex := input.schedIndex 168 if (latch) isvec := RegNext(input.isvec) else isvec := input.isvec 169 if (latch) isLastElem := RegNext(input.isLastElem) else isLastElem := input.isLastElem 170 if (latch) is128bit := RegNext(input.is128bit) else is128bit := input.is128bit 171 if (latch) vecActive := RegNext(input.vecActive) else vecActive := input.vecActive 172 if (latch) is_first_ele := RegNext(input.is_first_ele) else is_first_ele := input.is_first_ele 173 if (latch) uop_unit_stride_fof := RegNext(input.uop_unit_stride_fof) else uop_unit_stride_fof := input.uop_unit_stride_fof 174 if (latch) reg_offset := RegNext(input.reg_offset) else reg_offset := input.reg_offset 175 if (latch) flowPtr := RegNext(input.flowPtr) else flowPtr := input.flowPtr 176 if (latch) sflowPtr := RegNext(input.sflowPtr) else sflowPtr := input.sflowPtr 177 178 meta_prefetch := DontCare 179 meta_access := DontCare 180 forward_tlDchannel := DontCare 181 mshrid := DontCare 182 replayCarry := DontCare 183 atomic := DontCare 184 isLoadReplay := DontCare 185 isFastPath := DontCare 186 isFastReplay := DontCare 187 handledByMSHR := DontCare 188 replacementUpdated := DontCare 189 missDbUpdated := DontCare 190 delayedLoadError := DontCare 191 lateKill := DontCare 192 feedbacked := DontCare 193 ldCancel := DontCare 194 } 195 196 def asPrefetchReqBundle(): PrefetchReqBundle = { 197 val res = Wire(new PrefetchReqBundle) 198 res.vaddr := this.vaddr 199 res.paddr := this.paddr 200 res.pc := this.uop.pc 201 202 res 203 } 204} 205 206class StPrefetchTrainBundle(implicit p: Parameters) extends LdPrefetchTrainBundle {} 207 208class LqWriteBundle(implicit p: Parameters) extends LsPipelineBundle { 209 // load inst replay informations 210 val rep_info = new LoadToLsqReplayIO 211 // queue entry data, except flag bits, will be updated if writeQueue is true, 212 // valid bit in LqWriteBundle will be ignored 213 val data_wen_dup = Vec(6, Bool()) // dirty reg dup 214 215 216 def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false) = { 217 if(latch) vaddr := RegNext(input.vaddr) else vaddr := input.vaddr 218 if(latch) paddr := RegNext(input.paddr) else paddr := input.paddr 219 if(latch) mask := RegNext(input.mask) else mask := input.mask 220 if(latch) data := RegNext(input.data) else data := input.data 221 if(latch) uop := RegNext(input.uop) else uop := input.uop 222 if(latch) wlineflag := RegNext(input.wlineflag) else wlineflag := input.wlineflag 223 if(latch) miss := RegNext(input.miss) else miss := input.miss 224 if(latch) tlbMiss := RegNext(input.tlbMiss) else tlbMiss := input.tlbMiss 225 if(latch) ptwBack := RegNext(input.ptwBack) else ptwBack := input.ptwBack 226 if(latch) mmio := RegNext(input.mmio) else mmio := input.mmio 227 if(latch) atomic := RegNext(input.atomic) else atomic := input.atomic 228 if(latch) rsIdx := RegNext(input.rsIdx) else rsIdx := input.rsIdx 229 if(latch) forwardMask := RegNext(input.forwardMask) else forwardMask := input.forwardMask 230 if(latch) forwardData := RegNext(input.forwardData) else forwardData := input.forwardData 231 if(latch) isPrefetch := RegNext(input.isPrefetch) else isPrefetch := input.isPrefetch 232 if(latch) isHWPrefetch := RegNext(input.isHWPrefetch) else isHWPrefetch := input.isHWPrefetch 233 if(latch) isFirstIssue := RegNext(input.isFirstIssue) else isFirstIssue := input.isFirstIssue 234 if(latch) hasROBEntry := RegNext(input.hasROBEntry) else hasROBEntry := input.hasROBEntry 235 if(latch) isLoadReplay := RegNext(input.isLoadReplay) else isLoadReplay := input.isLoadReplay 236 if(latch) isFastPath := RegNext(input.isFastPath) else isFastPath := input.isFastPath 237 if(latch) isFastReplay := RegNext(input.isFastReplay) else isFastReplay := input.isFastReplay 238 if(latch) mshrid := RegNext(input.mshrid) else mshrid := input.mshrid 239 if(latch) forward_tlDchannel := RegNext(input.forward_tlDchannel) else forward_tlDchannel := input.forward_tlDchannel 240 if(latch) replayCarry := RegNext(input.replayCarry) else replayCarry := input.replayCarry 241 if(latch) dcacheRequireReplay := RegNext(input.dcacheRequireReplay) else dcacheRequireReplay := input.dcacheRequireReplay 242 if(latch) schedIndex := RegNext(input.schedIndex) else schedIndex := input.schedIndex 243 if(latch) handledByMSHR := RegNext(input.handledByMSHR) else handledByMSHR := input.handledByMSHR 244 if(latch) replacementUpdated := RegNext(input.replacementUpdated) else replacementUpdated := input.replacementUpdated 245 if(latch) missDbUpdated := RegNext(input.missDbUpdated) else missDbUpdated := input.missDbUpdated 246 if(latch) delayedLoadError := RegNext(input.delayedLoadError) else delayedLoadError := input.delayedLoadError 247 if(latch) lateKill := RegNext(input.lateKill) else lateKill := input.lateKill 248 if(latch) feedbacked := RegNext(input.feedbacked) else feedbacked := input.feedbacked 249 if(latch) isvec := RegNext(input.isvec) else isvec := input.isvec 250 if(latch) is128bit := RegNext(input.is128bit) else is128bit := input.is128bit 251 if(latch) vecActive := RegNext(input.vecActive) else vecActive := input.vecActive 252 if(latch) uop_unit_stride_fof := RegNext(input.uop_unit_stride_fof) else uop_unit_stride_fof := input.uop_unit_stride_fof 253 if(latch) reg_offset := RegNext(input.reg_offset) else reg_offset := input.reg_offset 254 255 rep_info := DontCare 256 data_wen_dup := DontCare 257 } 258} 259 260class LoadForwardQueryIO(implicit p: Parameters) extends XSBundle { 261 val vaddr = Output(UInt(VAddrBits.W)) 262 val paddr = Output(UInt(PAddrBits.W)) 263 val mask = Output(UInt((VLEN/8).W)) 264 val uop = Output(new DynInst) // for replay 265 val pc = Output(UInt(VAddrBits.W)) //for debug 266 val valid = Output(Bool()) 267 268 val forwardMaskFast = Input(Vec((VLEN/8), Bool())) // resp to load_s1 269 val forwardMask = Input(Vec((VLEN/8), Bool())) // resp to load_s2 270 val forwardData = Input(Vec((VLEN/8), UInt(8.W))) // resp to load_s2 271 272 // val lqIdx = Output(UInt(LoadQueueIdxWidth.W)) 273 val sqIdx = Output(new SqPtr) 274 275 // dataInvalid suggests store to load forward found forward should happen, 276 // but data is not available for now. If dataInvalid, load inst should 277 // be replayed from RS. Feedback type should be RSFeedbackType.dataInvalid 278 val dataInvalid = Input(Bool()) // Addr match, but data is not valid for now 279 280 // matchInvalid suggests in store to load forward logic, paddr cam result does 281 // to equal to vaddr cam result. If matchInvalid, a microarchitectural exception 282 // should be raised to flush SQ and committed sbuffer. 283 val matchInvalid = Input(Bool()) // resp to load_s2 284 285 // addrInvalid suggests store to load forward found forward should happen, 286 // but address (SSID) is not available for now. If addrInvalid, load inst should 287 // be replayed from RS. Feedback type should be RSFeedbackType.addrInvalid 288 val addrInvalid = Input(Bool()) 289} 290 291// LoadForwardQueryIO used in load pipeline 292// 293// Difference between PipeLoadForwardQueryIO and LoadForwardQueryIO: 294// PipeIO use predecoded sqIdxMask for better forward timing 295class PipeLoadForwardQueryIO(implicit p: Parameters) extends LoadForwardQueryIO { 296 // val sqIdx = Output(new SqPtr) // for debug, should not be used in pipeline for timing reasons 297 // sqIdxMask is calcuated in earlier stage for better timing 298 val sqIdxMask = Output(UInt(StoreQueueSize.W)) 299 300 // dataInvalid: addr match, but data is not valid for now 301 val dataInvalidFast = Input(Bool()) // resp to load_s1 302 // val dataInvalid = Input(Bool()) // resp to load_s2 303 val dataInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx 304 val addrInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx 305} 306 307// Query load queue for ld-ld violation 308// 309// Req should be send in load_s1 310// Resp will be generated 1 cycle later 311// 312// Note that query req may be !ready, as dcache is releasing a block 313// If it happens, a replay from rs is needed. 314class LoadNukeQueryReq(implicit p: Parameters) extends XSBundle { // provide lqIdx 315 val uop = new DynInst 316 // mask: load's data mask. 317 val mask = UInt((VLEN/8).W) 318 319 // paddr: load's paddr. 320 val paddr = UInt(PAddrBits.W) 321 // dataInvalid: load data is invalid. 322 val data_valid = Bool() 323} 324 325class LoadNukeQueryResp(implicit p: Parameters) extends XSBundle { 326 // rep_frm_fetch: ld-ld violation check success, replay from fetch. 327 val rep_frm_fetch = Bool() 328} 329 330class LoadNukeQueryIO(implicit p: Parameters) extends XSBundle { 331 val req = Decoupled(new LoadNukeQueryReq) 332 val resp = Flipped(Valid(new LoadNukeQueryResp)) 333 val revoke = Output(Bool()) 334} 335 336class StoreNukeQueryIO(implicit p: Parameters) extends XSBundle { 337 // robIdx: Requestor's (a store instruction) rob index for match logic. 338 val robIdx = new RobPtr 339 340 // paddr: requestor's (a store instruction) physical address for match logic. 341 val paddr = UInt(PAddrBits.W) 342 343 // mask: requestor's (a store instruction) data width mask for match logic. 344 val mask = UInt((VLEN/8).W) 345} 346 347// Store byte valid mask write bundle 348// 349// Store byte valid mask write to SQ takes 2 cycles 350class StoreMaskBundle(implicit p: Parameters) extends XSBundle { 351 val sqIdx = new SqPtr 352 val mask = UInt((VLEN/8).W) 353} 354 355class LoadDataFromDcacheBundle(implicit p: Parameters) extends DCacheBundle { 356 // old dcache: optimize data sram read fanout 357 // val bankedDcacheData = Vec(DCacheBanks, UInt(64.W)) 358 // val bank_oh = UInt(DCacheBanks.W) 359 360 // new dcache 361 val respDcacheData = UInt(VLEN.W) 362 val forwardMask = Vec(VLEN/8, Bool()) 363 val forwardData = Vec(VLEN/8, UInt(8.W)) 364 val uop = new DynInst // for data selection, only fwen and fuOpType are used 365 val addrOffset = UInt(4.W) // for data selection 366 367 // forward tilelink D channel 368 val forward_D = Bool() 369 val forwardData_D = Vec(VLEN/8, UInt(8.W)) 370 371 // forward mshr data 372 val forward_mshr = Bool() 373 val forwardData_mshr = Vec(VLEN/8, UInt(8.W)) 374 375 val forward_result_valid = Bool() 376 377 def dcacheData(): UInt = { 378 // old dcache 379 // val dcache_data = Mux1H(bank_oh, bankedDcacheData) 380 // new dcache 381 val dcache_data = respDcacheData 382 val use_D = forward_D && forward_result_valid 383 val use_mshr = forward_mshr && forward_result_valid 384 Mux(use_D, forwardData_D.asUInt, Mux(use_mshr, forwardData_mshr.asUInt, dcache_data)) 385 } 386 387 def mergedData(): UInt = { 388 val rdataVec = VecInit((0 until VLEN / 8).map(j => 389 Mux(forwardMask(j), forwardData(j), dcacheData()(8*(j+1)-1, 8*j)) 390 )) 391 rdataVec.asUInt 392 } 393} 394 395// Load writeback data from load queue (refill) 396class LoadDataFromLQBundle(implicit p: Parameters) extends XSBundle { 397 val lqData = UInt(64.W) // load queue has merged data 398 val uop = new DynInst // for data selection, only fwen and fuOpType are used 399 val addrOffset = UInt(3.W) // for data selection 400 401 def mergedData(): UInt = { 402 lqData 403 } 404} 405 406// Bundle for load / store wait waking up 407class MemWaitUpdateReq(implicit p: Parameters) extends XSBundle { 408 val robIdx = Vec(backendParams.StaExuCnt, ValidIO(new RobPtr)) 409 val sqIdx = Vec(backendParams.StdCnt, ValidIO(new SqPtr)) 410} 411 412object AddPipelineReg { 413 class PipelineRegModule[T <: Data](gen: T) extends Module { 414 val io = IO(new Bundle() { 415 val in = Flipped(DecoupledIO(gen.cloneType)) 416 val out = DecoupledIO(gen.cloneType) 417 val isFlush = Input(Bool()) 418 }) 419 420 val valid = RegInit(false.B) 421 valid.suggestName("pipeline_reg_valid") 422 when (io.out.fire) { valid := false.B } 423 when (io.in.fire) { valid := true.B } 424 when (io.isFlush) { valid := false.B } 425 426 io.in.ready := !valid || io.out.ready 427 io.out.bits := RegEnable(io.in.bits, io.in.fire) 428 io.out.valid := valid //&& !isFlush 429 } 430 431 def apply[T <: Data] 432 (left: DecoupledIO[T], right: DecoupledIO[T], isFlush: Bool, 433 moduleName: Option[String] = None 434 ){ 435 val pipelineReg = Module(new PipelineRegModule[T](left.bits.cloneType)) 436 if(moduleName.nonEmpty) pipelineReg.suggestName(moduleName.get) 437 pipelineReg.io.in <> left 438 right <> pipelineReg.io.out 439 pipelineReg.io.isFlush := isFlush 440 } 441} 442