1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* 6* XiangShan is licensed under Mulan PSL v2. 7* You can use this software according to the terms and conditions of the Mulan PSL v2. 8* You may obtain a copy of Mulan PSL v2 at: 9* http://license.coscl.org.cn/MulanPSL2 10* 11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14* 15* See the Mulan PSL v2 for more details. 16***************************************************************************************/ 17 18package xiangshan.mem 19 20 21import org.chipsalliance.cde.config.Parameters 22import chisel3._ 23import chisel3.util._ 24import utility._ 25import utils._ 26import xiangshan._ 27import xiangshan.backend.Bundles.{DynInst, MemExuInput} 28import xiangshan.backend.rob.RobPtr 29import xiangshan.cache._ 30import xiangshan.backend.fu.FenceToSbuffer 31import xiangshan.cache.wpu.ReplayCarry 32import xiangshan.mem.prefetch.PrefetchReqBundle 33import math._ 34 35object genWmask { 36 def apply(addr: UInt, sizeEncode: UInt): UInt = { 37 (LookupTree(sizeEncode, List( 38 "b00".U -> 0x1.U, //0001 << addr(2:0) 39 "b01".U -> 0x3.U, //0011 40 "b10".U -> 0xf.U, //1111 41 "b11".U -> 0xff.U //11111111 42 )) << addr(2, 0)).asUInt 43 } 44} 45 46object genVWmask { 47 def apply(addr: UInt, sizeEncode: UInt): UInt = { 48 (LookupTree(sizeEncode, List( 49 "b00".U -> 0x1.U, //0001 << addr(2:0) 50 "b01".U -> 0x3.U, //0011 51 "b10".U -> 0xf.U, //1111 52 "b11".U -> 0xff.U //11111111 53 )) << addr(3, 0)).asUInt 54 } 55} 56 57object genWdata { 58 def apply(data: UInt, sizeEncode: UInt): UInt = { 59 LookupTree(sizeEncode, List( 60 "b00".U -> Fill(16, data(7, 0)), 61 "b01".U -> Fill(8, data(15, 0)), 62 "b10".U -> Fill(4, data(31, 0)), 63 "b11".U -> Fill(2, data(63,0)) 64 )) 65 } 66} 67 68object shiftDataToLow { 69 def apply(addr: UInt,data : UInt): UInt = { 70 Mux(addr(3), (data >> 64).asUInt,data) 71 } 72} 73object shiftMaskToLow { 74 def apply(addr: UInt,mask: UInt): UInt = { 75 Mux(addr(3),(mask >> 8).asUInt,mask) 76 } 77} 78 79class LsPipelineBundle(implicit p: Parameters) extends XSBundle 80 with HasDCacheParameters 81 with HasVLSUParameters { 82 val uop = new DynInst 83 val vaddr = UInt(VAddrBits.W) 84 val paddr = UInt(PAddrBits.W) 85 val gpaddr = UInt(GPAddrBits.W) 86 // val func = UInt(6.W) 87 val mask = UInt((VLEN/8).W) 88 val data = UInt((VLEN+1).W) 89 val wlineflag = Bool() // store write the whole cache line 90 91 val miss = Bool() 92 val tlbMiss = Bool() 93 val ptwBack = Bool() 94 val af = Bool() 95 val mmio = Bool() 96 val atomic = Bool() 97 98 val forwardMask = Vec(VLEN/8, Bool()) 99 val forwardData = Vec(VLEN/8, UInt(8.W)) 100 101 // prefetch 102 val isPrefetch = Bool() 103 val isHWPrefetch = Bool() 104 def isSWPrefetch = isPrefetch && !isHWPrefetch 105 106 // misalignBuffer 107 val isFrmMisAlignBuf = Bool() 108 109 // vector 110 val isvec = Bool() 111 val isLastElem = Bool() 112 val is128bit = Bool() 113 val uop_unit_stride_fof = Bool() 114 val usSecondInv = Bool() 115 val elemIdx = UInt(elemIdxBits.W) 116 val alignedType = UInt(alignTypeBits.W) 117 val mbIndex = UInt(max(vlmBindexBits, vsmBindexBits).W) 118 // val rob_idx_valid = Vec(2,Bool()) 119 // val inner_idx = Vec(2,UInt(3.W)) 120 // val rob_idx = Vec(2,new RobPtr) 121 val reg_offset = UInt(vOffsetBits.W) 122 val elemIdxInsideVd = UInt(elemIdxBits.W) 123 // val offset = Vec(2,UInt(4.W)) 124 val vecActive = Bool() // 1: vector active element or scala mem operation, 0: vector not active element 125 val is_first_ele = Bool() 126 // val flowPtr = new VlflowPtr() // VLFlowQueue ptr 127 // val sflowPtr = new VsFlowPtr() // VSFlowQueue ptr 128 129 // For debug usage 130 val isFirstIssue = Bool() 131 val hasROBEntry = Bool() 132 133 // For load replay 134 val isLoadReplay = Bool() 135 val isFastPath = Bool() 136 val isFastReplay = Bool() 137 val replayCarry = new ReplayCarry(nWays) 138 139 // For dcache miss load 140 val mshrid = UInt(log2Up(cfg.nMissEntries).W) 141 val handledByMSHR = Bool() 142 val replacementUpdated = Bool() 143 val missDbUpdated = Bool() 144 145 val forward_tlDchannel = Bool() 146 val dcacheRequireReplay = Bool() 147 val delayedLoadError = Bool() 148 val lateKill = Bool() 149 val feedbacked = Bool() 150 val ldCancel = ValidUndirectioned(UInt(log2Ceil(LoadPipelineWidth).W)) 151 // loadQueueReplay index. 152 val schedIndex = UInt(log2Up(LoadQueueReplaySize).W) 153} 154 155class LdPrefetchTrainBundle(implicit p: Parameters) extends LsPipelineBundle { 156 val meta_prefetch = UInt(L1PfSourceBits.W) 157 val meta_access = Bool() 158 159 def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false, enable: Bool = true.B) = { 160 if (latch) vaddr := RegEnable(input.vaddr, enable) else vaddr := input.vaddr 161 if (latch) paddr := RegEnable(input.paddr, enable) else paddr := input.paddr 162 if (latch) gpaddr := RegEnable(input.gpaddr, enable) else gpaddr := input.gpaddr 163 if (latch) mask := RegEnable(input.mask, enable) else mask := input.mask 164 if (latch) data := RegEnable(input.data, enable) else data := input.data 165 if (latch) uop := RegEnable(input.uop, enable) else uop := input.uop 166 if (latch) wlineflag := RegEnable(input.wlineflag, enable) else wlineflag := input.wlineflag 167 if (latch) miss := RegEnable(input.miss, enable) else miss := input.miss 168 if (latch) tlbMiss := RegEnable(input.tlbMiss, enable) else tlbMiss := input.tlbMiss 169 if (latch) ptwBack := RegEnable(input.ptwBack, enable) else ptwBack := input.ptwBack 170 if (latch) af := RegEnable(input.af, enable) else af := input.af 171 if (latch) mmio := RegEnable(input.mmio, enable) else mmio := input.mmio 172 if (latch) forwardMask := RegEnable(input.forwardMask, enable) else forwardMask := input.forwardMask 173 if (latch) forwardData := RegEnable(input.forwardData, enable) else forwardData := input.forwardData 174 if (latch) isPrefetch := RegEnable(input.isPrefetch, enable) else isPrefetch := input.isPrefetch 175 if (latch) isHWPrefetch := RegEnable(input.isHWPrefetch, enable) else isHWPrefetch := input.isHWPrefetch 176 if (latch) isFrmMisAlignBuf := RegEnable(input.isFrmMisAlignBuf, enable) else isFrmMisAlignBuf := input.isFrmMisAlignBuf 177 if (latch) isFirstIssue := RegEnable(input.isFirstIssue, enable) else isFirstIssue := input.isFirstIssue 178 if (latch) hasROBEntry := RegEnable(input.hasROBEntry, enable) else hasROBEntry := input.hasROBEntry 179 if (latch) dcacheRequireReplay := RegEnable(input.dcacheRequireReplay, enable) else dcacheRequireReplay := input.dcacheRequireReplay 180 if (latch) schedIndex := RegEnable(input.schedIndex, enable) else schedIndex := input.schedIndex 181 if (latch) isvec := RegEnable(input.isvec, enable) else isvec := input.isvec 182 if (latch) isLastElem := RegEnable(input.isLastElem, enable) else isLastElem := input.isLastElem 183 if (latch) is128bit := RegEnable(input.is128bit, enable) else is128bit := input.is128bit 184 if (latch) vecActive := RegEnable(input.vecActive, enable) else vecActive := input.vecActive 185 if (latch) is_first_ele := RegEnable(input.is_first_ele, enable) else is_first_ele := input.is_first_ele 186 if (latch) uop_unit_stride_fof := RegEnable(input.uop_unit_stride_fof, enable) else uop_unit_stride_fof := input.uop_unit_stride_fof 187 if (latch) usSecondInv := RegEnable(input.usSecondInv, enable) else usSecondInv := input.usSecondInv 188 if (latch) reg_offset := RegEnable(input.reg_offset, enable) else reg_offset := input.reg_offset 189 if (latch) elemIdx := RegEnable(input.elemIdx, enable) else elemIdx := input.elemIdx 190 if (latch) alignedType := RegEnable(input.alignedType, enable) else alignedType := input.alignedType 191 if (latch) mbIndex := RegEnable(input.mbIndex, enable) else mbIndex := input.mbIndex 192 if (latch) elemIdxInsideVd := RegEnable(input.elemIdxInsideVd, enable) else elemIdxInsideVd := input.elemIdxInsideVd 193 // if (latch) flowPtr := RegEnable(input.flowPtr, enable) else flowPtr := input.flowPtr 194 // if (latch) sflowPtr := RegEnable(input.sflowPtr, enable) else sflowPtr := input.sflowPtr 195 196 meta_prefetch := DontCare 197 meta_access := DontCare 198 forward_tlDchannel := DontCare 199 mshrid := DontCare 200 replayCarry := DontCare 201 atomic := DontCare 202 isLoadReplay := DontCare 203 isFastPath := DontCare 204 isFastReplay := DontCare 205 handledByMSHR := DontCare 206 replacementUpdated := DontCare 207 missDbUpdated := DontCare 208 delayedLoadError := DontCare 209 lateKill := DontCare 210 feedbacked := DontCare 211 ldCancel := DontCare 212 } 213 214 def asPrefetchReqBundle(): PrefetchReqBundle = { 215 val res = Wire(new PrefetchReqBundle) 216 res.vaddr := this.vaddr 217 res.paddr := this.paddr 218 res.pc := this.uop.pc 219 res.miss := this.miss 220 221 res 222 } 223} 224 225class StPrefetchTrainBundle(implicit p: Parameters) extends LdPrefetchTrainBundle {} 226 227class LqWriteBundle(implicit p: Parameters) extends LsPipelineBundle { 228 // load inst replay informations 229 val rep_info = new LoadToLsqReplayIO 230 // queue entry data, except flag bits, will be updated if writeQueue is true, 231 // valid bit in LqWriteBundle will be ignored 232 val data_wen_dup = Vec(6, Bool()) // dirty reg dup 233 234 235 def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false, enable: Bool = true.B) = { 236 if(latch) vaddr := RegEnable(input.vaddr, enable) else vaddr := input.vaddr 237 if(latch) paddr := RegEnable(input.paddr, enable) else paddr := input.paddr 238 if(latch) gpaddr := RegEnable(input.gpaddr, enable) else gpaddr := input.gpaddr 239 if(latch) mask := RegEnable(input.mask, enable) else mask := input.mask 240 if(latch) data := RegEnable(input.data, enable) else data := input.data 241 if(latch) uop := RegEnable(input.uop, enable) else uop := input.uop 242 if(latch) wlineflag := RegEnable(input.wlineflag, enable) else wlineflag := input.wlineflag 243 if(latch) miss := RegEnable(input.miss, enable) else miss := input.miss 244 if(latch) tlbMiss := RegEnable(input.tlbMiss, enable) else tlbMiss := input.tlbMiss 245 if(latch) ptwBack := RegEnable(input.ptwBack, enable) else ptwBack := input.ptwBack 246 if(latch) mmio := RegEnable(input.mmio, enable) else mmio := input.mmio 247 if(latch) atomic := RegEnable(input.atomic, enable) else atomic := input.atomic 248 if(latch) forwardMask := RegEnable(input.forwardMask, enable) else forwardMask := input.forwardMask 249 if(latch) forwardData := RegEnable(input.forwardData, enable) else forwardData := input.forwardData 250 if(latch) isPrefetch := RegEnable(input.isPrefetch, enable) else isPrefetch := input.isPrefetch 251 if(latch) isHWPrefetch := RegEnable(input.isHWPrefetch, enable) else isHWPrefetch := input.isHWPrefetch 252 if(latch) isFrmMisAlignBuf := RegEnable(input.isFrmMisAlignBuf, enable) else isFrmMisAlignBuf := input.isFrmMisAlignBuf 253 if(latch) isFirstIssue := RegEnable(input.isFirstIssue, enable) else isFirstIssue := input.isFirstIssue 254 if(latch) hasROBEntry := RegEnable(input.hasROBEntry, enable) else hasROBEntry := input.hasROBEntry 255 if(latch) isLoadReplay := RegEnable(input.isLoadReplay, enable) else isLoadReplay := input.isLoadReplay 256 if(latch) isFastPath := RegEnable(input.isFastPath, enable) else isFastPath := input.isFastPath 257 if(latch) isFastReplay := RegEnable(input.isFastReplay, enable) else isFastReplay := input.isFastReplay 258 if(latch) mshrid := RegEnable(input.mshrid, enable) else mshrid := input.mshrid 259 if(latch) forward_tlDchannel := RegEnable(input.forward_tlDchannel, enable) else forward_tlDchannel := input.forward_tlDchannel 260 if(latch) replayCarry := RegEnable(input.replayCarry, enable) else replayCarry := input.replayCarry 261 if(latch) dcacheRequireReplay := RegEnable(input.dcacheRequireReplay, enable) else dcacheRequireReplay := input.dcacheRequireReplay 262 if(latch) schedIndex := RegEnable(input.schedIndex, enable) else schedIndex := input.schedIndex 263 if(latch) handledByMSHR := RegEnable(input.handledByMSHR, enable) else handledByMSHR := input.handledByMSHR 264 if(latch) replacementUpdated := RegEnable(input.replacementUpdated, enable) else replacementUpdated := input.replacementUpdated 265 if(latch) missDbUpdated := RegEnable(input.missDbUpdated, enable) else missDbUpdated := input.missDbUpdated 266 if(latch) delayedLoadError := RegEnable(input.delayedLoadError, enable) else delayedLoadError := input.delayedLoadError 267 if(latch) lateKill := RegEnable(input.lateKill, enable) else lateKill := input.lateKill 268 if(latch) feedbacked := RegEnable(input.feedbacked, enable) else feedbacked := input.feedbacked 269 if(latch) isvec := RegEnable(input.isvec, enable) else isvec := input.isvec 270 if(latch) is128bit := RegEnable(input.is128bit, enable) else is128bit := input.is128bit 271 if(latch) vecActive := RegEnable(input.vecActive, enable) else vecActive := input.vecActive 272 if(latch) uop_unit_stride_fof := RegEnable(input.uop_unit_stride_fof, enable) else uop_unit_stride_fof := input.uop_unit_stride_fof 273 if(latch) reg_offset := RegEnable(input.reg_offset, enable) else reg_offset := input.reg_offset 274 if(latch) mbIndex := RegEnable(input.mbIndex, enable) else mbIndex := input.mbIndex 275 if(latch) elemIdxInsideVd := RegEnable(input.elemIdxInsideVd, enable) else elemIdxInsideVd := input.elemIdxInsideVd 276 277 rep_info := DontCare 278 data_wen_dup := DontCare 279 } 280} 281 282class SqWriteBundle(implicit p: Parameters) extends LsPipelineBundle { 283 val need_rep = Bool() 284} 285 286class LoadForwardQueryIO(implicit p: Parameters) extends XSBundle { 287 val vaddr = Output(UInt(VAddrBits.W)) 288 val paddr = Output(UInt(PAddrBits.W)) 289 val mask = Output(UInt((VLEN/8).W)) 290 val uop = Output(new DynInst) // for replay 291 val pc = Output(UInt(VAddrBits.W)) //for debug 292 val valid = Output(Bool()) 293 294 val forwardMaskFast = Input(Vec((VLEN/8), Bool())) // resp to load_s1 295 val forwardMask = Input(Vec((VLEN/8), Bool())) // resp to load_s2 296 val forwardData = Input(Vec((VLEN/8), UInt(8.W))) // resp to load_s2 297 298 // val lqIdx = Output(UInt(LoadQueueIdxWidth.W)) 299 val sqIdx = Output(new SqPtr) 300 301 // dataInvalid suggests store to load forward found forward should happen, 302 // but data is not available for now. If dataInvalid, load inst should 303 // be replayed from RS. Feedback type should be RSFeedbackType.dataInvalid 304 val dataInvalid = Input(Bool()) // Addr match, but data is not valid for now 305 306 // matchInvalid suggests in store to load forward logic, paddr cam result does 307 // to equal to vaddr cam result. If matchInvalid, a microarchitectural exception 308 // should be raised to flush SQ and committed sbuffer. 309 val matchInvalid = Input(Bool()) // resp to load_s2 310 311 // addrInvalid suggests store to load forward found forward should happen, 312 // but address (SSID) is not available for now. If addrInvalid, load inst should 313 // be replayed from RS. Feedback type should be RSFeedbackType.addrInvalid 314 val addrInvalid = Input(Bool()) 315} 316 317// LoadForwardQueryIO used in load pipeline 318// 319// Difference between PipeLoadForwardQueryIO and LoadForwardQueryIO: 320// PipeIO use predecoded sqIdxMask for better forward timing 321class PipeLoadForwardQueryIO(implicit p: Parameters) extends LoadForwardQueryIO { 322 // val sqIdx = Output(new SqPtr) // for debug, should not be used in pipeline for timing reasons 323 // sqIdxMask is calcuated in earlier stage for better timing 324 val sqIdxMask = Output(UInt(StoreQueueSize.W)) 325 326 // dataInvalid: addr match, but data is not valid for now 327 val dataInvalidFast = Input(Bool()) // resp to load_s1 328 // val dataInvalid = Input(Bool()) // resp to load_s2 329 val dataInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx 330 val addrInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx 331} 332 333// Query load queue for ld-ld violation 334// 335// Req should be send in load_s1 336// Resp will be generated 1 cycle later 337// 338// Note that query req may be !ready, as dcache is releasing a block 339// If it happens, a replay from rs is needed. 340class LoadNukeQueryReq(implicit p: Parameters) extends XSBundle { // provide lqIdx 341 val uop = new DynInst 342 // mask: load's data mask. 343 val mask = UInt((VLEN/8).W) 344 345 // paddr: load's paddr. 346 val paddr = UInt(PAddrBits.W) 347 // dataInvalid: load data is invalid. 348 val data_valid = Bool() 349} 350 351class LoadNukeQueryResp(implicit p: Parameters) extends XSBundle { 352 // rep_frm_fetch: ld-ld violation check success, replay from fetch. 353 val rep_frm_fetch = Bool() 354} 355 356class LoadNukeQueryIO(implicit p: Parameters) extends XSBundle { 357 val req = Decoupled(new LoadNukeQueryReq) 358 val resp = Flipped(Valid(new LoadNukeQueryResp)) 359 val revoke = Output(Bool()) 360} 361 362class StoreNukeQueryIO(implicit p: Parameters) extends XSBundle { 363 // robIdx: Requestor's (a store instruction) rob index for match logic. 364 val robIdx = new RobPtr 365 366 // paddr: requestor's (a store instruction) physical address for match logic. 367 val paddr = UInt(PAddrBits.W) 368 369 // mask: requestor's (a store instruction) data width mask for match logic. 370 val mask = UInt((VLEN/8).W) 371 372 // matchLine: if store is vector 128-bits, load unit need to compare 128-bits vaddr. 373 val matchLine = Bool() 374} 375 376class StoreMaBufToSqControlIO(implicit p: Parameters) extends XSBundle { 377 // from storeMisalignBuffer to storeQueue, control it's sbuffer write 378 val control = Output(new XSBundle { 379 // control sq to write-into sb 380 val writeSb = Bool() 381 val wdata = UInt(VLEN.W) 382 val wmask = UInt((VLEN / 8).W) 383 val paddr = UInt(PAddrBits.W) 384 val vaddr = UInt(VAddrBits.W) 385 val last = Bool() 386 val hasException = Bool() 387 // remove this entry in sq 388 val removeSq = Bool() 389 }) 390 // from storeQueue to storeMisalignBuffer, provide detail info of this store 391 val storeInfo = Input(new XSBundle { 392 val data = UInt(VLEN.W) 393 // is the data of the unaligned store ready at sq? 394 val dataReady = Bool() 395 // complete a data transfer from sq to sb 396 val completeSbTrans = Bool() 397 }) 398} 399 400// Store byte valid mask write bundle 401// 402// Store byte valid mask write to SQ takes 2 cycles 403class StoreMaskBundle(implicit p: Parameters) extends XSBundle { 404 val sqIdx = new SqPtr 405 val mask = UInt((VLEN/8).W) 406} 407 408class LoadDataFromDcacheBundle(implicit p: Parameters) extends DCacheBundle { 409 // old dcache: optimize data sram read fanout 410 // val bankedDcacheData = Vec(DCacheBanks, UInt(64.W)) 411 // val bank_oh = UInt(DCacheBanks.W) 412 413 // new dcache 414 val respDcacheData = UInt(VLEN.W) 415 val forwardMask = Vec(VLEN/8, Bool()) 416 val forwardData = Vec(VLEN/8, UInt(8.W)) 417 val uop = new DynInst // for data selection, only fwen and fuOpType are used 418 val addrOffset = UInt(4.W) // for data selection 419 420 // forward tilelink D channel 421 val forward_D = Bool() 422 val forwardData_D = Vec(VLEN/8, UInt(8.W)) 423 424 // forward mshr data 425 val forward_mshr = Bool() 426 val forwardData_mshr = Vec(VLEN/8, UInt(8.W)) 427 428 val forward_result_valid = Bool() 429 430 def dcacheData(): UInt = { 431 // old dcache 432 // val dcache_data = Mux1H(bank_oh, bankedDcacheData) 433 // new dcache 434 val dcache_data = respDcacheData 435 val use_D = forward_D && forward_result_valid 436 val use_mshr = forward_mshr && forward_result_valid 437 Mux(use_D, forwardData_D.asUInt, Mux(use_mshr, forwardData_mshr.asUInt, dcache_data)) 438 } 439 440 def mergedData(): UInt = { 441 val rdataVec = VecInit((0 until VLEN / 8).map(j => 442 Mux(forwardMask(j), forwardData(j), dcacheData()(8*(j+1)-1, 8*j)) 443 )) 444 rdataVec.asUInt 445 } 446} 447 448// Load writeback data from load queue (refill) 449class LoadDataFromLQBundle(implicit p: Parameters) extends XSBundle { 450 val lqData = UInt(64.W) // load queue has merged data 451 val uop = new DynInst // for data selection, only fwen and fuOpType are used 452 val addrOffset = UInt(3.W) // for data selection 453 454 def mergedData(): UInt = { 455 lqData 456 } 457} 458 459// Bundle for load / store wait waking up 460class MemWaitUpdateReq(implicit p: Parameters) extends XSBundle { 461 val robIdx = Vec(backendParams.StaExuCnt, ValidIO(new RobPtr)) 462 val sqIdx = Vec(backendParams.StdCnt, ValidIO(new SqPtr)) 463} 464 465object AddPipelineReg { 466 class PipelineRegModule[T <: Data](gen: T) extends Module { 467 val io = IO(new Bundle() { 468 val in = Flipped(DecoupledIO(gen.cloneType)) 469 val out = DecoupledIO(gen.cloneType) 470 val isFlush = Input(Bool()) 471 }) 472 473 val valid = RegInit(false.B) 474 valid.suggestName("pipeline_reg_valid") 475 when (io.out.fire) { valid := false.B } 476 when (io.in.fire) { valid := true.B } 477 when (io.isFlush) { valid := false.B } 478 479 io.in.ready := !valid || io.out.ready 480 io.out.bits := RegEnable(io.in.bits, io.in.fire) 481 io.out.valid := valid //&& !isFlush 482 } 483 484 def apply[T <: Data] 485 (left: DecoupledIO[T], right: DecoupledIO[T], isFlush: Bool, 486 moduleName: Option[String] = None 487 ): Unit = { 488 val pipelineReg = Module(new PipelineRegModule[T](left.bits.cloneType)) 489 if(moduleName.nonEmpty) pipelineReg.suggestName(moduleName.get) 490 pipelineReg.io.in <> left 491 right <> pipelineReg.io.out 492 pipelineReg.io.isFlush := isFlush 493 } 494}