1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import utility._ 24import utils._ 25import xiangshan._ 26import xiangshan.backend.Bundles.{DynInst, MemExuInput} 27import xiangshan.backend.rob.RobPtr 28import xiangshan.cache._ 29import xiangshan.backend.fu.FenceToSbuffer 30import xiangshan.cache.wpu.ReplayCarry 31import xiangshan.mem.prefetch.PrefetchReqBundle 32import math._ 33 34object genWmask { 35 def apply(addr: UInt, sizeEncode: UInt): UInt = { 36 (LookupTree(sizeEncode, List( 37 "b00".U -> 0x1.U, //0001 << addr(2:0) 38 "b01".U -> 0x3.U, //0011 39 "b10".U -> 0xf.U, //1111 40 "b11".U -> 0xff.U //11111111 41 )) << addr(2, 0)).asUInt 42 } 43} 44 45object genVWmask { 46 def apply(addr: UInt, sizeEncode: UInt): UInt = { 47 (LookupTree(sizeEncode, List( 48 "b00".U -> 0x1.U, //0001 << addr(2:0) 49 "b01".U -> 0x3.U, //0011 50 "b10".U -> 0xf.U, //1111 51 "b11".U -> 0xff.U //11111111 52 )) << addr(3, 0)).asUInt 53 } 54} 55 56object genWdata { 57 def apply(data: UInt, sizeEncode: UInt): UInt = { 58 LookupTree(sizeEncode, List( 59 "b00".U -> Fill(16, data(7, 0)), 60 "b01".U -> Fill(8, data(15, 0)), 61 "b10".U -> Fill(4, data(31, 0)), 62 "b11".U -> Fill(2, data(63,0)) 63 )) 64 } 65} 66 67object shiftDataToLow { 68 def apply(addr: UInt,data : UInt): UInt = { 69 Mux(addr(3), (data >> 64).asUInt,data) 70 } 71} 72object shiftMaskToLow { 73 def apply(addr: UInt,mask: UInt): UInt = { 74 Mux(addr(3),(mask >> 8).asUInt,mask) 75 } 76} 77 78class LsPipelineBundle(implicit p: Parameters) extends XSBundle 79 with HasDCacheParameters 80 with HasVLSUParameters { 81 val uop = new DynInst 82 val vaddr = UInt(VAddrBits.W) 83 val paddr = UInt(PAddrBits.W) 84 // val func = UInt(6.W) 85 val mask = UInt((VLEN/8).W) 86 val data = UInt((VLEN+1).W) 87 val wlineflag = Bool() // store write the whole cache line 88 89 val miss = Bool() 90 val tlbMiss = Bool() 91 val ptwBack = Bool() 92 val mmio = Bool() 93 val atomic = Bool() 94 val rsIdx = UInt(log2Up(MemIQSizeMax).W) 95 96 val forwardMask = Vec(VLEN/8, Bool()) 97 val forwardData = Vec(VLEN/8, UInt(8.W)) 98 99 // prefetch 100 val isPrefetch = Bool() 101 val isHWPrefetch = Bool() 102 def isSWPrefetch = isPrefetch && !isHWPrefetch 103 104 // vector 105 val isvec = Bool() 106 val isLastElem = Bool() 107 val is128bit = Bool() 108 val uop_unit_stride_fof = Bool() 109 val usSecondInv = Bool() 110 val elemIdx = UInt(elemIdxBits.W) 111 val alignedType = UInt(alignTypeBits.W) 112 val mbIndex = UInt(max(vlmBindexBits, vsmBindexBits).W) 113 // val rob_idx_valid = Vec(2,Bool()) 114 // val inner_idx = Vec(2,UInt(3.W)) 115 // val rob_idx = Vec(2,new RobPtr) 116 val reg_offset = UInt(vOffsetBits.W) 117 val elemIdxInsideVd = UInt(elemIdxBits.W) 118 // val offset = Vec(2,UInt(4.W)) 119 val vecActive = Bool() // 1: vector active element or scala mem operation, 0: vector not active element 120 val is_first_ele = Bool() 121 // val flowPtr = new VlflowPtr() // VLFlowQueue ptr 122 // val sflowPtr = new VsFlowPtr() // VSFlowQueue ptr 123 124 // For debug usage 125 val isFirstIssue = Bool() 126 val hasROBEntry = Bool() 127 128 // For load replay 129 val isLoadReplay = Bool() 130 val isFastPath = Bool() 131 val isFastReplay = Bool() 132 val replayCarry = new ReplayCarry(nWays) 133 134 // For dcache miss load 135 val mshrid = UInt(log2Up(cfg.nMissEntries).W) 136 val handledByMSHR = Bool() 137 val replacementUpdated = Bool() 138 val missDbUpdated = Bool() 139 140 val forward_tlDchannel = Bool() 141 val dcacheRequireReplay = Bool() 142 val delayedLoadError = Bool() 143 val lateKill = Bool() 144 val feedbacked = Bool() 145 val ldCancel = ValidUndirectioned(UInt(log2Ceil(LoadPipelineWidth).W)) 146 // loadQueueReplay index. 147 val schedIndex = UInt(log2Up(LoadQueueReplaySize).W) 148} 149 150class LdPrefetchTrainBundle(implicit p: Parameters) extends LsPipelineBundle { 151 val meta_prefetch = UInt(L1PfSourceBits.W) 152 val meta_access = Bool() 153 154 def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false) = { 155 if (latch) vaddr := RegNext(input.vaddr) else vaddr := input.vaddr 156 if (latch) paddr := RegNext(input.paddr) else paddr := input.paddr 157 if (latch) mask := RegNext(input.mask) else mask := input.mask 158 if (latch) data := RegNext(input.data) else data := input.data 159 if (latch) uop := RegNext(input.uop) else uop := input.uop 160 if (latch) wlineflag := RegNext(input.wlineflag) else wlineflag := input.wlineflag 161 if (latch) miss := RegNext(input.miss) else miss := input.miss 162 if (latch) tlbMiss := RegNext(input.tlbMiss) else tlbMiss := input.tlbMiss 163 if (latch) ptwBack := RegNext(input.ptwBack) else ptwBack := input.ptwBack 164 if (latch) mmio := RegNext(input.mmio) else mmio := input.mmio 165 if (latch) rsIdx := RegNext(input.rsIdx) else rsIdx := input.rsIdx 166 if (latch) forwardMask := RegNext(input.forwardMask) else forwardMask := input.forwardMask 167 if (latch) forwardData := RegNext(input.forwardData) else forwardData := input.forwardData 168 if (latch) isPrefetch := RegNext(input.isPrefetch) else isPrefetch := input.isPrefetch 169 if (latch) isHWPrefetch := RegNext(input.isHWPrefetch) else isHWPrefetch := input.isHWPrefetch 170 if (latch) isFirstIssue := RegNext(input.isFirstIssue) else isFirstIssue := input.isFirstIssue 171 if (latch) hasROBEntry := RegNext(input.hasROBEntry) else hasROBEntry := input.hasROBEntry 172 if (latch) dcacheRequireReplay := RegNext(input.dcacheRequireReplay) else dcacheRequireReplay := input.dcacheRequireReplay 173 if (latch) schedIndex := RegNext(input.schedIndex) else schedIndex := input.schedIndex 174 if (latch) isvec := RegNext(input.isvec) else isvec := input.isvec 175 if (latch) isLastElem := RegNext(input.isLastElem) else isLastElem := input.isLastElem 176 if (latch) is128bit := RegNext(input.is128bit) else is128bit := input.is128bit 177 if (latch) vecActive := RegNext(input.vecActive) else vecActive := input.vecActive 178 if (latch) is_first_ele := RegNext(input.is_first_ele) else is_first_ele := input.is_first_ele 179 if (latch) uop_unit_stride_fof := RegNext(input.uop_unit_stride_fof) else uop_unit_stride_fof := input.uop_unit_stride_fof 180 if (latch) usSecondInv := RegNext(input.usSecondInv) else usSecondInv := input.usSecondInv 181 if (latch) reg_offset := RegNext(input.reg_offset) else reg_offset := input.reg_offset 182 if (latch) elemIdx := RegNext(input.elemIdx) else elemIdx := input.elemIdx 183 if (latch) alignedType := RegNext(input.alignedType) else alignedType := input.alignedType 184 if (latch) mbIndex := RegNext(input.mbIndex) else mbIndex := input.mbIndex 185 if(latch) elemIdxInsideVd := RegNext(input.elemIdxInsideVd) else elemIdxInsideVd := input.elemIdxInsideVd 186 // if (latch) flowPtr := RegNext(input.flowPtr) else flowPtr := input.flowPtr 187 // if (latch) sflowPtr := RegNext(input.sflowPtr) else sflowPtr := input.sflowPtr 188 189 meta_prefetch := DontCare 190 meta_access := DontCare 191 forward_tlDchannel := DontCare 192 mshrid := DontCare 193 replayCarry := DontCare 194 atomic := DontCare 195 isLoadReplay := DontCare 196 isFastPath := DontCare 197 isFastReplay := DontCare 198 handledByMSHR := DontCare 199 replacementUpdated := DontCare 200 missDbUpdated := DontCare 201 delayedLoadError := DontCare 202 lateKill := DontCare 203 feedbacked := DontCare 204 ldCancel := DontCare 205 } 206 207 def asPrefetchReqBundle(): PrefetchReqBundle = { 208 val res = Wire(new PrefetchReqBundle) 209 res.vaddr := this.vaddr 210 res.paddr := this.paddr 211 res.pc := this.uop.pc 212 213 res 214 } 215} 216 217class StPrefetchTrainBundle(implicit p: Parameters) extends LdPrefetchTrainBundle {} 218 219class LqWriteBundle(implicit p: Parameters) extends LsPipelineBundle { 220 // load inst replay informations 221 val rep_info = new LoadToLsqReplayIO 222 // queue entry data, except flag bits, will be updated if writeQueue is true, 223 // valid bit in LqWriteBundle will be ignored 224 val data_wen_dup = Vec(6, Bool()) // dirty reg dup 225 226 227 def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false) = { 228 if(latch) vaddr := RegNext(input.vaddr) else vaddr := input.vaddr 229 if(latch) paddr := RegNext(input.paddr) else paddr := input.paddr 230 if(latch) mask := RegNext(input.mask) else mask := input.mask 231 if(latch) data := RegNext(input.data) else data := input.data 232 if(latch) uop := RegNext(input.uop) else uop := input.uop 233 if(latch) wlineflag := RegNext(input.wlineflag) else wlineflag := input.wlineflag 234 if(latch) miss := RegNext(input.miss) else miss := input.miss 235 if(latch) tlbMiss := RegNext(input.tlbMiss) else tlbMiss := input.tlbMiss 236 if(latch) ptwBack := RegNext(input.ptwBack) else ptwBack := input.ptwBack 237 if(latch) mmio := RegNext(input.mmio) else mmio := input.mmio 238 if(latch) atomic := RegNext(input.atomic) else atomic := input.atomic 239 if(latch) rsIdx := RegNext(input.rsIdx) else rsIdx := input.rsIdx 240 if(latch) forwardMask := RegNext(input.forwardMask) else forwardMask := input.forwardMask 241 if(latch) forwardData := RegNext(input.forwardData) else forwardData := input.forwardData 242 if(latch) isPrefetch := RegNext(input.isPrefetch) else isPrefetch := input.isPrefetch 243 if(latch) isHWPrefetch := RegNext(input.isHWPrefetch) else isHWPrefetch := input.isHWPrefetch 244 if(latch) isFirstIssue := RegNext(input.isFirstIssue) else isFirstIssue := input.isFirstIssue 245 if(latch) hasROBEntry := RegNext(input.hasROBEntry) else hasROBEntry := input.hasROBEntry 246 if(latch) isLoadReplay := RegNext(input.isLoadReplay) else isLoadReplay := input.isLoadReplay 247 if(latch) isFastPath := RegNext(input.isFastPath) else isFastPath := input.isFastPath 248 if(latch) isFastReplay := RegNext(input.isFastReplay) else isFastReplay := input.isFastReplay 249 if(latch) mshrid := RegNext(input.mshrid) else mshrid := input.mshrid 250 if(latch) forward_tlDchannel := RegNext(input.forward_tlDchannel) else forward_tlDchannel := input.forward_tlDchannel 251 if(latch) replayCarry := RegNext(input.replayCarry) else replayCarry := input.replayCarry 252 if(latch) dcacheRequireReplay := RegNext(input.dcacheRequireReplay) else dcacheRequireReplay := input.dcacheRequireReplay 253 if(latch) schedIndex := RegNext(input.schedIndex) else schedIndex := input.schedIndex 254 if(latch) handledByMSHR := RegNext(input.handledByMSHR) else handledByMSHR := input.handledByMSHR 255 if(latch) replacementUpdated := RegNext(input.replacementUpdated) else replacementUpdated := input.replacementUpdated 256 if(latch) missDbUpdated := RegNext(input.missDbUpdated) else missDbUpdated := input.missDbUpdated 257 if(latch) delayedLoadError := RegNext(input.delayedLoadError) else delayedLoadError := input.delayedLoadError 258 if(latch) lateKill := RegNext(input.lateKill) else lateKill := input.lateKill 259 if(latch) feedbacked := RegNext(input.feedbacked) else feedbacked := input.feedbacked 260 if(latch) isvec := RegNext(input.isvec) else isvec := input.isvec 261 if(latch) is128bit := RegNext(input.is128bit) else is128bit := input.is128bit 262 if(latch) vecActive := RegNext(input.vecActive) else vecActive := input.vecActive 263 if(latch) uop_unit_stride_fof := RegNext(input.uop_unit_stride_fof) else uop_unit_stride_fof := input.uop_unit_stride_fof 264 if(latch) reg_offset := RegNext(input.reg_offset) else reg_offset := input.reg_offset 265 if(latch) mbIndex := RegNext(input.mbIndex) else mbIndex := input.mbIndex 266 if(latch) elemIdxInsideVd := RegNext(input.elemIdxInsideVd) else elemIdxInsideVd := input.elemIdxInsideVd 267 268 rep_info := DontCare 269 data_wen_dup := DontCare 270 } 271} 272 273class LoadForwardQueryIO(implicit p: Parameters) extends XSBundle { 274 val vaddr = Output(UInt(VAddrBits.W)) 275 val paddr = Output(UInt(PAddrBits.W)) 276 val mask = Output(UInt((VLEN/8).W)) 277 val uop = Output(new DynInst) // for replay 278 val pc = Output(UInt(VAddrBits.W)) //for debug 279 val valid = Output(Bool()) 280 281 val forwardMaskFast = Input(Vec((VLEN/8), Bool())) // resp to load_s1 282 val forwardMask = Input(Vec((VLEN/8), Bool())) // resp to load_s2 283 val forwardData = Input(Vec((VLEN/8), UInt(8.W))) // resp to load_s2 284 285 // val lqIdx = Output(UInt(LoadQueueIdxWidth.W)) 286 val sqIdx = Output(new SqPtr) 287 288 // dataInvalid suggests store to load forward found forward should happen, 289 // but data is not available for now. If dataInvalid, load inst should 290 // be replayed from RS. Feedback type should be RSFeedbackType.dataInvalid 291 val dataInvalid = Input(Bool()) // Addr match, but data is not valid for now 292 293 // matchInvalid suggests in store to load forward logic, paddr cam result does 294 // to equal to vaddr cam result. If matchInvalid, a microarchitectural exception 295 // should be raised to flush SQ and committed sbuffer. 296 val matchInvalid = Input(Bool()) // resp to load_s2 297 298 // addrInvalid suggests store to load forward found forward should happen, 299 // but address (SSID) is not available for now. If addrInvalid, load inst should 300 // be replayed from RS. Feedback type should be RSFeedbackType.addrInvalid 301 val addrInvalid = Input(Bool()) 302} 303 304// LoadForwardQueryIO used in load pipeline 305// 306// Difference between PipeLoadForwardQueryIO and LoadForwardQueryIO: 307// PipeIO use predecoded sqIdxMask for better forward timing 308class PipeLoadForwardQueryIO(implicit p: Parameters) extends LoadForwardQueryIO { 309 // val sqIdx = Output(new SqPtr) // for debug, should not be used in pipeline for timing reasons 310 // sqIdxMask is calcuated in earlier stage for better timing 311 val sqIdxMask = Output(UInt(StoreQueueSize.W)) 312 313 // dataInvalid: addr match, but data is not valid for now 314 val dataInvalidFast = Input(Bool()) // resp to load_s1 315 // val dataInvalid = Input(Bool()) // resp to load_s2 316 val dataInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx 317 val addrInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx 318} 319 320// Query load queue for ld-ld violation 321// 322// Req should be send in load_s1 323// Resp will be generated 1 cycle later 324// 325// Note that query req may be !ready, as dcache is releasing a block 326// If it happens, a replay from rs is needed. 327class LoadNukeQueryReq(implicit p: Parameters) extends XSBundle { // provide lqIdx 328 val uop = new DynInst 329 // mask: load's data mask. 330 val mask = UInt((VLEN/8).W) 331 332 // paddr: load's paddr. 333 val paddr = UInt(PAddrBits.W) 334 // dataInvalid: load data is invalid. 335 val data_valid = Bool() 336} 337 338class LoadNukeQueryResp(implicit p: Parameters) extends XSBundle { 339 // rep_frm_fetch: ld-ld violation check success, replay from fetch. 340 val rep_frm_fetch = Bool() 341} 342 343class LoadNukeQueryIO(implicit p: Parameters) extends XSBundle { 344 val req = Decoupled(new LoadNukeQueryReq) 345 val resp = Flipped(Valid(new LoadNukeQueryResp)) 346 val revoke = Output(Bool()) 347} 348 349class StoreNukeQueryIO(implicit p: Parameters) extends XSBundle { 350 // robIdx: Requestor's (a store instruction) rob index for match logic. 351 val robIdx = new RobPtr 352 353 // paddr: requestor's (a store instruction) physical address for match logic. 354 val paddr = UInt(PAddrBits.W) 355 356 // mask: requestor's (a store instruction) data width mask for match logic. 357 val mask = UInt((VLEN/8).W) 358} 359 360// Store byte valid mask write bundle 361// 362// Store byte valid mask write to SQ takes 2 cycles 363class StoreMaskBundle(implicit p: Parameters) extends XSBundle { 364 val sqIdx = new SqPtr 365 val mask = UInt((VLEN/8).W) 366} 367 368class LoadDataFromDcacheBundle(implicit p: Parameters) extends DCacheBundle { 369 // old dcache: optimize data sram read fanout 370 // val bankedDcacheData = Vec(DCacheBanks, UInt(64.W)) 371 // val bank_oh = UInt(DCacheBanks.W) 372 373 // new dcache 374 val respDcacheData = UInt(VLEN.W) 375 val forwardMask = Vec(VLEN/8, Bool()) 376 val forwardData = Vec(VLEN/8, UInt(8.W)) 377 val uop = new DynInst // for data selection, only fwen and fuOpType are used 378 val addrOffset = UInt(4.W) // for data selection 379 380 // forward tilelink D channel 381 val forward_D = Bool() 382 val forwardData_D = Vec(VLEN/8, UInt(8.W)) 383 384 // forward mshr data 385 val forward_mshr = Bool() 386 val forwardData_mshr = Vec(VLEN/8, UInt(8.W)) 387 388 val forward_result_valid = Bool() 389 390 def dcacheData(): UInt = { 391 // old dcache 392 // val dcache_data = Mux1H(bank_oh, bankedDcacheData) 393 // new dcache 394 val dcache_data = respDcacheData 395 val use_D = forward_D && forward_result_valid 396 val use_mshr = forward_mshr && forward_result_valid 397 Mux(use_D, forwardData_D.asUInt, Mux(use_mshr, forwardData_mshr.asUInt, dcache_data)) 398 } 399 400 def mergedData(): UInt = { 401 val rdataVec = VecInit((0 until VLEN / 8).map(j => 402 Mux(forwardMask(j), forwardData(j), dcacheData()(8*(j+1)-1, 8*j)) 403 )) 404 rdataVec.asUInt 405 } 406} 407 408// Load writeback data from load queue (refill) 409class LoadDataFromLQBundle(implicit p: Parameters) extends XSBundle { 410 val lqData = UInt(64.W) // load queue has merged data 411 val uop = new DynInst // for data selection, only fwen and fuOpType are used 412 val addrOffset = UInt(3.W) // for data selection 413 414 def mergedData(): UInt = { 415 lqData 416 } 417} 418 419// Bundle for load / store wait waking up 420class MemWaitUpdateReq(implicit p: Parameters) extends XSBundle { 421 val robIdx = Vec(backendParams.StaExuCnt, ValidIO(new RobPtr)) 422 val sqIdx = Vec(backendParams.StdCnt, ValidIO(new SqPtr)) 423} 424 425object AddPipelineReg { 426 class PipelineRegModule[T <: Data](gen: T) extends Module { 427 val io = IO(new Bundle() { 428 val in = Flipped(DecoupledIO(gen.cloneType)) 429 val out = DecoupledIO(gen.cloneType) 430 val isFlush = Input(Bool()) 431 }) 432 433 val valid = RegInit(false.B) 434 valid.suggestName("pipeline_reg_valid") 435 when (io.out.fire) { valid := false.B } 436 when (io.in.fire) { valid := true.B } 437 when (io.isFlush) { valid := false.B } 438 439 io.in.ready := !valid || io.out.ready 440 io.out.bits := RegEnable(io.in.bits, io.in.fire) 441 io.out.valid := valid //&& !isFlush 442 } 443 444 def apply[T <: Data] 445 (left: DecoupledIO[T], right: DecoupledIO[T], isFlush: Bool, 446 moduleName: Option[String] = None 447 ){ 448 val pipelineReg = Module(new PipelineRegModule[T](left.bits.cloneType)) 449 if(moduleName.nonEmpty) pipelineReg.suggestName(moduleName.get) 450 pipelineReg.io.in <> left 451 right <> pipelineReg.io.out 452 pipelineReg.io.isFlush := isFlush 453 } 454} 455