1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.frontend.icache 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.tilelink._ 23import utils._ 24import xiangshan.cache.mmu._ 25import xiangshan.frontend._ 26import xiangshan.backend.fu.{PMPReqBundle, PMPRespBundle} 27import huancun.{PreferCacheKey} 28 29 30abstract class IPrefetchBundle(implicit p: Parameters) extends ICacheBundle 31abstract class IPrefetchModule(implicit p: Parameters) extends ICacheModule 32 33class PIQReq(implicit p: Parameters) extends IPrefetchBundle { 34 val paddr = UInt(PAddrBits.W) 35} 36 37 38class IPrefetchToMissUnit(implicit p: Parameters) extends IPrefetchBundle{ 39 val enqReq = DecoupledIO(new PIQReq) 40} 41 42class IPredfetchIO(implicit p: Parameters) extends IPrefetchBundle { 43 val fromFtq = Flipped(new FtqPrefechBundle) 44 val iTLBInter = new TlbRequestIO 45 val pmp = new ICachePMPBundle 46 val toIMeta = Decoupled(new ICacheReadBundle) 47 val fromIMeta = Input(new ICacheMetaRespBundle) 48 val toMissUnit = new IPrefetchToMissUnit 49 val fromMSHR = Flipped(Vec(PortNumber,ValidIO(UInt(PAddrBits.W)))) 50 51 val prefetchEnable = Input(Bool()) 52 val prefetchDisable = Input(Bool()) 53} 54 55class IPrefetchPipe(implicit p: Parameters) extends IPrefetchModule 56{ 57 val io = IO(new IPredfetchIO) 58 59 val enableBit = RegInit(false.B) 60 val maxPrefetchCoutner = RegInit(0.U(log2Ceil(nPrefetchEntries + 1).W)) 61 62 val reachMaxSize = maxPrefetchCoutner === nPrefetchEntries.U 63 64 when(io.prefetchEnable){ 65 enableBit := true.B 66 }.elsewhen((enableBit && io.prefetchDisable) || (enableBit && reachMaxSize)){ 67 enableBit := false.B 68 } 69 70 class PrefetchDir(implicit p: Parameters) extends IPrefetchBundle 71 { 72 val valid = Bool() 73 val paddr = UInt(PAddrBits.W) 74 } 75 76 val prefetch_dir = RegInit(VecInit(Seq.fill(nPrefetchEntries)(0.U.asTypeOf(new PrefetchDir)))) 77 78 val fromFtq = io.fromFtq 79 val (toITLB, fromITLB) = (io.iTLBInter.req, io.iTLBInter.resp) 80 val (toIMeta, fromIMeta) = (io.toIMeta, io.fromIMeta.metaData(0)) 81 val (toPMP, fromPMP) = (io.pmp.req, io.pmp.resp) 82 val toMissUnit = io.toMissUnit 83 84 val p0_fire, p1_fire, p2_fire, p3_fire = WireInit(false.B) 85 val p1_discard, p2_discard, p3_discard = WireInit(false.B) 86 val p0_ready, p1_ready, p2_ready, p3_ready = WireInit(false.B) 87 88 /** Prefetch Stage 0: req from Ftq */ 89 val p0_valid = fromFtq.req.valid 90 val p0_vaddr = addrAlign(fromFtq.req.bits.target, blockBytes, VAddrBits) 91 p0_fire := p0_valid && p1_ready && toITLB.fire() && !fromITLB.bits.miss && toIMeta.ready && enableBit 92 //discard req when source not ready 93 // p0_discard := p0_valid && ((toITLB.fire() && fromITLB.bits.miss) || !toIMeta.ready || !enableBit) 94 95 toIMeta.valid := p0_valid 96 toIMeta.bits.vSetIdx(0) := get_idx(p0_vaddr) 97 98 toIMeta.bits.vSetIdx(1) := DontCare 99 toIMeta.bits.isDoubleLine := false.B 100 101 toITLB.valid := p0_valid 102 toITLB.bits.size := 3.U // TODO: fix the size 103 toITLB.bits.vaddr := p0_vaddr 104 toITLB.bits.debug.pc := p0_vaddr 105 106 toITLB.bits.kill := DontCare 107 toITLB.bits.cmd := TlbCmd.exec 108 toITLB.bits.debug.robIdx := DontCare 109 toITLB.bits.debug.isFirstIssue := DontCare 110 111 112 fromITLB.ready := true.B 113 114 fromFtq.req.ready := true.B //(!enableBit || (enableBit && p3_ready)) && toIMeta.ready //&& GTimer() > 500.U 115 116 /** Prefetch Stage 1: cache probe filter */ 117 val p1_valid = generatePipeControl(lastFire = p0_fire, thisFire = p1_fire || p1_discard, thisFlush = false.B, lastFlush = false.B) 118 119 val p1_vaddr = RegEnable(p0_vaddr, p0_fire) 120 121 //tlb resp 122 val tlb_resp_valid = RegInit(false.B) 123 when(p0_fire) {tlb_resp_valid := true.B} 124 .elsewhen(tlb_resp_valid && (p1_fire || p1_discard)) {tlb_resp_valid := false.B} 125 126 val tlb_resp_paddr = ResultHoldBypass(valid = RegNext(p0_fire), data = fromITLB.bits.paddr) 127 val tlb_resp_pf = ResultHoldBypass(valid = RegNext(p0_fire), data = fromITLB.bits.excp.pf.instr && tlb_resp_valid) 128 val tlb_resp_af = ResultHoldBypass(valid = RegNext(p0_fire), data = fromITLB.bits.excp.af.instr && tlb_resp_valid) 129 130 val p1_exception = VecInit(Seq(tlb_resp_pf, tlb_resp_af)) 131 val p1_has_except = p1_exception.reduce(_ || _) 132 133 val p1_ptag = get_phy_tag(tlb_resp_paddr) 134 135 val p1_meta_ptags = ResultHoldBypass(data = VecInit(fromIMeta.map(way => way.tag)),valid = RegNext(p0_fire)) 136 val p1_meta_cohs = ResultHoldBypass(data = VecInit(fromIMeta.map(way => way.coh)),valid = RegNext(p0_fire)) 137 138 val p1_tag_eq_vec = VecInit(p1_meta_ptags.map(_ === p1_ptag )) 139 val p1_tag_match_vec = VecInit(p1_tag_eq_vec.zipWithIndex.map{ case(way_tag_eq, w) => way_tag_eq && p1_meta_cohs(w).isValid()}) 140 val p1_tag_match = ParallelOR(p1_tag_match_vec) 141 val (p1_hit, p1_miss) = (p1_valid && p1_tag_match && !p1_has_except, p1_valid && !p1_tag_match && !p1_has_except) 142 143 //overriding the invalid req 144 val p1_req_cancle = (p1_hit || (tlb_resp_valid && p1_exception.reduce(_ || _))) && p1_valid 145 val p1_req_accept = p1_valid && tlb_resp_valid && p1_miss 146 147 p1_ready := p1_fire || p1_req_cancle || !p1_valid 148 p1_fire := p1_valid && p1_req_accept && p2_ready && enableBit 149 p1_discard := p1_valid && p1_req_cancle 150 151 /** Prefetch Stage 2: filtered req PIQ enqueue */ 152 val p2_valid = generatePipeControl(lastFire = p1_fire, thisFire = p2_fire || p2_discard, thisFlush = false.B, lastFlush = false.B) 153 val p2_pmp_fire = p2_valid 154 val pmpExcpAF = fromPMP.instr 155 156 val p2_paddr = RegEnable(tlb_resp_paddr, p1_fire) 157 val p2_except_pf = RegEnable(tlb_resp_pf, p1_fire) 158 val p2_except_af = DataHoldBypass(pmpExcpAF, p2_pmp_fire) || RegEnable(tlb_resp_af, p1_fire) 159 val p2_mmio = DataHoldBypass(io.pmp.resp.mmio && !p2_except_af && !p2_except_pf, p2_pmp_fire) 160 161 /*when a prefetch req meet with a miss req in MSHR cancle the prefetch req */ 162 val p2_check_in_mshr = VecInit(io.fromMSHR.map(mshr => mshr.valid && mshr.bits === addrAlign(p2_paddr, blockBytes, PAddrBits))).reduce(_||_) 163 164 //TODO wait PMP logic 165 val p2_exception = VecInit(Seq(pmpExcpAF, p2_mmio)).reduce(_||_) 166 167 io.pmp.req.valid := p2_pmp_fire 168 io.pmp.req.bits.addr := p2_paddr 169 io.pmp.req.bits.size := 3.U 170 io.pmp.req.bits.cmd := TlbCmd.exec 171 172 p2_ready := p2_fire || p2_discard || !p2_valid 173 p2_fire := p2_valid && !p2_exception && p3_ready && p2_pmp_fire 174 p2_discard := p2_valid && (p2_exception && p2_pmp_fire) 175 176 /** Prefetch Stage 2: filtered req PIQ enqueue */ 177 val p3_valid = generatePipeControl(lastFire = p2_fire, thisFire = p3_fire || p3_discard, thisFlush = false.B, lastFlush = false.B) 178 179 val p3_paddr = RegEnable(p2_paddr, p2_fire) 180 val p3_check_in_mshr = RegEnable(p2_check_in_mshr, p2_fire) 181 182 val p3_hit_dir = VecInit((0 until nPrefetchEntries).map(i => prefetch_dir(i).valid && prefetch_dir(i).paddr === p3_paddr )).reduce(_||_) 183 184 p3_discard := p3_hit_dir || p3_check_in_mshr || (p3_valid && enableBit && !toMissUnit.enqReq.ready) 185 186 toMissUnit.enqReq.valid := p3_valid && enableBit && !p3_discard 187 toMissUnit.enqReq.bits.paddr := p3_paddr 188 189 when(reachMaxSize){ 190 maxPrefetchCoutner := 0.U 191 192 prefetch_dir.foreach(_.valid := false.B) 193 }.elsewhen(toMissUnit.enqReq.fire()){ 194 maxPrefetchCoutner := maxPrefetchCoutner + 1.U 195 196 prefetch_dir(maxPrefetchCoutner).valid := true.B 197 prefetch_dir(maxPrefetchCoutner).paddr := p3_paddr 198 } 199 200 p3_ready := toMissUnit.enqReq.ready || !enableBit 201 p3_fire := toMissUnit.enqReq.fire() 202 203} 204 205class IPrefetchEntry(edge: TLEdgeOut, id: Int)(implicit p: Parameters) extends ICacheMissUnitModule 206{ 207 val io = IO(new Bundle { 208 val id = Input(UInt(log2Ceil(PortNumber + nPrefetchEntries).W)) 209 210 val req = Flipped(DecoupledIO(new PIQReq)) 211 212 //tilelink channel 213 val mem_hint = DecoupledIO(new TLBundleA(edge.bundle)) 214 val mem_hint_ack = Flipped(DecoupledIO(new TLBundleD(edge.bundle))) 215 216 }) 217 218 /** default value for control signals */ 219 io.mem_hint.bits := DontCare 220 io.mem_hint_ack.ready := true.B 221 222 223 val s_idle :: s_send_hint :: s_wait_hint_ack :: Nil = Enum(3) 224 val state = RegInit(s_idle) 225 /** control logic transformation */ 226 //request register 227 val req = Reg(new PIQReq) 228 //initial 229 io.mem_hint.bits := DontCare 230 io.mem_hint_ack.ready := true.B 231 232 io.req.ready := (state === s_idle) 233 io.mem_hint.valid := (state === s_send_hint) 234 235 //state change 236 switch(state) { 237 is(s_idle) { 238 when(io.req.fire()) { 239 state := s_send_hint 240 req := io.req.bits 241 } 242 } 243 244 // memory request 245 is(s_send_hint) { 246 when(io.mem_hint.fire()) { 247 state := s_idle 248 } 249 } 250 } 251 252 /** refill write and meta write */ 253 val hint = edge.Hint( 254 fromSource = io.id, 255 toAddress = addrAlign(req.paddr, blockBytes, PAddrBits) + blockBytes.U, 256 lgSize = (log2Up(cacheParams.blockBytes)).U, 257 param = TLHints.PREFETCH_READ 258 )._2 259 io.mem_hint.bits := hint 260 io.mem_hint.bits.user.lift(PreferCacheKey).foreach(_ := true.B) 261 262 263 XSPerfAccumulate("PrefetchEntryReq" + Integer.toString(id, 10), io.req.fire()) 264 265} 266