1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.frontend.icache 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import difftest._ 23import freechips.rocketchip.tilelink._ 24import utils._ 25import xiangshan.cache.mmu._ 26import xiangshan.frontend._ 27import xiangshan.backend.fu.{PMPReqBundle, PMPRespBundle} 28import huancun.PreferCacheKey 29import xiangshan.XSCoreParamsKey 30import utility._ 31 32abstract class IPrefetchBundle(implicit p: Parameters) extends ICacheBundle 33abstract class IPrefetchModule(implicit p: Parameters) extends ICacheModule 34 35class IPrefetchIO(implicit p: Parameters) extends IPrefetchBundle { 36 // control 37 val csr_pf_enable = Input(Bool()) 38 val flush = Input(Bool()) 39 40 val ftqReq = Flipped(new FtqToPrefetchIO) 41 val itlb = Vec(PortNumber, new TlbRequestIO) 42 val pmp = Vec(PortNumber, new ICachePMPBundle) 43 val metaRead = new ICacheMetaReqBundle 44 val MSHRReq = DecoupledIO(new ICacheMissReq) 45 val MSHRResp = Flipped(ValidIO(new ICacheMissResp)) 46 val wayLookupWrite = DecoupledIO(new WayLookupInfo) 47} 48 49class IPrefetchPipe(implicit p: Parameters) extends IPrefetchModule 50{ 51 val io: IPrefetchIO = IO(new IPrefetchIO) 52 53 val fromFtq = io.ftqReq 54 val (toITLB, fromITLB) = (io.itlb.map(_.req), io.itlb.map(_.resp)) 55 val (toPMP, fromPMP) = (io.pmp.map(_.req), io.pmp.map(_.resp)) 56 val (toMeta, fromMeta) = (io.metaRead.toIMeta, io.metaRead.fromIMeta) 57 val (toMSHR, fromMSHR) = (io.MSHRReq, io.MSHRResp) 58 val toWayLookup = io.wayLookupWrite 59 60 // FIXME: csr_pf_enable/enableBit is not used now 61 val enableBit = RegInit(false.B) 62 enableBit := io.csr_pf_enable 63 64 val s0_fire, s1_fire, s2_fire = WireInit(false.B) 65 val s0_discard, s2_discard = WireInit(false.B) 66 val s0_ready, s1_ready, s2_ready = WireInit(false.B) 67 val s0_flush, s1_flush, s2_flush = WireInit(false.B) 68 val from_bpu_s0_flush, from_bpu_s1_flush = WireInit(false.B) 69 70 /** 71 ****************************************************************************** 72 * IPrefetch Stage 0 73 * - 1. receive ftq req 74 * - 2. send req to ITLB 75 * - 3. send req to Meta SRAM 76 ****************************************************************************** 77 */ 78 val s0_valid = fromFtq.req.valid 79 80 /** 81 ****************************************************************************** 82 * receive ftq req 83 ****************************************************************************** 84 */ 85 val s0_req_vaddr = VecInit(Seq(fromFtq.req.bits.startAddr, fromFtq.req.bits.nextlineStart)) 86 val s0_req_ftqIdx = fromFtq.req.bits.ftqIdx 87 val s0_doubleline = fromFtq.req.bits.crossCacheline 88 val s0_req_vSetIdx = s0_req_vaddr.map(get_idx) 89 90 from_bpu_s0_flush := fromFtq.flushFromBpu.shouldFlushByStage2(s0_req_ftqIdx) || 91 fromFtq.flushFromBpu.shouldFlushByStage3(s0_req_ftqIdx) 92 s0_flush := io.flush || from_bpu_s0_flush || s1_flush 93 94 val s0_can_go = s1_ready && toITLB(0).ready && toITLB(1).ready && toMeta.ready 95 fromFtq.req.ready := s0_can_go 96 97 s0_fire := s0_valid && s0_can_go && !s0_flush 98 99 /** 100 ****************************************************************************** 101 * IPrefetch Stage 1 102 * - 1. Receive resp from ITLB 103 * - 2. Receive resp from IMeta and check 104 * - 3. Monitor the requests from missUnit to write to SRAM. 105 * - 4. Wirte wayLookup 106 ****************************************************************************** 107 */ 108 val s1_valid = generatePipeControl(lastFire = s0_fire, thisFire = s1_fire, thisFlush = s1_flush, lastFlush = false.B) 109 110 val s1_req_vaddr = RegEnable(s0_req_vaddr, 0.U.asTypeOf(s0_req_vaddr), s0_fire) 111 val s1_doubleline = RegEnable(s0_doubleline, 0.U.asTypeOf(s0_doubleline), s0_fire) 112 val s1_req_ftqIdx = RegEnable(s0_req_ftqIdx, 0.U.asTypeOf(s0_req_ftqIdx), s0_fire) 113 val s1_req_vSetIdx = VecInit(s1_req_vaddr.map(get_idx)) 114 115 val m_idle :: m_itlbResend :: m_metaResend :: m_enqWay :: m_enterS2 :: Nil = Enum(5) 116 val state = RegInit(m_idle) 117 val next_state = WireDefault(state) 118 val s0_fire_r = RegNext(s0_fire) 119 dontTouch(state) 120 dontTouch(next_state) 121 state := next_state 122 123 /** 124 ****************************************************************************** 125 * resend itlb req if miss 126 ****************************************************************************** 127 */ 128 val s1_wait_itlb = RegInit(VecInit(Seq.fill(PortNumber)(false.B))) 129 (0 until PortNumber).foreach { i => 130 when(s1_flush) { 131 s1_wait_itlb(i) := false.B 132 }.elsewhen(RegNext(s0_fire) && fromITLB(i).bits.miss) { 133 s1_wait_itlb(i) := true.B 134 }.elsewhen(s1_wait_itlb(i) && !fromITLB(i).bits.miss) { 135 s1_wait_itlb(i) := false.B 136 } 137 } 138 val s1_need_itlb = VecInit(Seq((RegNext(s0_fire) || s1_wait_itlb(0)) && fromITLB(0).bits.miss, 139 (RegNext(s0_fire) || s1_wait_itlb(1)) && fromITLB(1).bits.miss && s1_doubleline)) 140 val tlb_valid_pulse = VecInit(Seq((RegNext(s0_fire) || s1_wait_itlb(0)) && !fromITLB(0).bits.miss, 141 (RegNext(s0_fire) || s1_wait_itlb(1)) && !fromITLB(1).bits.miss && s1_doubleline)) 142 val tlb_valid_latch = VecInit((0 until PortNumber).map(i => ValidHoldBypass(tlb_valid_pulse(i), s1_fire, flush=s1_flush))) 143 val itlb_finish = tlb_valid_latch(0) && (!s1_doubleline || tlb_valid_latch(1)) 144 145 for (i <- 0 until PortNumber) { 146 toITLB(i).valid := s1_need_itlb(i) || (s0_valid && (if(i == 0) true.B else s0_doubleline)) 147 toITLB(i).bits := DontCare 148 toITLB(i).bits.size := 3.U 149 toITLB(i).bits.vaddr := Mux(s1_need_itlb(i), s1_req_vaddr(i), s0_req_vaddr(i)) 150 toITLB(i).bits.debug.pc := Mux(s1_need_itlb(i), s1_req_vaddr(i), s0_req_vaddr(i)) 151 toITLB(i).bits.cmd := TlbCmd.exec 152 toITLB(i).bits.no_translate := false.B 153 } 154 fromITLB.foreach(_.ready := true.B) 155 io.itlb.foreach(_.req_kill := false.B) 156 157 /** 158 ****************************************************************************** 159 * Receive resp from ITLB 160 ****************************************************************************** 161 */ 162 val s1_req_paddr_wire = VecInit(fromITLB.map(_.bits.paddr(0))) 163 val s1_req_paddr_reg = VecInit((0 until PortNumber).map( i => 164 RegEnable(s1_req_paddr_wire(i), 0.U(PAddrBits.W), tlb_valid_pulse(i)) 165 )) 166 val s1_req_paddr = VecInit((0 until PortNumber).map( i => 167 Mux(tlb_valid_pulse(i), s1_req_paddr_wire(i), s1_req_paddr_reg(i)) 168 )) 169 val s1_req_gpaddr_tmp = VecInit((0 until PortNumber).map( i => 170 ResultHoldBypass(valid = tlb_valid_pulse(i), init = 0.U.asTypeOf(fromITLB(i).bits.gpaddr(0)), data = fromITLB(i).bits.gpaddr(0)) 171 )) 172 val s1_itlb_exception = VecInit((0 until PortNumber).map( i => 173 ResultHoldBypass(valid = tlb_valid_pulse(i), init = 0.U(ExceptionType.width.W), data = ExceptionType.fromTlbResp(fromITLB(i).bits)) 174 )) 175 val s1_itlb_exception_gpf = VecInit(s1_itlb_exception.map(_ === ExceptionType.gpf)) 176 177 /* Select gpaddr with the first gpf 178 * Note: the backend wants the base guest physical address of a fetch block 179 * for port(i), its base gpaddr is actually (gpaddr - i * blocksize) 180 * see GPAMem: https://github.com/OpenXiangShan/XiangShan/blob/344cf5d55568dd40cd658a9ee66047a505eeb504/src/main/scala/xiangshan/backend/GPAMem.scala#L33-L34 181 * see also: https://github.com/OpenXiangShan/XiangShan/blob/344cf5d55568dd40cd658a9ee66047a505eeb504/src/main/scala/xiangshan/frontend/IFU.scala#L374-L375 182 */ 183 val s1_req_gpaddr = PriorityMuxDefault( 184 s1_itlb_exception_gpf zip (0 until PortNumber).map(i => s1_req_gpaddr_tmp(i) - (i << blockOffBits).U), 185 0.U.asTypeOf(s1_req_gpaddr_tmp(0)) 186 ) 187 188 /** 189 ****************************************************************************** 190 * resend metaArray read req when itlb miss finish 191 ****************************************************************************** 192 */ 193 val s1_need_meta = ((state === m_itlbResend) && itlb_finish) || (state === m_metaResend) 194 toMeta.valid := s1_need_meta || s0_valid 195 toMeta.bits := DontCare 196 toMeta.bits.isDoubleLine := Mux(s1_need_meta, s1_doubleline, s0_doubleline) 197 198 for (i <- 0 until PortNumber) { 199 toMeta.bits.vSetIdx(i) := Mux(s1_need_meta, s1_req_vSetIdx(i), s0_req_vSetIdx(i)) 200 } 201 202 /** 203 ****************************************************************************** 204 * Receive resp from IMeta and check 205 ****************************************************************************** 206 */ 207 val s1_req_ptags = VecInit(s1_req_paddr.map(get_phy_tag)) 208 209 val s1_meta_ptags = fromMeta.tags 210 val s1_meta_valids = fromMeta.entryValid 211 // If error is found in either way, the tag_eq_vec is unreliable, so we do not use waymask, but directly .orR 212 val s1_meta_corrupt = VecInit(fromMeta.errors.map(_.asUInt.orR)) 213 214 def get_waymask(paddrs: Vec[UInt]): Vec[UInt] = { 215 val ptags = paddrs.map(get_phy_tag) 216 val tag_eq_vec = VecInit((0 until PortNumber).map( p => VecInit((0 until nWays).map( w => s1_meta_ptags(p)(w) === ptags(p))))) 217 val tag_match_vec = VecInit((0 until PortNumber).map( k => VecInit(tag_eq_vec(k).zipWithIndex.map{ case(way_tag_eq, w) => way_tag_eq && s1_meta_valids(k)(w)}))) 218 val waymasks = VecInit(tag_match_vec.map(_.asUInt)) 219 waymasks 220 } 221 222 val s1_SRAM_waymasks = VecInit((0 until PortNumber).map(i => 223 Mux(tlb_valid_pulse(i), get_waymask(s1_req_paddr_wire)(i), get_waymask(s1_req_paddr_reg)(i)))) 224 225 /** 226 ****************************************************************************** 227 * update waymask according to MSHR update data 228 ****************************************************************************** 229 */ 230 def update_waymask(mask: UInt, vSetIdx: UInt, ptag: UInt): UInt = { 231 require(mask.getWidth == nWays) 232 val new_mask = WireInit(mask) 233 val valid = fromMSHR.valid && !fromMSHR.bits.corrupt 234 val vset_same = fromMSHR.bits.vSetIdx === vSetIdx 235 val ptag_same = getPhyTagFromBlk(fromMSHR.bits.blkPaddr) === ptag 236 val way_same = fromMSHR.bits.waymask === mask 237 when(valid && vset_same) { 238 when(ptag_same) { 239 new_mask := fromMSHR.bits.waymask 240 }.elsewhen(way_same) { 241 new_mask := 0.U 242 } 243 } 244 new_mask 245 } 246 247 val s1_SRAM_valid = s0_fire_r || RegNext(s1_need_meta && toMeta.ready) 248 val s1_MSHR_valid = fromMSHR.valid && !fromMSHR.bits.corrupt 249 val s1_waymasks = WireInit(VecInit(Seq.fill(PortNumber)(0.U(nWays.W)))) 250 val s1_waymasks_r = RegEnable(s1_waymasks, 0.U.asTypeOf(s1_waymasks), s1_SRAM_valid || s1_MSHR_valid) 251 (0 until PortNumber).foreach{i => 252 val old_waymask = Mux(s1_SRAM_valid, s1_SRAM_waymasks(i), s1_waymasks_r(i)) 253 s1_waymasks(i) := update_waymask(old_waymask, s1_req_vSetIdx(i), s1_req_ptags(i)) 254 } 255 256 /** 257 ****************************************************************************** 258 * send enqueu req to WayLookup 259 ******** ********************************************************************** 260 */ 261 // Disallow enqueuing wayLookup when SRAM write occurs. 262 toWayLookup.valid := ((state === m_enqWay) || ((state === m_idle) && itlb_finish)) && !s1_flush && !fromMSHR.valid 263 toWayLookup.bits.vSetIdx := s1_req_vSetIdx 264 toWayLookup.bits.waymask := s1_waymasks 265 toWayLookup.bits.ptag := s1_req_ptags 266 toWayLookup.bits.gpaddr := s1_req_gpaddr 267 (0 until PortNumber).foreach { i => 268 val excpValid = (if (i == 0) true.B else s1_doubleline) // exception in first line is always valid, in second line is valid iff is doubleline request 269 // Send s1_itlb_exception to WayLookup (instead of s1_exception_out) for better timing. Will check pmp again in mainPipe 270 toWayLookup.bits.itlb_exception(i) := Mux(excpValid, s1_itlb_exception(i), ExceptionType.none) 271 toWayLookup.bits.meta_corrupt(i) := excpValid && s1_meta_corrupt(i) 272 } 273 274 val s1_waymasks_vec = s1_waymasks.map(_.asTypeOf(Vec(nWays, Bool()))) 275 when(toWayLookup.fire) { 276 assert(PopCount(s1_waymasks_vec(0)) <= 1.U && (PopCount(s1_waymasks_vec(1)) <= 1.U || !s1_doubleline), 277 "Multiple hit in main pipe, port0:is=%d,ptag=0x%x,vidx=0x%x,vaddr=0x%x port1:is=%d,ptag=0x%x,vidx=0x%x,vaddr=0x%x ", 278 PopCount(s1_waymasks_vec(0)) > 1.U, s1_req_ptags(0), get_idx(s1_req_vaddr(0)), s1_req_vaddr(0), 279 PopCount(s1_waymasks_vec(1)) > 1.U && s1_doubleline, s1_req_ptags(1), get_idx(s1_req_vaddr(1)), s1_req_vaddr(1)) 280 } 281 282 /** 283 ****************************************************************************** 284 * PMP check 285 ****************************************************************************** 286 */ 287 toPMP.zipWithIndex.foreach { case (p, i) => 288 // if itlb has exception, paddr can be invalid, therefore pmp check can be skipped 289 p.valid := s1_valid // && s1_itlb_exception === ExceptionType.none 290 p.bits.addr := s1_req_paddr(i) 291 p.bits.size := 3.U // TODO 292 p.bits.cmd := TlbCmd.exec 293 } 294 val s1_pmp_exception = VecInit(fromPMP.map(ExceptionType.fromPMPResp)) 295 val s1_mmio = VecInit(fromPMP.map(_.mmio)) 296 297 // merge s1 itlb/pmp exceptions, itlb has higher priority 298 val s1_exception_out = ExceptionType.merge(s1_itlb_exception, s1_pmp_exception) 299 300 /** 301 ****************************************************************************** 302 * state machine 303 ******** ********************************************************************** 304 */ 305 306 switch(state) { 307 is(m_idle) { 308 when(s1_valid && !itlb_finish) { 309 next_state := m_itlbResend 310 }.elsewhen(s1_valid && itlb_finish && !toWayLookup.fire) { 311 next_state := m_enqWay 312 }.elsewhen(s1_valid && itlb_finish && toWayLookup.fire && !s2_ready) { 313 next_state := m_enterS2 314 } 315 } 316 is(m_itlbResend) { 317 when(itlb_finish && !toMeta.ready) { 318 next_state := m_metaResend 319 }.elsewhen(itlb_finish && toMeta.ready) { 320 next_state := m_enqWay 321 } 322 } 323 is(m_metaResend) { 324 when(toMeta.ready) { 325 next_state := m_enqWay 326 } 327 } 328 is(m_enqWay) { 329 when(toWayLookup.fire && !s2_ready) { 330 next_state := m_enterS2 331 }.elsewhen(toWayLookup.fire && s2_ready) { 332 next_state := m_idle 333 } 334 } 335 is(m_enterS2) { 336 when(s2_ready) { 337 next_state := m_idle 338 } 339 } 340 } 341 342 when(s1_flush) { 343 next_state := m_idle 344 } 345 346 /** Stage 1 control */ 347 from_bpu_s1_flush := s1_valid && fromFtq.flushFromBpu.shouldFlushByStage3(s1_req_ftqIdx) 348 s1_flush := io.flush || from_bpu_s1_flush 349 350 s1_ready := next_state === m_idle 351 s1_fire := (next_state === m_idle) && s1_valid && !s1_flush 352 353 /** 354 ****************************************************************************** 355 * IPrefetch Stage 2 356 * - 1. Monitor the requests from missUnit to write to SRAM. 357 * - 2. send req to missUnit 358 ****************************************************************************** 359 */ 360 val s2_valid = generatePipeControl(lastFire = s1_fire, thisFire = s2_fire, thisFlush = s2_flush, lastFlush = false.B) 361 362 val s2_req_vaddr = RegEnable(s1_req_vaddr, 0.U.asTypeOf(s1_req_vaddr), s1_fire) 363 val s2_doubleline = RegEnable(s1_doubleline, 0.U.asTypeOf(s1_doubleline), s1_fire) 364 val s2_req_paddr = RegEnable(s1_req_paddr, 0.U.asTypeOf(s1_req_paddr), s1_fire) 365 val s2_exception = RegEnable(s1_exception_out, 0.U.asTypeOf(s1_exception_out), s1_fire) // includes itlb/pmp exceptions 366 val s2_mmio = RegEnable(s1_mmio, 0.U.asTypeOf(s1_mmio), s1_fire) 367 val s2_waymasks = RegEnable(s1_waymasks, 0.U.asTypeOf(s1_waymasks), s1_fire) 368 369 val s2_req_vSetIdx = s2_req_vaddr.map(get_idx) 370 val s2_req_ptags = s2_req_paddr.map(get_phy_tag) 371 372 /** 373 ****************************************************************************** 374 * Monitor the requests from missUnit to write to SRAM 375 ****************************************************************************** 376 */ 377 378 /* NOTE: If fromMSHR.bits.corrupt, we should set s2_MSHR_hits to false.B, and send prefetch requests again. 379 * This is the opposite of how mainPipe handles fromMSHR.bits.corrupt, 380 * in which we should set s2_MSHR_hits to true.B, and send error to ifu. 381 */ 382 val s2_MSHR_match = VecInit((0 until PortNumber).map(i => 383 (s2_req_vSetIdx(i) === fromMSHR.bits.vSetIdx) && 384 (s2_req_ptags(i) === getPhyTagFromBlk(fromMSHR.bits.blkPaddr)) && 385 s2_valid && fromMSHR.valid && !fromMSHR.bits.corrupt 386 )) 387 val s2_MSHR_hits = (0 until PortNumber).map(i => ValidHoldBypass(s2_MSHR_match(i), s2_fire || s2_flush)) 388 389 val s2_SRAM_hits = s2_waymasks.map(_.orR) 390 val s2_hits = VecInit((0 until PortNumber).map(i => s2_MSHR_hits(i) || s2_SRAM_hits(i))) 391 392 /* s2_exception includes itlb pf/gpf/af and pmp af, neither of which should be prefetched 393 * mmio should not be prefetched 394 * also, if port0 has exception, port1 should not be prefetched 395 * miss = this port not hit && need this port && no exception found before and in this port 396 */ 397 // FIXME: maybe we should cancel fetch when meta error is detected, since hits (waymasks) can be invalid 398 val s2_miss = VecInit((0 until PortNumber).map { i => 399 !s2_hits(i) && (if (i==0) true.B else s2_doubleline) && 400 s2_exception.take(i+1).map(_ === ExceptionType.none).reduce(_&&_) && 401 s2_mmio.take(i+1).map(!_).reduce(_&&_) 402 }) 403 404 /** 405 ****************************************************************************** 406 * send req to missUnit 407 ****************************************************************************** 408 */ 409 val toMSHRArbiter = Module(new Arbiter(new ICacheMissReq, PortNumber)) 410 411 // To avoid sending duplicate requests. 412 val has_send = RegInit(VecInit(Seq.fill(PortNumber)(false.B))) 413 (0 until PortNumber).foreach{ i => 414 when(s1_fire) { 415 has_send(i) := false.B 416 }.elsewhen(toMSHRArbiter.io.in(i).fire) { 417 has_send(i) := true.B 418 } 419 } 420 421 (0 until PortNumber).map{ i => 422 toMSHRArbiter.io.in(i).valid := s2_valid && s2_miss(i) && !has_send(i) 423 toMSHRArbiter.io.in(i).bits.blkPaddr := getBlkAddr(s2_req_paddr(i)) 424 toMSHRArbiter.io.in(i).bits.vSetIdx := s2_req_vSetIdx(i) 425 } 426 427 toMSHR <> toMSHRArbiter.io.out 428 429 s2_flush := io.flush 430 431 val s2_finish = (0 until PortNumber).map(i => has_send(i) || !s2_miss(i) || toMSHRArbiter.io.in(i).fire).reduce(_&&_) 432 s2_ready := s2_finish || !s2_valid 433 s2_fire := s2_valid && s2_finish && !s2_flush 434 435 /** PerfAccumulate */ 436 // the number of prefetch request received from ftq 437 XSPerfAccumulate("prefetch_req_receive", fromFtq.req.fire) 438 // the number of prefetch request sent to missUnit 439 XSPerfAccumulate("prefetch_req_send", toMSHR.fire) 440 XSPerfAccumulate("to_missUnit_stall", toMSHR.valid && !toMSHR.ready) 441 /** 442 * Count the number of requests that are filtered for various reasons. 443 * The number of prefetch discard in Performance Accumulator may be 444 * a littel larger the number of really discarded. Because there can 445 * be multiple reasons for a canceled request at the same time. 446 */ 447 // discard prefetch request by flush 448 // XSPerfAccumulate("fdip_prefetch_discard_by_tlb_except", p1_discard && p1_tlb_except) 449 // // discard prefetch request by hit icache SRAM 450 // XSPerfAccumulate("fdip_prefetch_discard_by_hit_cache", p2_discard && p1_meta_hit) 451 // // discard prefetch request by hit wirte SRAM 452 // XSPerfAccumulate("fdip_prefetch_discard_by_p1_monoitor", p1_discard && p1_monitor_hit) 453 // // discard prefetch request by pmp except or mmio 454 // XSPerfAccumulate("fdip_prefetch_discard_by_pmp", p2_discard && p2_pmp_except) 455 // // discard prefetch request by hit mainPipe info 456 // // XSPerfAccumulate("fdip_prefetch_discard_by_mainPipe", p2_discard && p2_mainPipe_hit) 457}