1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend.icache 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.tilelink.ClientStates 23import xiangshan._ 24import xiangshan.cache.mmu._ 25import utils._ 26import xiangshan.backend.fu.{PMPReqBundle, PMPRespBundle} 27import xiangshan.frontend.{FtqICacheInfo, FtqToICacheRequestBundle} 28 29class ICacheMainPipeReq(implicit p: Parameters) extends ICacheBundle 30{ 31 val vaddr = UInt(VAddrBits.W) 32 def vsetIdx = get_idx(vaddr) 33} 34 35class ICacheMainPipeResp(implicit p: Parameters) extends ICacheBundle 36{ 37 val vaddr = UInt(VAddrBits.W) 38 val registerData = UInt(blockBits.W) 39 val sramData = UInt(blockBits.W) 40 val select = Bool() 41 val paddr = UInt(PAddrBits.W) 42 val tlbExcp = new Bundle{ 43 val pageFault = Bool() 44 val accessFault = Bool() 45 val mmio = Bool() 46 } 47} 48 49class ICacheMainPipeBundle(implicit p: Parameters) extends ICacheBundle 50{ 51 val req = Flipped(Decoupled(new FtqToICacheRequestBundle)) 52 val resp = Vec(PortNumber, ValidIO(new ICacheMainPipeResp)) 53} 54 55class ICacheMetaReqBundle(implicit p: Parameters) extends ICacheBundle{ 56 val toIMeta = DecoupledIO(new ICacheReadBundle) 57 val fromIMeta = Input(new ICacheMetaRespBundle) 58} 59 60class ICacheDataReqBundle(implicit p: Parameters) extends ICacheBundle{ 61 val toIData = DecoupledIO(Vec(partWayNum, new ICacheReadBundle)) 62 val fromIData = Input(new ICacheDataRespBundle) 63} 64 65class ICacheMSHRBundle(implicit p: Parameters) extends ICacheBundle{ 66 val toMSHR = Decoupled(new ICacheMissReq) 67 val fromMSHR = Flipped(ValidIO(new ICacheMissResp)) 68} 69 70class ICachePMPBundle(implicit p: Parameters) extends ICacheBundle{ 71 val req = Valid(new PMPReqBundle()) 72 val resp = Input(new PMPRespBundle()) 73} 74 75class ICachePerfInfo(implicit p: Parameters) extends ICacheBundle{ 76 val only_0_hit = Bool() 77 val only_0_miss = Bool() 78 val hit_0_hit_1 = Bool() 79 val hit_0_miss_1 = Bool() 80 val miss_0_hit_1 = Bool() 81 val miss_0_miss_1 = Bool() 82 val hit_0_except_1 = Bool() 83 val miss_0_except_1 = Bool() 84 val except_0 = Bool() 85 val bank_hit = Vec(2,Bool()) 86 val hit = Bool() 87} 88 89class ICacheMainPipeInterface(implicit p: Parameters) extends ICacheBundle { 90 /*** internal interface ***/ 91 val metaArray = new ICacheMetaReqBundle 92 val dataArray = new ICacheDataReqBundle 93 val mshr = Vec(PortNumber, new ICacheMSHRBundle) 94 val errors = Output(Vec(PortNumber, new L1CacheErrorInfo)) 95 /*** outside interface ***/ 96 //val fetch = Vec(PortNumber, new ICacheMainPipeBundle) 97 /* when ftq.valid is high in T + 1 cycle 98 * the ftq component must be valid in T cycle 99 */ 100 val fetch = new ICacheMainPipeBundle 101 val pmp = Vec(PortNumber, new ICachePMPBundle) 102 val itlb = Vec(PortNumber, new TlbRequestIO) 103 val respStall = Input(Bool()) 104 val perfInfo = Output(new ICachePerfInfo) 105 106 val prefetchEnable = Output(Bool()) 107 val prefetchDisable = Output(Bool()) 108 val csr_parity_enable = Input(Bool()) 109 110} 111 112class ICacheMainPipe(implicit p: Parameters) extends ICacheModule 113{ 114 val io = IO(new ICacheMainPipeInterface) 115 116 /** Input/Output port */ 117 val (fromFtq, toIFU) = (io.fetch.req, io.fetch.resp) 118 val (toMeta, metaResp) = (io.metaArray.toIMeta, io.metaArray.fromIMeta) 119 val (toData, dataResp) = (io.dataArray.toIData, io.dataArray.fromIData) 120 val (toMSHR, fromMSHR) = (io.mshr.map(_.toMSHR), io.mshr.map(_.fromMSHR)) 121 val (toITLB, fromITLB) = (io.itlb.map(_.req), io.itlb.map(_.resp)) 122 val (toPMP, fromPMP) = (io.pmp.map(_.req), io.pmp.map(_.resp)) 123 io.itlb.foreach(_.req_kill := false.B) 124 125 //Ftq RegNext Register 126 val fromFtqReq = fromFtq.bits.pcMemRead 127 128 /** pipeline control signal */ 129 val s1_ready, s2_ready = Wire(Bool()) 130 val s0_fire, s1_fire , s2_fire = Wire(Bool()) 131 132 val missSwitchBit = RegInit(false.B) 133 134 /** replacement status register */ 135 val touch_sets = Seq.fill(2)(Wire(Vec(2, UInt(log2Ceil(nSets/2).W)))) 136 val touch_ways = Seq.fill(2)(Wire(Vec(2, Valid(UInt(log2Ceil(nWays).W)))) ) 137 138 /** 139 ****************************************************************************** 140 * ICache Stage 0 141 * - send req to ITLB and wait for tlb miss fixing 142 * - send req to Meta/Data SRAM 143 ****************************************************************************** 144 */ 145 146 /** s0 control */ 147 val s0_valid = fromFtq.valid 148 val s0_req_vaddr = (0 until partWayNum + 1).map(i => VecInit(Seq(fromFtqReq(i).startAddr, fromFtqReq(i).nextlineStart))) 149 val s0_req_vsetIdx = (0 until partWayNum + 1).map(i => VecInit(s0_req_vaddr(i).map(get_idx(_)))) 150 val s0_only_first = (0 until partWayNum + 1).map(i => fromFtq.bits.readValid(i) && !fromFtqReq(i).crossCacheline) 151 val s0_double_line = (0 until partWayNum + 1).map(i => fromFtq.bits.readValid(i) && fromFtqReq(i).crossCacheline) 152 153 val s0_final_valid = s0_valid 154 val s0_final_vaddr = s0_req_vaddr.head 155 val s0_final_vsetIdx = s0_req_vsetIdx.head 156 val s0_final_only_first = s0_only_first.head 157 val s0_final_double_line = s0_double_line.head 158 159 /** SRAM request */ 160 //0 -> metaread, 1,2,3 -> data, 3 -> code 4 -> itlb 161 val ftq_req_to_data_doubleline = s0_double_line.init 162 val ftq_req_to_data_vset_idx = s0_req_vsetIdx.init 163 val ftq_req_to_data_valid = fromFtq.bits.readValid.init 164 165 val ftq_req_to_meta_doubleline = s0_double_line.head 166 val ftq_req_to_meta_vset_idx = s0_req_vsetIdx.head 167 168 val ftq_req_to_itlb_only_first = s0_only_first.last 169 val ftq_req_to_itlb_doubleline = s0_double_line.last 170 val ftq_req_to_itlb_vaddr = s0_req_vaddr.last 171 val ftq_req_to_itlb_vset_idx = s0_req_vsetIdx.last 172 173 174 for(i <- 0 until partWayNum) { 175 toData.valid := ftq_req_to_data_valid(i) && !missSwitchBit 176 toData.bits(i).isDoubleLine := ftq_req_to_data_doubleline(i) 177 toData.bits(i).vSetIdx := ftq_req_to_data_vset_idx(i) 178 } 179 180 toMeta.valid := s0_valid && !missSwitchBit 181 toMeta.bits.isDoubleLine := ftq_req_to_meta_doubleline 182 toMeta.bits.vSetIdx := ftq_req_to_meta_vset_idx 183 184 185 toITLB(0).valid := s0_valid 186 toITLB(0).bits.size := 3.U // TODO: fix the size 187 toITLB(0).bits.vaddr := ftq_req_to_itlb_vaddr(0) 188 toITLB(0).bits.debug.pc := ftq_req_to_itlb_vaddr(0) 189 190 toITLB(1).valid := s0_valid && ftq_req_to_itlb_doubleline 191 toITLB(1).bits.size := 3.U // TODO: fix the size 192 toITLB(1).bits.vaddr := ftq_req_to_itlb_vaddr(1) 193 toITLB(1).bits.debug.pc := ftq_req_to_itlb_vaddr(1) 194 195 toITLB.map{port => 196 port.bits.cmd := TlbCmd.exec 197 port.bits.debug.robIdx := DontCare 198 port.bits.debug.isFirstIssue := DontCare 199 } 200 201 /** ITLB & ICACHE sync case 202 * when icache is not ready, but itlb is ready 203 * because itlb is non-block, then the req will take the port 204 * then itlb will unset the ready?? itlb is wrongly blocked. 205 * Solution: maybe give itlb a signal to tell whether acquire the slot? 206 */ 207 208 val itlb_can_go = toITLB(0).ready && toITLB(1).ready 209 val icache_can_go = toData.ready && toMeta.ready 210 val pipe_can_go = !missSwitchBit && s1_ready 211 val s0_can_go = itlb_can_go && icache_can_go && pipe_can_go 212 val s0_fetch_fire = s0_valid && s0_can_go 213 s0_fire := s0_fetch_fire 214 toITLB.map{port => port.bits.kill := !icache_can_go || !pipe_can_go} 215 216 //TODO: fix GTimer() condition 217 fromFtq.ready := s0_can_go 218 219 /** 220 ****************************************************************************** 221 * ICache Stage 1 222 * - get tlb resp data (exceptiong info and physical addresses) 223 * - get Meta/Data SRAM read responses (latched for pipeline stop) 224 * - tag compare/hit check 225 ****************************************************************************** 226 */ 227 228 /** s1 control */ 229 230 val s1_valid = generatePipeControl(lastFire = s0_fire, thisFire = s1_fire, thisFlush = false.B, lastFlush = false.B) 231 232 val s1_req_vaddr = RegEnable(s0_final_vaddr, s0_fire) 233 val s1_req_vsetIdx = RegEnable(s0_final_vsetIdx, s0_fire) 234 val s1_only_first = RegEnable(s0_final_only_first, s0_fire) 235 val s1_double_line = RegEnable(s0_final_double_line, s0_fire) 236 237 /** tlb response latch for pipeline stop */ 238 val tlb_back = fromITLB.map(_.fire()) 239 val tlb_need_back = VecInit((0 until PortNumber).map(i => ValidHold(s0_fire && toITLB(i).fire(), s1_fire, false.B))) 240 val tlb_already_recv = RegInit(VecInit(Seq.fill(PortNumber)(false.B))) 241 val tlb_ready_recv = VecInit((0 until PortNumber).map(i => RegNext(s0_fire, false.B) || (s1_valid && !tlb_already_recv(i)))) 242 val tlb_resp_valid = Wire(Vec(2, Bool())) 243 for (i <- 0 until PortNumber) { 244 tlb_resp_valid(i) := tlb_already_recv(i) || (tlb_ready_recv(i) && tlb_back(i)) 245 when (tlb_already_recv(i) && s1_fire) { 246 tlb_already_recv(i) := false.B 247 } 248 when (tlb_back(i) && tlb_ready_recv(i) && !s1_fire) { 249 tlb_already_recv(i) := true.B 250 } 251 fromITLB(i).ready := tlb_ready_recv(i) 252 } 253 assert(RegNext(Cat((0 until PortNumber).map(i => tlb_need_back(i) || !tlb_resp_valid(i))).andR(), true.B), 254 "when tlb should not back, tlb should not resp valid") 255 assert(RegNext(!s1_valid || Cat(tlb_need_back).orR, true.B), "when s1_valid, need at least one tlb_need_back") 256 assert(RegNext(s1_valid || !Cat(tlb_need_back).orR, true.B), "when !s1_valid, all the tlb_need_back should be false") 257 assert(RegNext(s1_valid || !Cat(tlb_already_recv).orR, true.B), "when !s1_valid, should not tlb_already_recv") 258 assert(RegNext(s1_valid || !Cat(tlb_resp_valid).orR, true.B), "when !s1_valid, should not tlb_resp_valid") 259 260 val tlbRespPAddr = VecInit((0 until PortNumber).map(i => ResultHoldBypass(valid = tlb_back(i), data = fromITLB(i).bits.paddr(0)))) 261 val tlbExcpPF = VecInit((0 until PortNumber).map(i => ResultHoldBypass(valid = tlb_back(i), data = fromITLB(i).bits.excp(0).pf.instr) && tlb_need_back(i))) 262 val tlbExcpAF = VecInit((0 until PortNumber).map(i => ResultHoldBypass(valid = tlb_back(i), data = fromITLB(i).bits.excp(0).af.instr) && tlb_need_back(i))) 263 val tlbExcp = VecInit((0 until PortNumber).map(i => tlbExcpPF(i) || tlbExcpPF(i))) 264 265 val tlbRespAllValid = Cat((0 until PortNumber).map(i => !tlb_need_back(i) || tlb_resp_valid(i))).andR 266 s1_ready := s2_ready && tlbRespAllValid || !s1_valid 267 s1_fire := s1_valid && tlbRespAllValid && s2_ready 268 269 /** s1 hit check/tag compare */ 270 val s1_req_paddr = tlbRespPAddr 271 val s1_req_ptags = VecInit(s1_req_paddr.map(get_phy_tag(_))) 272 273 val s1_meta_ptags = ResultHoldBypass(data = metaResp.tags, valid = RegNext(s0_fire)) 274 val s1_meta_cohs = ResultHoldBypass(data = metaResp.cohs, valid = RegNext(s0_fire)) 275 val s1_meta_errors = ResultHoldBypass(data = metaResp.errors, valid = RegNext(s0_fire)) 276 277 val s1_data_cacheline = ResultHoldBypass(data = dataResp.datas, valid = RegNext(s0_fire)) 278 val s1_data_errorBits = ResultHoldBypass(data = dataResp.codes, valid = RegNext(s0_fire)) 279 280 val s1_tag_eq_vec = VecInit((0 until PortNumber).map( p => VecInit((0 until nWays).map( w => s1_meta_ptags(p)(w) === s1_req_ptags(p) )))) 281 val s1_tag_match_vec = VecInit((0 until PortNumber).map( k => VecInit(s1_tag_eq_vec(k).zipWithIndex.map{ case(way_tag_eq, w) => way_tag_eq && s1_meta_cohs(k)(w).isValid()}))) 282 val s1_tag_match = VecInit(s1_tag_match_vec.map(vector => ParallelOR(vector))) 283 284 val s1_port_hit = VecInit(Seq(s1_tag_match(0) && s1_valid && !tlbExcp(0), s1_tag_match(1) && s1_valid && s1_double_line && !tlbExcp(1) )) 285 val s1_bank_miss = VecInit(Seq(!s1_tag_match(0) && s1_valid && !tlbExcp(0), !s1_tag_match(1) && s1_valid && s1_double_line && !tlbExcp(1) )) 286 val s1_hit = (s1_port_hit(0) && s1_port_hit(1)) || (!s1_double_line && s1_port_hit(0)) 287 288 /** choose victim cacheline */ 289 val replacers = Seq.fill(PortNumber)(ReplacementPolicy.fromString(cacheParams.replacer,nWays,nSets/PortNumber)) 290 val s1_victim_oh = ResultHoldBypass(data = VecInit(replacers.zipWithIndex.map{case (replacer, i) => UIntToOH(replacer.way(s1_req_vsetIdx(i)))}), valid = RegNext(s0_fire)) 291 292 val s1_victim_coh = VecInit(s1_victim_oh.zipWithIndex.map {case(oh, port) => Mux1H(oh, s1_meta_cohs(port))}) 293 294 when(s1_valid){ 295 assert(PopCount(s1_tag_match_vec(0)) <= 1.U && PopCount(s1_tag_match_vec(1)) <= 1.U, "Multiple hit in main pipe") 296 } 297 298 ((replacers zip touch_sets) zip touch_ways).map{case ((r, s),w) => r.access(s,w)} 299 300 301 /** <PERF> replace victim way number */ 302 303 (0 until nWays).map{ w => 304 XSPerfAccumulate("line_0_hit_way_" + Integer.toString(w, 10), s1_fire && s1_port_hit(0) && OHToUInt(s1_tag_match_vec(0)) === w.U) 305 } 306 307 (0 until nWays).map{ w => 308 XSPerfAccumulate("line_0_victim_way_" + Integer.toString(w, 10), s1_fire && !s1_port_hit(0) && OHToUInt(s1_victim_oh(0)) === w.U) 309 } 310 311 (0 until nWays).map{ w => 312 XSPerfAccumulate("line_1_hit_way_" + Integer.toString(w, 10), s1_fire && s1_double_line && s1_port_hit(1) && OHToUInt(s1_tag_match_vec(1)) === w.U) 313 } 314 315 (0 until nWays).map{ w => 316 XSPerfAccumulate("line_1_victim_way_" + Integer.toString(w, 10), s1_fire && s1_double_line && !s1_port_hit(1) && OHToUInt(s1_victim_oh(1)) === w.U) 317 } 318 319 /** 320 ****************************************************************************** 321 * ICache Stage 2 322 * - send request to MSHR if ICache miss 323 * - generate secondary miss status/data registers 324 * - response to IFU 325 ****************************************************************************** 326 */ 327 328 /** s2 control */ 329 val s2_fetch_finish = Wire(Bool()) 330 331 val s2_valid = generatePipeControl(lastFire = s1_fire, thisFire = s2_fire, thisFlush = false.B, lastFlush = false.B) 332 val s2_miss_available = Wire(Bool()) 333 334 s2_ready := (s2_valid && s2_fetch_finish && !io.respStall) || (!s2_valid && s2_miss_available) 335 s2_fire := s2_valid && s2_fetch_finish && !io.respStall 336 337 /** s2 data */ 338 val mmio = fromPMP.map(port => port.mmio) // TODO: handle it 339 340 val (s2_req_paddr , s2_req_vaddr) = (RegEnable(s1_req_paddr, s1_fire), RegEnable(s1_req_vaddr, s1_fire)) 341 val s2_req_vsetIdx = RegEnable(s1_req_vsetIdx, s1_fire) 342 val s2_req_ptags = RegEnable(s1_req_ptags, s1_fire) 343 val s2_only_first = RegEnable(s1_only_first, s1_fire) 344 val s2_double_line = RegEnable(s1_double_line, s1_fire) 345 val s2_hit = RegEnable(s1_hit , s1_fire) 346 val s2_port_hit = RegEnable(s1_port_hit, s1_fire) 347 val s2_bank_miss = RegEnable(s1_bank_miss, s1_fire) 348 val s2_waymask = RegEnable(s1_victim_oh, s1_fire) 349 val s2_victim_coh = RegEnable(s1_victim_coh, s1_fire) 350 val s2_tag_match_vec = RegEnable(s1_tag_match_vec, s1_fire) 351 352 assert(RegNext(!s2_valid || s2_req_paddr(0)(11,0) === s2_req_vaddr(0)(11,0), true.B)) 353 354 /** status imply that s2 is a secondary miss (no need to resend miss request) */ 355 val sec_meet_vec = Wire(Vec(2, Bool())) 356 val s2_fixed_hit_vec = VecInit((0 until 2).map(i => s2_port_hit(i) || sec_meet_vec(i))) 357 val s2_fixed_hit = (s2_valid && s2_fixed_hit_vec(0) && s2_fixed_hit_vec(1) && s2_double_line) || (s2_valid && s2_fixed_hit_vec(0) && !s2_double_line) 358 359 val s2_meta_errors = RegEnable(s1_meta_errors, s1_fire) 360 val s2_data_errorBits = RegEnable(s1_data_errorBits, s1_fire) 361 val s2_data_cacheline = RegEnable(s1_data_cacheline, s1_fire) 362 363 val s2_data_errors = Wire(Vec(PortNumber,Vec(nWays, Bool()))) 364 365 (0 until PortNumber).map{ i => 366 val read_datas = s2_data_cacheline(i).asTypeOf(Vec(nWays,Vec(dataCodeUnitNum, UInt(dataCodeUnit.W)))) 367 val read_codes = s2_data_errorBits(i).asTypeOf(Vec(nWays,Vec(dataCodeUnitNum, UInt(dataCodeBits.W)))) 368 val data_full_wayBits = VecInit((0 until nWays).map( w => 369 VecInit((0 until dataCodeUnitNum).map(u => 370 Cat(read_codes(w)(u), read_datas(w)(u)))))) 371 val data_error_wayBits = VecInit((0 until nWays).map( w => 372 VecInit((0 until dataCodeUnitNum).map(u => 373 cacheParams.dataCode.decode(data_full_wayBits(w)(u)).error )))) 374 if(i == 0){ 375 (0 until nWays).map{ w => 376 s2_data_errors(i)(w) := RegNext(RegNext(s1_fire)) && RegNext(data_error_wayBits(w)).reduce(_||_) 377 } 378 } else { 379 (0 until nWays).map{ w => 380 s2_data_errors(i)(w) := RegNext(RegNext(s1_fire)) && RegNext(RegNext(s1_double_line)) && RegNext(data_error_wayBits(w)).reduce(_||_) 381 } 382 } 383 } 384 385 val s2_parity_meta_error = VecInit((0 until PortNumber).map(i => s2_meta_errors(i).reduce(_||_) && io.csr_parity_enable)) 386 val s2_parity_data_error = VecInit((0 until PortNumber).map(i => s2_data_errors(i).reduce(_||_) && io.csr_parity_enable)) 387 val s2_parity_error = VecInit((0 until PortNumber).map(i => RegNext(s2_parity_meta_error(i)) || s2_parity_data_error(i))) 388 389 for(i <- 0 until PortNumber){ 390 io.errors(i).valid := RegNext(s2_parity_error(i) && RegNext(RegNext(s1_fire))) 391 io.errors(i).report_to_beu := RegNext(s2_parity_error(i) && RegNext(RegNext(s1_fire))) 392 io.errors(i).paddr := RegNext(RegNext(s2_req_paddr(i))) 393 io.errors(i).source := DontCare 394 io.errors(i).source.tag := RegNext(RegNext(s2_parity_meta_error(i))) 395 io.errors(i).source.data := RegNext(s2_parity_data_error(i)) 396 io.errors(i).source.l2 := false.B 397 io.errors(i).opType := DontCare 398 io.errors(i).opType.fetch := true.B 399 } 400 XSError(s2_parity_error.reduce(_||_) && RegNext(RegNext(s1_fire)), "ICache has parity error in MainPaipe!") 401 402 403 /** exception and pmp logic **/ 404 //PMP Result 405 val s2_tlb_need_back = VecInit((0 until PortNumber).map(i => ValidHold(tlb_need_back(i) && s1_fire, s2_fire, false.B))) 406 val pmpExcpAF = Wire(Vec(PortNumber, Bool())) 407 pmpExcpAF(0) := fromPMP(0).instr && s2_tlb_need_back(0) 408 pmpExcpAF(1) := fromPMP(1).instr && s2_double_line && s2_tlb_need_back(1) 409 //exception information 410 //short delay exception signal 411 val s2_except_pf = RegEnable(tlbExcpPF, s1_fire) 412 val s2_except_tlb_af = RegEnable(tlbExcpAF, s1_fire) 413 //long delay exception signal 414 val s2_except_pmp_af = DataHoldBypass(pmpExcpAF, RegNext(s1_fire)) 415 // val s2_except_parity_af = VecInit(s2_parity_error(i) && RegNext(RegNext(s1_fire)) ) 416 417 val s2_except = VecInit((0 until 2).map{i => s2_except_pf(i) || s2_except_tlb_af(i)}) 418 val s2_has_except = s2_valid && (s2_except_tlb_af.reduce(_||_) || s2_except_pf.reduce(_||_)) 419 //MMIO 420 val s2_mmio = DataHoldBypass(io.pmp(0).resp.mmio && !s2_except_tlb_af(0) && !s2_except_pmp_af(0) && !s2_except_pf(0), RegNext(s1_fire)).asBool() && s2_valid 421 422 //send physical address to PMP 423 io.pmp.zipWithIndex.map { case (p, i) => 424 p.req.valid := s2_valid && !missSwitchBit 425 p.req.bits.addr := s2_req_paddr(i) 426 p.req.bits.size := 3.U // TODO 427 p.req.bits.cmd := TlbCmd.exec 428 } 429 430 /*** cacheline miss logic ***/ 431 val wait_idle :: wait_queue_ready :: wait_send_req :: wait_two_resp :: wait_0_resp :: wait_1_resp :: wait_one_resp ::wait_finish :: wait_pmp_except :: Nil = Enum(9) 432 val wait_state = RegInit(wait_idle) 433 434 val port_miss_fix = VecInit(Seq(fromMSHR(0).fire() && !s2_port_hit(0), fromMSHR(1).fire() && s2_double_line && !s2_port_hit(1) )) 435 436 // secondary miss record registers 437 class MissSlot(implicit p: Parameters) extends ICacheBundle { 438 val m_vSetIdx = UInt(idxBits.W) 439 val m_pTag = UInt(tagBits.W) 440 val m_data = UInt(blockBits.W) 441 val m_corrupt = Bool() 442 } 443 444 val missSlot = Seq.fill(2)(RegInit(0.U.asTypeOf(new MissSlot))) 445 val m_invalid :: m_valid :: m_refilled :: m_flushed :: m_wait_sec_miss :: m_check_final ::Nil = Enum(6) 446 val missStateQueue = RegInit(VecInit(Seq.fill(2)(m_invalid)) ) 447 val reservedRefillData = Wire(Vec(2, UInt(blockBits.W))) 448 449 s2_miss_available := VecInit(missStateQueue.map(entry => entry === m_invalid || entry === m_wait_sec_miss)).reduce(_&&_) 450 451 val fix_sec_miss = Wire(Vec(4, Bool())) 452 val sec_meet_0_miss = fix_sec_miss(0) || fix_sec_miss(2) 453 val sec_meet_1_miss = fix_sec_miss(1) || fix_sec_miss(3) 454 sec_meet_vec := VecInit(Seq(sec_meet_0_miss,sec_meet_1_miss )) 455 456 /*** miss/hit pattern: <Control Signal> only raise at the first cycle of s2_valid ***/ 457 val cacheline_0_hit = (s2_port_hit(0) || sec_meet_0_miss) 458 val cacheline_0_miss = !s2_port_hit(0) && !sec_meet_0_miss 459 460 val cacheline_1_hit = (s2_port_hit(1) || sec_meet_1_miss) 461 val cacheline_1_miss = !s2_port_hit(1) && !sec_meet_1_miss 462 463 val only_0_miss = RegNext(s1_fire) && cacheline_0_miss && !s2_double_line && !s2_has_except && !s2_mmio 464 val only_0_hit = RegNext(s1_fire) && cacheline_0_hit && !s2_double_line && !s2_mmio 465 val hit_0_hit_1 = RegNext(s1_fire) && cacheline_0_hit && cacheline_1_hit && s2_double_line && !s2_mmio 466 val hit_0_miss_1 = RegNext(s1_fire) && cacheline_0_hit && cacheline_1_miss && s2_double_line && !s2_has_except && !s2_mmio 467 val miss_0_hit_1 = RegNext(s1_fire) && cacheline_0_miss && cacheline_1_hit && s2_double_line && !s2_has_except && !s2_mmio 468 val miss_0_miss_1 = RegNext(s1_fire) && cacheline_0_miss && cacheline_1_miss && s2_double_line && !s2_has_except && !s2_mmio 469 470 val hit_0_except_1 = RegNext(s1_fire) && s2_double_line && !s2_except(0) && s2_except(1) && cacheline_0_hit 471 val miss_0_except_1 = RegNext(s1_fire) && s2_double_line && !s2_except(0) && s2_except(1) && cacheline_0_miss 472 val except_0 = RegNext(s1_fire) && s2_except(0) 473 474 def holdReleaseLatch(valid: Bool, release: Bool, flush: Bool): Bool ={ 475 val bit = RegInit(false.B) 476 when(flush) { bit := false.B } 477 .elsewhen(valid && !release) { bit := true.B } 478 .elsewhen(release) { bit := false.B } 479 bit || valid 480 } 481 482 /*** miss/hit pattern latch: <Control Signal> latch the miss/hit patter if pipeline stop ***/ 483 val miss_0_hit_1_latch = holdReleaseLatch(valid = miss_0_hit_1, release = s2_fire, flush = false.B) 484 val miss_0_miss_1_latch = holdReleaseLatch(valid = miss_0_miss_1, release = s2_fire, flush = false.B) 485 val only_0_miss_latch = holdReleaseLatch(valid = only_0_miss, release = s2_fire, flush = false.B) 486 val hit_0_miss_1_latch = holdReleaseLatch(valid = hit_0_miss_1, release = s2_fire, flush = false.B) 487 488 val miss_0_except_1_latch = holdReleaseLatch(valid = miss_0_except_1, release = s2_fire, flush = false.B) 489 val except_0_latch = holdReleaseLatch(valid = except_0, release = s2_fire, flush = false.B) 490 val hit_0_except_1_latch = holdReleaseLatch(valid = hit_0_except_1, release = s2_fire, flush = false.B) 491 492 val only_0_hit_latch = holdReleaseLatch(valid = only_0_hit, release = s2_fire, flush = false.B) 493 val hit_0_hit_1_latch = holdReleaseLatch(valid = hit_0_hit_1, release = s2_fire, flush = false.B) 494 495 496 /*** secondary miss judgment ***/ 497 498 def waitSecondComeIn(missState: UInt): Bool = (missState === m_wait_sec_miss) 499 500 def getMissSituat(slotNum : Int, missNum : Int ) :Bool = { 501 RegNext(s1_fire) && 502 RegNext(missSlot(slotNum).m_vSetIdx === s1_req_vsetIdx(missNum)) && 503 RegNext(missSlot(slotNum).m_pTag === s1_req_ptags(missNum)) && 504 !s2_port_hit(missNum) && 505 waitSecondComeIn(missStateQueue(slotNum)) 506 } 507 508 val miss_0_s2_0 = getMissSituat(slotNum = 0, missNum = 0) 509 val miss_0_s2_1 = getMissSituat(slotNum = 0, missNum = 1) 510 val miss_1_s2_0 = getMissSituat(slotNum = 1, missNum = 0) 511 val miss_1_s2_1 = getMissSituat(slotNum = 1, missNum = 1) 512 513 val miss_0_s2_0_latch = holdReleaseLatch(valid = miss_0_s2_0, release = s2_fire, flush = false.B) 514 val miss_0_s2_1_latch = holdReleaseLatch(valid = miss_0_s2_1, release = s2_fire, flush = false.B) 515 val miss_1_s2_0_latch = holdReleaseLatch(valid = miss_1_s2_0, release = s2_fire, flush = false.B) 516 val miss_1_s2_1_latch = holdReleaseLatch(valid = miss_1_s2_1, release = s2_fire, flush = false.B) 517 518 519 val slot_0_solve = fix_sec_miss(0) || fix_sec_miss(1) 520 val slot_1_solve = fix_sec_miss(2) || fix_sec_miss(3) 521 val slot_slove = VecInit(Seq(slot_0_solve, slot_1_solve)) 522 523 fix_sec_miss := VecInit(Seq(miss_0_s2_0_latch, miss_0_s2_1_latch, miss_1_s2_0_latch, miss_1_s2_1_latch)) 524 525 /*** reserved data for secondary miss ***/ 526 527 reservedRefillData(0) := DataHoldBypass(data = missSlot(0).m_data, valid = miss_0_s2_0 || miss_0_s2_1) 528 reservedRefillData(1) := DataHoldBypass(data = missSlot(1).m_data, valid = miss_1_s2_0 || miss_1_s2_1) 529 530 /*** miss state machine ***/ 531 532 //deal with not-cache-hit pmp af 533 val only_pmp_af = Wire(Vec(2, Bool())) 534 only_pmp_af(0) := s2_except_pmp_af(0) && cacheline_0_miss && !s2_except(0) && s2_valid 535 only_pmp_af(1) := s2_except_pmp_af(1) && cacheline_1_miss && !s2_except(1) && s2_valid && s2_double_line 536 537 switch(wait_state){ 538 is(wait_idle){ 539 when(only_pmp_af(0) || only_pmp_af(1) || s2_mmio){ 540 //should not send req to MissUnit when there is an access exception in PMP 541 //But to avoid using pmp exception in control signal (like s2_fire), should delay 1 cycle. 542 //NOTE: pmp exception cache line also could hit in ICache, but the result is meaningless. Just give the exception signals. 543 wait_state := wait_finish 544 }.elsewhen(miss_0_except_1_latch){ 545 wait_state := Mux(toMSHR(0).ready, wait_queue_ready ,wait_idle ) 546 }.elsewhen( only_0_miss_latch || miss_0_hit_1_latch){ 547 wait_state := Mux(toMSHR(0).ready, wait_queue_ready ,wait_idle ) 548 }.elsewhen(hit_0_miss_1_latch){ 549 wait_state := Mux(toMSHR(1).ready, wait_queue_ready ,wait_idle ) 550 }.elsewhen( miss_0_miss_1_latch ){ 551 wait_state := Mux(toMSHR(0).ready && toMSHR(1).ready, wait_queue_ready ,wait_idle) 552 } 553 } 554 555 is(wait_queue_ready){ 556 wait_state := wait_send_req 557 } 558 559 is(wait_send_req) { 560 when(miss_0_except_1_latch || only_0_miss_latch || hit_0_miss_1_latch || miss_0_hit_1_latch){ 561 wait_state := wait_one_resp 562 }.elsewhen( miss_0_miss_1_latch ){ 563 wait_state := wait_two_resp 564 } 565 } 566 567 is(wait_one_resp) { 568 when( (miss_0_except_1_latch ||only_0_miss_latch || miss_0_hit_1_latch) && fromMSHR(0).fire()){ 569 wait_state := wait_finish 570 }.elsewhen( hit_0_miss_1_latch && fromMSHR(1).fire()){ 571 wait_state := wait_finish 572 } 573 } 574 575 is(wait_two_resp) { 576 when(fromMSHR(0).fire() && fromMSHR(1).fire()){ 577 wait_state := wait_finish 578 }.elsewhen( !fromMSHR(0).fire() && fromMSHR(1).fire() ){ 579 wait_state := wait_0_resp 580 }.elsewhen(fromMSHR(0).fire() && !fromMSHR(1).fire()){ 581 wait_state := wait_1_resp 582 } 583 } 584 585 is(wait_0_resp) { 586 when(fromMSHR(0).fire()){ 587 wait_state := wait_finish 588 } 589 } 590 591 is(wait_1_resp) { 592 when(fromMSHR(1).fire()){ 593 wait_state := wait_finish 594 } 595 } 596 597 is(wait_finish) {when(s2_fire) {wait_state := wait_idle } 598 } 599 } 600 601 602 /*** send request to MissUnit ***/ 603 604 (0 until 2).map { i => 605 if(i == 1) toMSHR(i).valid := (hit_0_miss_1_latch || miss_0_miss_1_latch) && wait_state === wait_queue_ready && !s2_mmio 606 else toMSHR(i).valid := (only_0_miss_latch || miss_0_hit_1_latch || miss_0_miss_1_latch || miss_0_except_1_latch) && wait_state === wait_queue_ready && !s2_mmio 607 toMSHR(i).bits.paddr := s2_req_paddr(i) 608 toMSHR(i).bits.vaddr := s2_req_vaddr(i) 609 toMSHR(i).bits.waymask := s2_waymask(i) 610 toMSHR(i).bits.coh := s2_victim_coh(i) 611 612 613 when(toMSHR(i).fire() && missStateQueue(i) === m_invalid){ 614 missStateQueue(i) := m_valid 615 missSlot(i).m_vSetIdx := s2_req_vsetIdx(i) 616 missSlot(i).m_pTag := get_phy_tag(s2_req_paddr(i)) 617 } 618 619 when(fromMSHR(i).fire() && missStateQueue(i) === m_valid ){ 620 missStateQueue(i) := m_refilled 621 missSlot(i).m_data := fromMSHR(i).bits.data 622 missSlot(i).m_corrupt := fromMSHR(i).bits.corrupt 623 } 624 625 626 when(s2_fire && missStateQueue(i) === m_refilled){ 627 missStateQueue(i) := m_wait_sec_miss 628 } 629 630 /*** Only the first cycle to check whether meet the secondary miss ***/ 631 when(missStateQueue(i) === m_wait_sec_miss){ 632 /*** The seondary req has been fix by this slot and another also hit || the secondary req for other cacheline and hit ***/ 633 when((slot_slove(i) && s2_fire) || (!slot_slove(i) && s2_fire) ) { 634 missStateQueue(i) := m_invalid 635 } 636 /*** The seondary req has been fix by this slot but another miss/f3 not ready || the seondary req for other cacheline and miss ***/ 637 .elsewhen((slot_slove(i) && !s2_fire && s2_valid) || (s2_valid && !slot_slove(i) && !s2_fire) ){ 638 missStateQueue(i) := m_check_final 639 } 640 } 641 642 when(missStateQueue(i) === m_check_final && toMSHR(i).fire()){ 643 missStateQueue(i) := m_valid 644 missSlot(i).m_vSetIdx := s2_req_vsetIdx(i) 645 missSlot(i).m_pTag := get_phy_tag(s2_req_paddr(i)) 646 }.elsewhen(missStateQueue(i) === m_check_final) { 647 missStateQueue(i) := m_invalid 648 } 649 } 650 651 io.prefetchEnable := false.B 652 io.prefetchDisable := false.B 653 when(toMSHR.map(_.valid).reduce(_||_)){ 654 missSwitchBit := true.B 655 io.prefetchEnable := true.B 656 }.elsewhen(missSwitchBit && s2_fetch_finish){ 657 missSwitchBit := false.B 658 io.prefetchDisable := true.B 659 } 660 661 662 val miss_all_fix = wait_state === wait_finish 663 664 s2_fetch_finish := ((s2_valid && s2_fixed_hit) || miss_all_fix || hit_0_except_1_latch || except_0_latch) 665 666 /** update replacement status register: 0 is hit access/ 1 is miss access */ 667 (touch_ways zip touch_sets).zipWithIndex.map{ case((t_w,t_s), i) => 668 t_s(0) := s2_req_vsetIdx(i) 669 t_w(0).valid := s2_valid && s2_port_hit(i) 670 t_w(0).bits := OHToUInt(s2_tag_match_vec(i)) 671 672 t_s(1) := s2_req_vsetIdx(i) 673 t_w(1).valid := s2_valid && !s2_port_hit(i) 674 t_w(1).bits := OHToUInt(s2_waymask(i)) 675 } 676 677 //** use hit one-hot select data 678 val s2_hit_datas = VecInit(s2_data_cacheline.zipWithIndex.map { case(bank, i) => 679 val port_hit_data = Mux1H(s2_tag_match_vec(i).asUInt, bank) 680 port_hit_data 681 }) 682 683 val s2_register_datas = Wire(Vec(2, UInt(blockBits.W))) 684 685 s2_register_datas.zipWithIndex.map{case(bank,i) => 686 // if(i == 0) bank := Mux(s2_port_hit(i), s2_hit_datas(i), Mux(miss_0_s2_0_latch,reservedRefillData(0), Mux(miss_1_s2_0_latch,reservedRefillData(1), missSlot(0).m_data))) 687 // else bank := Mux(s2_port_hit(i), s2_hit_datas(i), Mux(miss_0_s2_1_latch,reservedRefillData(0), Mux(miss_1_s2_1_latch,reservedRefillData(1), missSlot(1).m_data))) 688 if(i == 0) bank := Mux(miss_0_s2_0_latch,reservedRefillData(0), Mux(miss_1_s2_0_latch,reservedRefillData(1), missSlot(0).m_data)) 689 else bank := Mux(miss_0_s2_1_latch,reservedRefillData(0), Mux(miss_1_s2_1_latch,reservedRefillData(1), missSlot(1).m_data)) 690 } 691 692 /** response to IFU */ 693 694 (0 until PortNumber).map{ i => 695 if(i ==0) toIFU(i).valid := s2_fire 696 else toIFU(i).valid := s2_fire && s2_double_line 697 //when select is high, use sramData. Otherwise, use registerData. 698 toIFU(i).bits.registerData := s2_register_datas(i) 699 toIFU(i).bits.sramData := s2_hit_datas(i) 700 toIFU(i).bits.select := s2_port_hit(i) 701 toIFU(i).bits.paddr := s2_req_paddr(i) 702 toIFU(i).bits.vaddr := s2_req_vaddr(i) 703 toIFU(i).bits.tlbExcp.pageFault := s2_except_pf(i) 704 toIFU(i).bits.tlbExcp.accessFault := s2_except_tlb_af(i) || missSlot(i).m_corrupt || s2_except_pmp_af(i) 705 toIFU(i).bits.tlbExcp.mmio := s2_mmio 706 707 when(RegNext(s2_fire && missSlot(i).m_corrupt)){ 708 io.errors(i).valid := true.B 709 io.errors(i).report_to_beu := false.B // l2 should have report that to bus error unit, no need to do it again 710 io.errors(i).paddr := RegNext(s2_req_paddr(i)) 711 io.errors(i).source.tag := false.B 712 io.errors(i).source.data := false.B 713 io.errors(i).source.l2 := true.B 714 } 715 } 716 717 io.perfInfo.only_0_hit := only_0_hit_latch 718 io.perfInfo.only_0_miss := only_0_miss_latch 719 io.perfInfo.hit_0_hit_1 := hit_0_hit_1_latch 720 io.perfInfo.hit_0_miss_1 := hit_0_miss_1_latch 721 io.perfInfo.miss_0_hit_1 := miss_0_hit_1_latch 722 io.perfInfo.miss_0_miss_1 := miss_0_miss_1_latch 723 io.perfInfo.hit_0_except_1 := hit_0_except_1_latch 724 io.perfInfo.miss_0_except_1 := miss_0_except_1_latch 725 io.perfInfo.except_0 := except_0_latch 726 io.perfInfo.bank_hit(0) := only_0_miss_latch || hit_0_hit_1_latch || hit_0_miss_1_latch || hit_0_except_1_latch 727 io.perfInfo.bank_hit(1) := miss_0_hit_1_latch || hit_0_hit_1_latch 728 io.perfInfo.hit := hit_0_hit_1_latch || only_0_hit_latch || hit_0_except_1_latch || except_0_latch 729 730 /** <PERF> fetch bubble generated by icache miss*/ 731 732 XSPerfAccumulate("icache_bubble_s2_miss", s2_valid && !s2_fetch_finish ) 733 734 val tlb_miss_vec = VecInit((0 until PortNumber).map(i => toITLB(i).valid && s0_can_go && fromITLB(i).bits.miss)) 735 val tlb_has_miss = tlb_miss_vec.reduce(_ || _) 736 XSPerfAccumulate("icache_bubble_s0_tlb_miss", s0_valid && tlb_has_miss ) 737} 738