1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend.icache 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.tilelink.ClientStates 23import xiangshan._ 24import xiangshan.cache.mmu._ 25import utils._ 26import xiangshan.backend.fu.{PMPReqBundle, PMPRespBundle} 27 28class ICacheMainPipeReq(implicit p: Parameters) extends ICacheBundle 29{ 30 val vaddr = UInt(VAddrBits.W) 31 def vsetIdx = get_idx(vaddr) 32} 33 34class ICacheMainPipeResp(implicit p: Parameters) extends ICacheBundle 35{ 36 val vaddr = UInt(VAddrBits.W) 37 val readData = UInt(blockBits.W) 38 val paddr = UInt(PAddrBits.W) 39 val tlbExcp = new Bundle{ 40 val pageFault = Bool() 41 val accessFault = Bool() 42 val mmio = Bool() 43 } 44} 45 46class ICacheMainPipeBundle(implicit p: Parameters) extends ICacheBundle 47{ 48 val req = Flipped(DecoupledIO(new ICacheMainPipeReq)) 49 val resp = ValidIO(new ICacheMainPipeResp) 50} 51 52class ICacheMetaReqBundle(implicit p: Parameters) extends ICacheBundle{ 53 val toIMeta = Decoupled(new ICacheReadBundle) 54 val fromIMeta = Input(new ICacheMetaRespBundle) 55} 56 57class ICacheDataReqBundle(implicit p: Parameters) extends ICacheBundle{ 58 val toIData = Decoupled(new ICacheReadBundle) 59 val fromIData = Input(new ICacheDataRespBundle) 60} 61 62class ICacheMSHRBundle(implicit p: Parameters) extends ICacheBundle{ 63 val toMSHR = Decoupled(new ICacheMissReq) 64 val fromMSHR = Flipped(ValidIO(new ICacheMissResp)) 65} 66 67class ICachePMPBundle(implicit p: Parameters) extends ICacheBundle{ 68 val req = Valid(new PMPReqBundle()) 69 val resp = Input(new PMPRespBundle()) 70} 71 72class ICachePerfInfo(implicit p: Parameters) extends ICacheBundle{ 73 val only_0_hit = Bool() 74 val only_0_miss = Bool() 75 val hit_0_hit_1 = Bool() 76 val hit_0_miss_1 = Bool() 77 val miss_0_hit_1 = Bool() 78 val miss_0_miss_1 = Bool() 79 val hit_0_except_1 = Bool() 80 val miss_0_except_1 = Bool() 81 val except_0 = Bool() 82 val bank_hit = Vec(2,Bool()) 83 val hit = Bool() 84} 85 86class ICacheMainPipeInterface(implicit p: Parameters) extends ICacheBundle { 87 /*** internal interface ***/ 88 val metaArray = new ICacheMetaReqBundle 89 val dataArray = new ICacheDataReqBundle 90 val mshr = Vec(PortNumber, new ICacheMSHRBundle) 91 val errors = Output(Vec(PortNumber, new L1CacheErrorInfo)) 92 /*** outside interface ***/ 93 val fetch = Vec(PortNumber, new ICacheMainPipeBundle) 94 val pmp = Vec(PortNumber, new ICachePMPBundle) 95 val itlb = Vec(PortNumber, new TlbRequestIO) 96 val respStall = Input(Bool()) 97 val perfInfo = Output(new ICachePerfInfo) 98 99 val prefetchEnable = Output(Bool()) 100 val prefetchDisable = Output(Bool()) 101 val csr_parity_enable = Input(Bool()) 102 103} 104 105class ICacheMainPipe(implicit p: Parameters) extends ICacheModule 106{ 107 val io = IO(new ICacheMainPipeInterface) 108 109 /** Input/Output port */ 110 val (fromIFU, toIFU) = (io.fetch.map(_.req), io.fetch.map(_.resp)) 111 val (toMeta, metaResp) = (io.metaArray.toIMeta, io.metaArray.fromIMeta) 112 val (toData, dataResp) = (io.dataArray.toIData, io.dataArray.fromIData) 113 val (toMSHR, fromMSHR) = (io.mshr.map(_.toMSHR), io.mshr.map(_.fromMSHR)) 114 val (toITLB, fromITLB) = (io.itlb.map(_.req), io.itlb.map(_.resp)) 115 val (toPMP, fromPMP) = (io.pmp.map(_.req), io.pmp.map(_.resp)) 116 117 /** pipeline control signal */ 118 val s1_ready, s2_ready = Wire(Bool()) 119 val s0_fire, s1_fire , s2_fire = Wire(Bool()) 120 121 val missSwitchBit = RegInit(false.B) 122 123 /** replacement status register */ 124 val touch_sets = Seq.fill(2)(Wire(Vec(2, UInt(log2Ceil(nSets/2).W)))) 125 val touch_ways = Seq.fill(2)(Wire(Vec(2, Valid(UInt(log2Ceil(nWays).W)))) ) 126 127 /** 128 ****************************************************************************** 129 * ICache Stage 0 130 * - send req to ITLB and wait for tlb miss fixing 131 * - send req to Meta/Data SRAM 132 ****************************************************************************** 133 */ 134 135 /** s0 control */ 136 val s0_valid = fromIFU.map(_.valid).reduce(_||_) 137 val s0_req_vaddr = VecInit(fromIFU.map(_.bits.vaddr)) 138 val s0_req_vsetIdx = VecInit(fromIFU.map(_.bits.vsetIdx)) 139 val s0_only_first = fromIFU(0).valid && !fromIFU(0).valid 140 val s0_double_line = fromIFU(0).valid && fromIFU(1).valid 141 142 val s0_final_valid = s0_valid 143 val s0_final_vaddr = s0_req_vaddr 144 val s0_final_vsetIdx = s0_req_vsetIdx 145 val s0_final_only_first = s0_only_first 146 val s0_final_double_line = s0_double_line 147 148 /** SRAM request */ 149 val fetch_req = List(toMeta, toData) 150 for(i <- 0 until 2) { 151 // fetch_req(i).valid := (s0_valid || tlb_slot.valid) && !missSwitchBit 152 fetch_req(i).valid := s0_valid && !missSwitchBit 153 fetch_req(i).bits.isDoubleLine := s0_final_double_line 154 fetch_req(i).bits.vSetIdx := s0_final_vsetIdx 155 } 156 157 /** s0 tlb **/ 158 toITLB(0).valid := s0_valid 159 toITLB(0).bits.size := 3.U // TODO: fix the size 160 toITLB(0).bits.vaddr := s0_req_vaddr(0) 161 toITLB(0).bits.debug.pc := s0_req_vaddr(0) 162 163 toITLB(1).valid := s0_valid && s0_double_line 164 toITLB(1).bits.size := 3.U // TODO: fix the size 165 toITLB(1).bits.vaddr := s0_req_vaddr(1) 166 toITLB(1).bits.debug.pc := s0_req_vaddr(1) 167 168 toITLB.map{port => 169 port.bits.cmd := TlbCmd.exec 170 port.bits.debug.robIdx := DontCare 171 port.bits.debug.isFirstIssue := DontCare 172 } 173 174 /** ITLB & ICACHE sync case 175 * when icache is not ready, but itlb is ready 176 * because itlb is non-block, then the req will take the port 177 * then itlb will unset the ready?? itlb is wrongly blocked. 178 * Solution: maybe give itlb a signal to tell whether acquire the slot? 179 */ 180 181 val itlb_can_go = toITLB(0).ready && toITLB(1).ready 182 val icache_can_go = fetch_req(0).ready && fetch_req(1).ready 183 val pipe_can_go = !missSwitchBit && s1_ready 184 val s0_can_go = itlb_can_go && icache_can_go && pipe_can_go 185 val s0_fetch_fire = s0_valid && s0_can_go 186 s0_fire := s0_fetch_fire 187 toITLB.map{port => port.bits.kill := !icache_can_go || !pipe_can_go} 188 189 //TODO: fix GTimer() condition 190 fromIFU.map(_.ready := s0_can_go) //&& GTimer() > 500.U ) 191 192 /** 193 ****************************************************************************** 194 * ICache Stage 1 195 * - get tlb resp data (exceptiong info and physical addresses) 196 * - get Meta/Data SRAM read responses (latched for pipeline stop) 197 * - tag compare/hit check 198 ****************************************************************************** 199 */ 200 201 /** s1 control */ 202 203 val s1_valid = generatePipeControl(lastFire = s0_fire, thisFire = s1_fire, thisFlush = false.B, lastFlush = false.B) 204 205 val s1_req_vaddr = RegEnable(s0_final_vaddr, s0_fire) 206 val s1_req_vsetIdx = RegEnable(s0_final_vsetIdx, s0_fire) 207 val s1_only_first = RegEnable(s0_final_only_first, s0_fire) 208 val s1_double_line = RegEnable(s0_final_double_line, s0_fire) 209 //val s1_tlb_miss = RegEnable(tlb_slot.valid, s0_fire) 210 211 /** tlb response latch for pipeline stop */ 212 val tlb_back = fromITLB.map(_.fire()) 213 val tlb_need_back = VecInit((0 until PortNumber).map(i => ValidHold(s0_fire && toITLB(i).fire(), s1_fire, false.B))) 214 val tlb_already_recv = RegInit(VecInit(Seq.fill(PortNumber)(false.B))) 215 val tlb_ready_recv = VecInit((0 until PortNumber).map(i => RegNext(s0_fire, false.B) || (s1_valid && !tlb_already_recv(i)))) 216 val tlb_resp_valid = Wire(Vec(2, Bool())) 217 for (i <- 0 until PortNumber) { 218 tlb_resp_valid(i) := tlb_already_recv(i) || (tlb_ready_recv(i) && tlb_back(i)) 219 when (tlb_already_recv(i) && s1_fire) { 220 tlb_already_recv(i) := false.B 221 } 222 when (tlb_back(i) && tlb_ready_recv(i) && !s1_fire) { 223 tlb_already_recv(i) := true.B 224 } 225 fromITLB(i).ready := tlb_ready_recv(i) 226 } 227 assert(RegNext(Cat((0 until PortNumber).map(i => tlb_need_back(i) || !tlb_resp_valid(i))).andR(), true.B), 228 "when tlb should not back, tlb should not resp valid") 229 assert(RegNext(!s1_valid || Cat(tlb_need_back).orR, true.B), "when s1_valid, need at least one tlb_need_back") 230 assert(RegNext(s1_valid || !Cat(tlb_need_back).orR, true.B), "when !s1_valid, all the tlb_need_back should be false") 231 assert(RegNext(s1_valid || !Cat(tlb_already_recv).orR, true.B), "when !s1_valid, should not tlb_already_recv") 232 assert(RegNext(s1_valid || !Cat(tlb_resp_valid).orR, true.B), "when !s1_valid, should not tlb_resp_valid") 233 234 val tlbRespPAddr = VecInit((0 until PortNumber).map(i => ResultHoldBypass(valid = tlb_back(i), data = fromITLB(i).bits.paddr))) 235 val tlbExcpPF = VecInit((0 until PortNumber).map(i => ResultHoldBypass(valid = tlb_back(i), data = fromITLB(i).bits.excp.pf.instr) && tlb_need_back(i))) 236 val tlbExcpAF = VecInit((0 until PortNumber).map(i => ResultHoldBypass(valid = tlb_back(i), data = fromITLB(i).bits.excp.af.instr) && tlb_need_back(i))) 237 val tlbExcp = VecInit((0 until PortNumber).map(i => tlbExcpPF(i) || tlbExcpPF(i))) 238 239 val tlbRespAllValid = Cat((0 until PortNumber).map(i => !tlb_need_back(i) || tlb_resp_valid(i))).andR 240 s1_ready := s2_ready && tlbRespAllValid || !s1_valid 241 s1_fire := s1_valid && tlbRespAllValid && s2_ready 242 243 /** s1 hit check/tag compare */ 244 val s1_req_paddr = tlbRespPAddr 245 val s1_req_ptags = VecInit(s1_req_paddr.map(get_phy_tag(_))) 246 247 val s1_meta_ptags = ResultHoldBypass(data = metaResp.tags, valid = RegNext(s0_fire)) 248 val s1_meta_cohs = ResultHoldBypass(data = metaResp.cohs, valid = RegNext(s0_fire)) 249 val s1_meta_errors = ResultHoldBypass(data = metaResp.errors, valid = RegNext(s0_fire)) 250 251 val s1_data_cacheline = ResultHoldBypass(data = dataResp.datas, valid = RegNext(s0_fire)) 252 val s1_data_errorBits = ResultHoldBypass(data = dataResp.codes, valid = RegNext(s0_fire)) 253 254 val s1_tag_eq_vec = VecInit((0 until PortNumber).map( p => VecInit((0 until nWays).map( w => s1_meta_ptags(p)(w) === s1_req_ptags(p) )))) 255 val s1_tag_match_vec = VecInit((0 until PortNumber).map( k => VecInit(s1_tag_eq_vec(k).zipWithIndex.map{ case(way_tag_eq, w) => way_tag_eq && s1_meta_cohs(k)(w).isValid()}))) 256 val s1_tag_match = VecInit(s1_tag_match_vec.map(vector => ParallelOR(vector))) 257 258 val s1_port_hit = VecInit(Seq(s1_tag_match(0) && s1_valid && !tlbExcp(0), s1_tag_match(1) && s1_valid && s1_double_line && !tlbExcp(1) )) 259 val s1_bank_miss = VecInit(Seq(!s1_tag_match(0) && s1_valid && !tlbExcp(0), !s1_tag_match(1) && s1_valid && s1_double_line && !tlbExcp(1) )) 260 val s1_hit = (s1_port_hit(0) && s1_port_hit(1)) || (!s1_double_line && s1_port_hit(0)) 261 262 /** choose victim cacheline */ 263 val replacers = Seq.fill(PortNumber)(ReplacementPolicy.fromString(cacheParams.replacer,nWays,nSets/PortNumber)) 264 val s1_victim_oh = ResultHoldBypass(data = VecInit(replacers.zipWithIndex.map{case (replacer, i) => UIntToOH(replacer.way(s1_req_vsetIdx(i)))}), valid = RegNext(s0_fire)) 265 266 val s1_victim_coh = VecInit(s1_victim_oh.zipWithIndex.map {case(oh, port) => Mux1H(oh, s1_meta_cohs(port))}) 267 268 assert(PopCount(s1_tag_match_vec(0)) <= 1.U && PopCount(s1_tag_match_vec(1)) <= 1.U, "Multiple hit in main pipe") 269 270 ((replacers zip touch_sets) zip touch_ways).map{case ((r, s),w) => r.access(s,w)} 271 272 val s1_hit_data = VecInit(s1_data_cacheline.zipWithIndex.map { case(bank, i) => 273 val port_hit_data = Mux1H(s1_tag_match_vec(i).asUInt, bank) 274 port_hit_data 275 }) 276 277 /** <PERF> replace victim way number */ 278 279 (0 until nWays).map{ w => 280 XSPerfAccumulate("line_0_hit_way_" + Integer.toString(w, 10), s1_fire && s1_port_hit(0) && OHToUInt(s1_tag_match_vec(0)) === w.U) 281 } 282 283 (0 until nWays).map{ w => 284 XSPerfAccumulate("line_0_victim_way_" + Integer.toString(w, 10), s1_fire && !s1_port_hit(0) && OHToUInt(s1_victim_oh(0)) === w.U) 285 } 286 287 (0 until nWays).map{ w => 288 XSPerfAccumulate("line_1_hit_way_" + Integer.toString(w, 10), s1_fire && s1_double_line && s1_port_hit(1) && OHToUInt(s1_tag_match_vec(1)) === w.U) 289 } 290 291 (0 until nWays).map{ w => 292 XSPerfAccumulate("line_1_victim_way_" + Integer.toString(w, 10), s1_fire && s1_double_line && !s1_port_hit(1) && OHToUInt(s1_victim_oh(1)) === w.U) 293 } 294 295 /** 296 ****************************************************************************** 297 * ICache Stage 2 298 * - send request to MSHR if ICache miss 299 * - generate secondary miss status/data registers 300 * - response to IFU 301 ****************************************************************************** 302 */ 303 304 /** s2 control */ 305 val s2_fetch_finish = Wire(Bool()) 306 307 val s2_valid = generatePipeControl(lastFire = s1_fire, thisFire = s2_fire, thisFlush = false.B, lastFlush = false.B) 308 val s2_miss_available = Wire(Bool()) 309 310 s2_ready := (s2_valid && s2_fetch_finish && !io.respStall) || (!s2_valid && s2_miss_available) 311 s2_fire := s2_valid && s2_fetch_finish && !io.respStall 312 313 /** s2 data */ 314 val mmio = fromPMP.map(port => port.mmio) // TODO: handle it 315 316 val (s2_req_paddr , s2_req_vaddr) = (RegEnable(s1_req_paddr, s1_fire), RegEnable(s1_req_vaddr, s1_fire)) 317 val s2_req_vsetIdx = RegEnable(s1_req_vsetIdx, s1_fire) 318 val s2_req_ptags = RegEnable(s1_req_ptags, s1_fire) 319 val s2_only_first = RegEnable(s1_only_first, s1_fire) 320 val s2_double_line = RegEnable(s1_double_line, s1_fire) 321 val s2_hit = RegEnable(s1_hit , s1_fire) 322 val s2_port_hit = RegEnable(s1_port_hit, s1_fire) 323 val s2_bank_miss = RegEnable(s1_bank_miss, s1_fire) 324 val s2_waymask = RegEnable(s1_victim_oh, s1_fire) 325 val s2_victim_coh = RegEnable(s1_victim_coh, s1_fire) 326 val s2_tag_match_vec = RegEnable(s1_tag_match_vec, s1_fire) 327 328 assert(RegNext(!s2_valid || s2_req_paddr(0)(11,0) === s2_req_vaddr(0)(11,0), true.B)) 329 330 /** status imply that s2 is a secondary miss (no need to resend miss request) */ 331 val sec_meet_vec = Wire(Vec(2, Bool())) 332 val s2_fixed_hit_vec = VecInit((0 until 2).map(i => s2_port_hit(i) || sec_meet_vec(i))) 333 val s2_fixed_hit = (s2_valid && s2_fixed_hit_vec(0) && s2_fixed_hit_vec(1) && s2_double_line) || (s2_valid && s2_fixed_hit_vec(0) && !s2_double_line) 334 335 val s2_meta_errors = RegEnable(s1_meta_errors, s1_fire) 336 val s2_data_errorBits = RegEnable(s1_data_errorBits, s1_fire) 337 val s2_data_cacheline = RegEnable(s1_data_cacheline, s1_fire) 338 339 val s2_data_errors = Wire(Vec(PortNumber,Vec(nWays, Bool()))) 340 341 (0 until PortNumber).map{ i => 342 val read_datas = s2_data_cacheline(i).asTypeOf(Vec(nWays,Vec(dataCodeUnitNum, UInt(dataCodeUnit.W)))) 343 val read_codes = s2_data_errorBits(i).asTypeOf(Vec(nWays,Vec(dataCodeUnitNum, UInt(dataCodeBits.W)))) 344 val data_full_wayBits = VecInit((0 until nWays).map( w => 345 VecInit((0 until dataCodeUnitNum).map(u => 346 Cat(read_codes(w)(u), read_datas(w)(u)))))) 347 val data_error_wayBits = VecInit((0 until nWays).map( w => 348 VecInit((0 until dataCodeUnitNum).map(u => 349 cacheParams.dataCode.decode(data_full_wayBits(w)(u)).error )))) 350 if(i == 0){ 351 (0 until nWays).map{ w => 352 s2_data_errors(i)(w) := RegNext(RegNext(s1_fire)) && RegNext(data_error_wayBits(w)).reduce(_||_) 353 } 354 } else { 355 (0 until nWays).map{ w => 356 s2_data_errors(i)(w) := RegNext(RegNext(s1_fire)) && RegNext(RegNext(s1_double_line)) && RegNext(data_error_wayBits(w)).reduce(_||_) 357 } 358 } 359 } 360 361 val s2_parity_meta_error = VecInit((0 until PortNumber).map(i => s2_meta_errors(i).reduce(_||_) && io.csr_parity_enable)) 362 val s2_parity_data_error = VecInit((0 until PortNumber).map(i => s2_data_errors(i).reduce(_||_) && io.csr_parity_enable)) 363 val s2_parity_error = VecInit((0 until PortNumber).map(i => RegNext(s2_parity_meta_error(i)) || s2_parity_data_error(i))) 364 365 for(i <- 0 until PortNumber){ 366 io.errors(i).valid := RegNext(s2_parity_error(i) && RegNext(RegNext(s1_fire))) 367 io.errors(i).report_to_beu := RegNext(s2_parity_error(i) && RegNext(RegNext(s1_fire))) 368 io.errors(i).paddr := RegNext(RegNext(s2_req_paddr(i))) 369 io.errors(i).source := DontCare 370 io.errors(i).source.tag := RegNext(RegNext(s2_parity_meta_error(i))) 371 io.errors(i).source.data := RegNext(s2_parity_data_error(i)) 372 io.errors(i).source.l2 := false.B 373 io.errors(i).opType := DontCare 374 io.errors(i).opType.fetch := true.B 375 } 376 XSError(s2_parity_error.reduce(_||_) && RegNext(RegNext(s1_fire)), "ICache has parity error in MainPaipe!") 377 378 379 /** exception and pmp logic **/ 380 //PMP Result 381 val s2_tlb_need_back = VecInit((0 until PortNumber).map(i => ValidHold(tlb_need_back(i) && s1_fire, s2_fire, false.B))) 382 val pmpExcpAF = Wire(Vec(PortNumber, Bool())) 383 pmpExcpAF(0) := fromPMP(0).instr && s2_tlb_need_back(0) 384 pmpExcpAF(1) := fromPMP(1).instr && s2_double_line && s2_tlb_need_back(1) 385 //exception information 386 val s2_except_pf = RegEnable(tlbExcpPF, s1_fire) 387 val s2_except_af = VecInit(RegEnable(tlbExcpAF, s1_fire).zip(pmpExcpAF).map{ 388 case(tlbAf, pmpAf) => tlbAf || DataHoldBypass(pmpAf, RegNext(s1_fire)).asBool}) 389 val s2_except = VecInit((0 until 2).map{i => s2_except_pf(i) || s2_except_af(i)}) 390 val s2_has_except = s2_valid && (s2_except_af.reduce(_||_) || s2_except_pf.reduce(_||_)) 391 //MMIO 392 val s2_mmio = DataHoldBypass(io.pmp(0).resp.mmio && !s2_except_af(0) && !s2_except_pf(0), RegNext(s1_fire)).asBool() 393 394 //send physical address to PMP 395 io.pmp.zipWithIndex.map { case (p, i) => 396 p.req.valid := s2_valid && !missSwitchBit 397 p.req.bits.addr := s2_req_paddr(i) 398 p.req.bits.size := 3.U // TODO 399 p.req.bits.cmd := TlbCmd.exec 400 } 401 402 /*** cacheline miss logic ***/ 403 val wait_idle :: wait_queue_ready :: wait_send_req :: wait_two_resp :: wait_0_resp :: wait_1_resp :: wait_one_resp ::wait_finish :: Nil = Enum(8) 404 val wait_state = RegInit(wait_idle) 405 406 val port_miss_fix = VecInit(Seq(fromMSHR(0).fire() && !s2_port_hit(0), fromMSHR(1).fire() && s2_double_line && !s2_port_hit(1) )) 407 408 // secondary miss record registers 409 class MissSlot(implicit p: Parameters) extends ICacheBundle { 410 val m_vSetIdx = UInt(idxBits.W) 411 val m_pTag = UInt(tagBits.W) 412 val m_data = UInt(blockBits.W) 413 val m_corrupt = Bool() 414 } 415 416 val missSlot = Seq.fill(2)(RegInit(0.U.asTypeOf(new MissSlot))) 417 val m_invalid :: m_valid :: m_refilled :: m_flushed :: m_wait_sec_miss :: m_check_final ::Nil = Enum(6) 418 val missStateQueue = RegInit(VecInit(Seq.fill(2)(m_invalid)) ) 419 val reservedRefillData = Wire(Vec(2, UInt(blockBits.W))) 420 421 s2_miss_available := VecInit(missStateQueue.map(entry => entry === m_invalid || entry === m_wait_sec_miss)).reduce(_&&_) 422 423 val fix_sec_miss = Wire(Vec(4, Bool())) 424 val sec_meet_0_miss = fix_sec_miss(0) || fix_sec_miss(2) 425 val sec_meet_1_miss = fix_sec_miss(1) || fix_sec_miss(3) 426 sec_meet_vec := VecInit(Seq(sec_meet_0_miss,sec_meet_1_miss )) 427 428 /*** miss/hit pattern: <Control Signal> only raise at the first cycle of s2_valid ***/ 429 val cacheline_0_hit = (s2_port_hit(0) || sec_meet_0_miss) 430 val cacheline_0_miss = !s2_port_hit(0) && !sec_meet_0_miss 431 432 val cacheline_1_hit = (s2_port_hit(1) || sec_meet_1_miss) 433 val cacheline_1_miss = !s2_port_hit(1) && !sec_meet_1_miss 434 435 val only_0_miss = RegNext(s1_fire) && cacheline_0_miss && !s2_double_line && !s2_has_except && !s2_mmio 436 val only_0_hit = RegNext(s1_fire) && cacheline_0_hit && !s2_double_line && !s2_mmio 437 val hit_0_hit_1 = RegNext(s1_fire) && cacheline_0_hit && cacheline_1_hit && s2_double_line && !s2_mmio 438 val hit_0_miss_1 = RegNext(s1_fire) && cacheline_0_hit && cacheline_1_miss && s2_double_line && !s2_has_except && !s2_mmio 439 val miss_0_hit_1 = RegNext(s1_fire) && cacheline_0_miss && cacheline_1_hit && s2_double_line && !s2_has_except && !s2_mmio 440 val miss_0_miss_1 = RegNext(s1_fire) && cacheline_0_miss && cacheline_1_miss && s2_double_line && !s2_has_except && !s2_mmio 441 442 val hit_0_except_1 = RegNext(s1_fire) && s2_double_line && !s2_except(0) && s2_except(1) && cacheline_0_hit 443 val miss_0_except_1 = RegNext(s1_fire) && s2_double_line && !s2_except(0) && s2_except(1) && cacheline_0_miss 444 val except_0 = RegNext(s1_fire) && s2_except(0) 445 446 def holdReleaseLatch(valid: Bool, release: Bool, flush: Bool): Bool ={ 447 val bit = RegInit(false.B) 448 when(flush) { bit := false.B } 449 .elsewhen(valid && !release) { bit := true.B } 450 .elsewhen(release) { bit := false.B} 451 bit || valid 452 } 453 454 /*** miss/hit pattern latch: <Control Signal> latch the miss/hit patter if pipeline stop ***/ 455 val miss_0_hit_1_latch = holdReleaseLatch(valid = miss_0_hit_1, release = s2_fire, flush = false.B) 456 val miss_0_miss_1_latch = holdReleaseLatch(valid = miss_0_miss_1, release = s2_fire, flush = false.B) 457 val only_0_miss_latch = holdReleaseLatch(valid = only_0_miss, release = s2_fire, flush = false.B) 458 val hit_0_miss_1_latch = holdReleaseLatch(valid = hit_0_miss_1, release = s2_fire, flush = false.B) 459 460 val miss_0_except_1_latch = holdReleaseLatch(valid = miss_0_except_1, release = s2_fire, flush = false.B) 461 val except_0_latch = holdReleaseLatch(valid = except_0, release = s2_fire, flush = false.B) 462 val hit_0_except_1_latch = holdReleaseLatch(valid = hit_0_except_1, release = s2_fire, flush = false.B) 463 464 val only_0_hit_latch = holdReleaseLatch(valid = only_0_hit, release = s2_fire, flush = false.B) 465 val hit_0_hit_1_latch = holdReleaseLatch(valid = hit_0_hit_1, release = s2_fire, flush = false.B) 466 467 468 /*** secondary miss judgment ***/ 469 470 def waitSecondComeIn(missState: UInt): Bool = (missState === m_wait_sec_miss) 471 472 def getMissSituat(slotNum : Int, missNum : Int ) :Bool = { 473 RegNext(s1_fire) && (missSlot(slotNum).m_vSetIdx === s2_req_vsetIdx(missNum)) && (missSlot(slotNum).m_pTag === s2_req_ptags(missNum)) && !s2_port_hit(missNum) && waitSecondComeIn(missStateQueue(slotNum)) //&& !s2_mmio 474 } 475 476 val miss_0_s2_0 = getMissSituat(slotNum = 0, missNum = 0) 477 val miss_0_s2_1 = getMissSituat(slotNum = 0, missNum = 1) 478 val miss_1_s2_0 = getMissSituat(slotNum = 1, missNum = 0) 479 val miss_1_s2_1 = getMissSituat(slotNum = 1, missNum = 1) 480 481 val miss_0_s2_0_latch = holdReleaseLatch(valid = miss_0_s2_0, release = s2_fire, flush = false.B) 482 val miss_0_s2_1_latch = holdReleaseLatch(valid = miss_0_s2_1, release = s2_fire, flush = false.B) 483 val miss_1_s2_0_latch = holdReleaseLatch(valid = miss_1_s2_0, release = s2_fire, flush = false.B) 484 val miss_1_s2_1_latch = holdReleaseLatch(valid = miss_1_s2_1, release = s2_fire, flush = false.B) 485 486 487 val slot_0_solve = fix_sec_miss(0) || fix_sec_miss(1) 488 val slot_1_solve = fix_sec_miss(2) || fix_sec_miss(3) 489 val slot_slove = VecInit(Seq(slot_0_solve, slot_1_solve)) 490 491 fix_sec_miss := VecInit(Seq(miss_0_s2_0_latch, miss_0_s2_1_latch, miss_1_s2_0_latch, miss_1_s2_1_latch)) 492 493 /*** reserved data for secondary miss ***/ 494 495 reservedRefillData(0) := DataHoldBypass(data = missSlot(0).m_data, valid = miss_0_s2_0 || miss_0_s2_1) 496 reservedRefillData(1) := DataHoldBypass(data = missSlot(1).m_data, valid = miss_1_s2_0 || miss_1_s2_1) 497 498 /*** miss state machine ***/ 499 500 switch(wait_state){ 501 is(wait_idle){ 502 when(miss_0_except_1_latch){ 503 wait_state := Mux(toMSHR(0).ready, wait_queue_ready ,wait_idle ) 504 }.elsewhen( only_0_miss_latch || miss_0_hit_1_latch){ 505 wait_state := Mux(toMSHR(0).ready, wait_queue_ready ,wait_idle ) 506 }.elsewhen(hit_0_miss_1_latch){ 507 wait_state := Mux(toMSHR(1).ready, wait_queue_ready ,wait_idle ) 508 }.elsewhen( miss_0_miss_1_latch ){ 509 wait_state := Mux(toMSHR(0).ready && toMSHR(1).ready, wait_queue_ready ,wait_idle) 510 } 511 } 512 513 is(wait_queue_ready){ 514 wait_state := wait_send_req 515 } 516 517 is(wait_send_req) { 518 when(miss_0_except_1_latch || only_0_miss_latch || hit_0_miss_1_latch || miss_0_hit_1_latch){ 519 wait_state := wait_one_resp 520 }.elsewhen( miss_0_miss_1_latch ){ 521 wait_state := wait_two_resp 522 } 523 } 524 525 is(wait_one_resp) { 526 when( (miss_0_except_1_latch ||only_0_miss_latch || miss_0_hit_1_latch) && fromMSHR(0).fire()){ 527 wait_state := wait_finish 528 }.elsewhen( hit_0_miss_1_latch && fromMSHR(1).fire()){ 529 wait_state := wait_finish 530 } 531 } 532 533 is(wait_two_resp) { 534 when(fromMSHR(0).fire() && fromMSHR(1).fire()){ 535 wait_state := wait_finish 536 }.elsewhen( !fromMSHR(0).fire() && fromMSHR(1).fire() ){ 537 wait_state := wait_0_resp 538 }.elsewhen(fromMSHR(0).fire() && !fromMSHR(1).fire()){ 539 wait_state := wait_1_resp 540 } 541 } 542 543 is(wait_0_resp) { 544 when(fromMSHR(0).fire()){ 545 wait_state := wait_finish 546 } 547 } 548 549 is(wait_1_resp) { 550 when(fromMSHR(1).fire()){ 551 wait_state := wait_finish 552 } 553 } 554 555 is(wait_finish) {when(s2_fire) {wait_state := wait_idle } 556 } 557 } 558 559 560 /*** send request to MissUnit ***/ 561 562 (0 until 2).map { i => 563 if(i == 1) toMSHR(i).valid := (hit_0_miss_1_latch || miss_0_miss_1_latch) && wait_state === wait_queue_ready && !s2_mmio 564 else toMSHR(i).valid := (only_0_miss_latch || miss_0_hit_1_latch || miss_0_miss_1_latch || miss_0_except_1_latch) && wait_state === wait_queue_ready && !s2_mmio 565 toMSHR(i).bits.paddr := s2_req_paddr(i) 566 toMSHR(i).bits.vaddr := s2_req_vaddr(i) 567 toMSHR(i).bits.waymask := s2_waymask(i) 568 toMSHR(i).bits.coh := s2_victim_coh(i) 569 570 571 when(toMSHR(i).fire() && missStateQueue(i) === m_invalid){ 572 missStateQueue(i) := m_valid 573 missSlot(i).m_vSetIdx := s2_req_vsetIdx(i) 574 missSlot(i).m_pTag := get_phy_tag(s2_req_paddr(i)) 575 } 576 577 when(fromMSHR(i).fire() && missStateQueue(i) === m_valid ){ 578 missStateQueue(i) := m_refilled 579 missSlot(i).m_data := fromMSHR(i).bits.data 580 missSlot(i).m_corrupt := fromMSHR(i).bits.corrupt 581 } 582 583 584 when(s2_fire && missStateQueue(i) === m_refilled){ 585 missStateQueue(i) := m_wait_sec_miss 586 } 587 588 /*** Only the first cycle to check whether meet the secondary miss ***/ 589 when(missStateQueue(i) === m_wait_sec_miss){ 590 /*** The seondary req has been fix by this slot and another also hit || the secondary req for other cacheline and hit ***/ 591 when((slot_slove(i) && s2_fire) || (!slot_slove(i) && s2_fire) ) { 592 missStateQueue(i) := m_invalid 593 } 594 /*** The seondary req has been fix by this slot but another miss/f3 not ready || the seondary req for other cacheline and miss ***/ 595 .elsewhen((slot_slove(i) && !s2_fire && s2_valid) || (s2_valid && !slot_slove(i) && !s2_fire) ){ 596 missStateQueue(i) := m_check_final 597 } 598 } 599 600 when(missStateQueue(i) === m_check_final && toMSHR(i).fire()){ 601 missStateQueue(i) := m_valid 602 missSlot(i).m_vSetIdx := s2_req_vsetIdx(i) 603 missSlot(i).m_pTag := get_phy_tag(s2_req_paddr(i)) 604 }.elsewhen(missStateQueue(i) === m_check_final) { 605 missStateQueue(i) := m_invalid 606 } 607 } 608 609 io.prefetchEnable := false.B 610 io.prefetchDisable := false.B 611 when(toMSHR.map(_.valid).reduce(_||_)){ 612 missSwitchBit := true.B 613 io.prefetchEnable := true.B 614 }.elsewhen(missSwitchBit && s2_fetch_finish){ 615 missSwitchBit := false.B 616 io.prefetchDisable := true.B 617 } 618 619 620 val miss_all_fix = wait_state === wait_finish 621 s2_fetch_finish := ((s2_valid && s2_fixed_hit) || miss_all_fix || hit_0_except_1_latch || except_0_latch || s2_mmio) 622 623 /** update replacement status register: 0 is hit access/ 1 is miss access */ 624 (touch_ways zip touch_sets).zipWithIndex.map{ case((t_w,t_s), i) => 625 t_s(0) := s2_req_vsetIdx(i) 626 t_w(0).valid := s2_valid && s2_port_hit(i) 627 t_w(0).bits := OHToUInt(s2_tag_match_vec(i)) 628 629 t_s(1) := s2_req_vsetIdx(i) 630 t_w(1).valid := s2_valid && !s2_port_hit(i) 631 t_w(1).bits := OHToUInt(s2_waymask(i)) 632 } 633 634 val s2_hit_datas = RegEnable(s1_hit_data, s1_fire) 635 val s2_datas = Wire(Vec(2, UInt(blockBits.W))) 636 637 s2_datas.zipWithIndex.map{case(bank,i) => 638 if(i == 0) bank := Mux(s2_port_hit(i), s2_hit_datas(i),Mux(miss_0_s2_0_latch,reservedRefillData(0), Mux(miss_1_s2_0_latch,reservedRefillData(1), missSlot(0).m_data))) 639 else bank := Mux(s2_port_hit(i), s2_hit_datas(i),Mux(miss_0_s2_1_latch,reservedRefillData(0), Mux(miss_1_s2_1_latch,reservedRefillData(1), missSlot(1).m_data))) 640 } 641 642 /** response to IFU */ 643 644 (0 until PortNumber).map{ i => 645 if(i ==0) toIFU(i).valid := s2_fire 646 else toIFU(i).valid := s2_fire && s2_double_line 647 toIFU(i).bits.readData := s2_datas(i) 648 toIFU(i).bits.paddr := s2_req_paddr(i) 649 toIFU(i).bits.vaddr := s2_req_vaddr(i) 650 toIFU(i).bits.tlbExcp.pageFault := s2_except_pf(i) 651 toIFU(i).bits.tlbExcp.accessFault := s2_except_af(i) || missSlot(i).m_corrupt 652 toIFU(i).bits.tlbExcp.mmio := s2_mmio 653 654 when(RegNext(s2_fire && missSlot(i).m_corrupt)){ 655 io.errors(i).valid := true.B 656 io.errors(i).report_to_beu := false.B // l2 should have report that to bus error unit, no need to do it again 657 io.errors(i).paddr := RegNext(s2_req_paddr(i)) 658 io.errors(i).source.tag := false.B 659 io.errors(i).source.data := false.B 660 io.errors(i).source.l2 := true.B 661 } 662 } 663 664 io.perfInfo.only_0_hit := only_0_hit_latch 665 io.perfInfo.only_0_miss := only_0_miss_latch 666 io.perfInfo.hit_0_hit_1 := hit_0_hit_1_latch 667 io.perfInfo.hit_0_miss_1 := hit_0_miss_1_latch 668 io.perfInfo.miss_0_hit_1 := miss_0_hit_1_latch 669 io.perfInfo.miss_0_miss_1 := miss_0_miss_1_latch 670 io.perfInfo.hit_0_except_1 := hit_0_except_1_latch 671 io.perfInfo.miss_0_except_1 := miss_0_except_1_latch 672 io.perfInfo.except_0 := except_0_latch 673 io.perfInfo.bank_hit(0) := only_0_miss_latch || hit_0_hit_1_latch || hit_0_miss_1_latch || hit_0_except_1_latch 674 io.perfInfo.bank_hit(1) := miss_0_hit_1_latch || hit_0_hit_1_latch 675 io.perfInfo.hit := hit_0_hit_1_latch || only_0_hit_latch || hit_0_except_1_latch || except_0_latch 676 677 /** <PERF> fetch bubble generated by icache miss*/ 678 679 XSPerfAccumulate("icache_bubble_s2_miss", s2_valid && !s2_fetch_finish ) 680 681} 682