1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend.icache 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.tilelink.ClientStates 23import xiangshan._ 24import xiangshan.cache.mmu._ 25import utils._ 26import xiangshan.backend.fu.{PMPReqBundle, PMPRespBundle} 27 28class ICacheMainPipeReq(implicit p: Parameters) extends ICacheBundle 29{ 30 val vaddr = UInt(VAddrBits.W) 31 def vsetIdx = get_idx(vaddr) 32} 33 34class ICacheMainPipeResp(implicit p: Parameters) extends ICacheBundle 35{ 36 val vaddr = UInt(VAddrBits.W) 37 val readData = UInt(blockBits.W) 38 val paddr = UInt(PAddrBits.W) 39 val tlbExcp = new Bundle{ 40 val pageFault = Bool() 41 val accessFault = Bool() 42 val mmio = Bool() 43 } 44} 45 46class ICacheMainPipeBundle(implicit p: Parameters) extends ICacheBundle 47{ 48 val req = Flipped(DecoupledIO(new ICacheMainPipeReq)) 49 val resp = ValidIO(new ICacheMainPipeResp) 50} 51 52class ICacheMetaReqBundle(implicit p: Parameters) extends ICacheBundle{ 53 val toIMeta = Decoupled(new ICacheReadBundle) 54 val fromIMeta = Input(new ICacheMetaRespBundle) 55} 56 57class ICacheDataReqBundle(implicit p: Parameters) extends ICacheBundle{ 58 val toIData = Decoupled(new ICacheReadBundle) 59 val fromIData = Input(new ICacheDataRespBundle) 60} 61 62class ICacheMSHRBundle(implicit p: Parameters) extends ICacheBundle{ 63 val toMSHR = Decoupled(new ICacheMissReq) 64 val fromMSHR = Flipped(ValidIO(new ICacheMissResp)) 65} 66 67class ICachePMPBundle(implicit p: Parameters) extends ICacheBundle{ 68 val req = Valid(new PMPReqBundle()) 69 val resp = Input(new PMPRespBundle()) 70} 71 72class ICachePerfInfo(implicit p: Parameters) extends ICacheBundle{ 73 val only_0_hit = Bool() 74 val only_0_miss = Bool() 75 val hit_0_hit_1 = Bool() 76 val hit_0_miss_1 = Bool() 77 val miss_0_hit_1 = Bool() 78 val miss_0_miss_1 = Bool() 79 val bank_hit = Vec(2,Bool()) 80 val hit = Bool() 81} 82 83class ICacheMainPipeInterface(implicit p: Parameters) extends ICacheBundle { 84 /*** internal interface ***/ 85 val metaArray = new ICacheMetaReqBundle 86 val dataArray = new ICacheDataReqBundle 87 val mshr = Vec(PortNumber, new ICacheMSHRBundle) 88 val errors = Output(Vec(PortNumber, new L1CacheErrorInfo)) 89 /*** outside interface ***/ 90 val fetch = Vec(PortNumber, new ICacheMainPipeBundle) 91 val pmp = Vec(PortNumber, new ICachePMPBundle) 92 val itlb = Vec(PortNumber, new BlockTlbRequestIO) 93 val respStall = Input(Bool()) 94 val perfInfo = Output(new ICachePerfInfo) 95 96} 97 98class ICacheMainPipe(implicit p: Parameters) extends ICacheModule 99{ 100 val io = IO(new ICacheMainPipeInterface) 101 102 /** Input/Output port */ 103 val (fromIFU, toIFU) = (io.fetch.map(_.req), io.fetch.map(_.resp)) 104 val (toMeta, metaResp) = (io.metaArray.toIMeta, io.metaArray.fromIMeta) 105 val (toData, dataResp) = (io.dataArray.toIData, io.dataArray.fromIData) 106 val (toMSHR, fromMSHR) = (io.mshr.map(_.toMSHR), io.mshr.map(_.fromMSHR)) 107 val (toITLB, fromITLB) = (io.itlb.map(_.req), io.itlb.map(_.resp)) 108 val (toPMP, fromPMP) = (io.pmp.map(_.req), io.pmp.map(_.resp)) 109 110 /** pipeline control signal */ 111 val s0_ready, s1_ready, s2_ready = WireInit(false.B) 112 val s0_fire, s1_fire , s2_fire = WireInit(false.B) 113 114 val missSwitchBit = RegInit(false.B) 115 116 /** replacement status register */ 117 val touch_sets = Seq.fill(2)(Wire(Vec(2, UInt(log2Ceil(nSets/2).W)))) 118 val touch_ways = Seq.fill(2)(Wire(Vec(2, Valid(UInt(log2Ceil(nWays).W)))) ) 119 120 /** 121 ****************************************************************************** 122 * ICache Stage 0 123 * - send req to ITLB and wait for tlb miss fixing 124 * - send req to Meta/Data SRAM 125 ****************************************************************************** 126 */ 127 128 /** s0 control */ 129 val s0_valid = fromIFU.map(_.valid).reduce(_||_) 130 val s0_req_vaddr = VecInit(fromIFU.map(_.bits.vaddr)) 131 val s0_req_vsetIdx = VecInit(fromIFU.map(_.bits.vsetIdx)) 132 val s0_only_fisrt = fromIFU(0).valid && !fromIFU(0).valid 133 val s0_double_line = fromIFU(0).valid && fromIFU(1).valid 134 135 /** SRAM request */ 136 val fetch_req = List(toMeta, toData) 137 for(i <- 0 until 2) { 138 fetch_req(i).valid := s0_valid && !missSwitchBit 139 fetch_req(i).bits.isDoubleLine := s0_double_line 140 fetch_req(i).bits.vSetIdx := s0_req_vsetIdx 141 } 142 143 toITLB(0).valid := s0_valid && !missSwitchBit 144 145 toITLB(0).bits.size := 3.U // TODO: fix the size 146 toITLB(0).bits.vaddr := s0_req_vaddr(0) 147 toITLB(0).bits.debug.pc := s0_req_vaddr(0) 148 149 toITLB(1).valid := s0_valid && s0_double_line && !missSwitchBit 150 toITLB(1).bits.size := 3.U // TODO: fix the size 151 toITLB(1).bits.vaddr := s0_req_vaddr(1) 152 toITLB(1).bits.debug.pc := s0_req_vaddr(1) 153 154 toITLB.map{port => 155 port.bits.cmd := TlbCmd.exec 156 port.bits.robIdx := DontCare 157 port.bits.debug.isFirstIssue := DontCare 158 } 159 160 /** ITLB miss wait logic */ 161 val t_idle :: t_miss :: t_fixed :: Nil = Enum(3) 162 val tlb_status = RegInit(VecInit(Seq.fill(PortNumber)(t_idle))) 163 dontTouch(tlb_status) 164 165 val tlb_miss_vec = VecInit((0 until PortNumber).map( i => toITLB(i).valid && fromITLB(i).bits.miss )) 166 val tlb_resp = Wire(Vec(2, Bool())) 167 tlb_resp(0) := !fromITLB(0).bits.miss 168 tlb_resp(1) := !fromITLB(1).bits.miss || !s0_double_line 169 val tlb_all_resp = tlb_resp.reduce(_&&_) 170 171 (0 until PortNumber).map { i => 172 when(tlb_miss_vec(i)){ 173 tlb_status(i) := t_miss 174 } 175 176 when(tlb_status(i) === t_miss && !fromITLB(i).bits.miss){ 177 tlb_status(i) := t_idle 178 } 179 } 180 181 s0_fire := s0_valid && !missSwitchBit && s1_ready && tlb_all_resp && fetch_req(0).ready && fetch_req(1).ready 182 183 //TODO: fix GTimer() condition 184 fromIFU.map(_.ready := fetch_req(0).ready && fetch_req(1).ready && !missSwitchBit && 185 tlb_all_resp && 186 s1_ready && GTimer() > 500.U ) 187 188 /** 189 ****************************************************************************** 190 * ICache Stage 1 191 * - get tlb resp data (exceptiong info and physical addresses) 192 * - get Meta/Data SRAM read responses (latched for pipeline stop) 193 * - tag compare/hit check 194 ****************************************************************************** 195 */ 196 197 /** s1 control */ 198 val tlbRespAllValid = WireInit(false.B) 199 200 val s1_valid = generatePipeControl(lastFire = s0_fire, thisFire = s1_fire, thisFlush = false.B, lastFlush = false.B) 201 202 val s1_req_vaddr = RegEnable(next = s0_req_vaddr, enable = s0_fire) 203 val s1_req_vsetIdx = RegEnable(next = s0_req_vsetIdx, enable = s0_fire) 204 val s1_only_fisrt = RegEnable(next = s0_only_fisrt, enable = s0_fire) 205 val s1_double_line = RegEnable(next = s0_double_line, enable = s0_fire) 206 207 s1_ready := s2_ready && tlbRespAllValid || !s1_valid 208 s1_fire := s1_valid && tlbRespAllValid && s2_ready 209 210 fromITLB.map(_.ready := true.B) 211 212 /** tlb response latch for pipeline stop */ 213 val s1_tlb_all_resp_wire = RegNext(s0_fire) 214 val s1_tlb_all_resp_reg = RegInit(false.B) 215 216 when(s1_valid && s1_tlb_all_resp_wire && !s2_ready) {s1_tlb_all_resp_reg := true.B} 217 .elsewhen(s1_fire && s1_tlb_all_resp_reg) {s1_tlb_all_resp_reg := false.B} 218 219 tlbRespAllValid := s1_tlb_all_resp_wire || s1_tlb_all_resp_reg 220 221 val tlbRespPAddr = ResultHoldBypass(valid = s1_tlb_all_resp_wire, data = VecInit(fromITLB.map(_.bits.paddr))) 222 val tlbExcpPF = ResultHoldBypass(valid = s1_tlb_all_resp_wire, data = VecInit(fromITLB.map(port => port.bits.excp.pf.instr && port.valid))) 223 val tlbExcpAF = ResultHoldBypass(valid = s1_tlb_all_resp_wire, data = VecInit(fromITLB.map(port => port.bits.excp.af.instr && port.valid))) 224 225 /** s1 hit check/tag compare */ 226 val s1_req_paddr = tlbRespPAddr 227 val s1_req_ptags = VecInit(s1_req_paddr.map(get_phy_tag(_))) 228 229 val s1_meta_ptags = ResultHoldBypass(data = metaResp.tags, valid = RegNext(s0_fire)) 230 val s1_meta_cohs = ResultHoldBypass(data = metaResp.cohs, valid = RegNext(s0_fire)) 231 val s1_meta_errors = ResultHoldBypass(data = metaResp.errors, valid = RegNext(s0_fire)) 232 233 val s1_data_cacheline = ResultHoldBypass(data = dataResp.datas, valid = RegNext(s0_fire)) 234 val s1_data_errors = ResultHoldBypass(data = dataResp.errors, valid = RegNext(s0_fire)) 235 236 val s1_parity_meta_error = VecInit((0 until PortNumber).map(i => s1_meta_errors(i).reduce(_||_))) 237 val s1_parity_data_error = VecInit((0 until PortNumber).map(i => s1_data_errors(i).reduce(_||_))) 238 val s1_parity_error = VecInit((0 until PortNumber).map(i => s1_parity_meta_error(i) || s1_parity_data_error(i))) 239 240 val s1_tag_eq_vec = VecInit((0 until PortNumber).map( p => VecInit((0 until nWays).map( w => s1_meta_ptags(p)(w) === s1_req_ptags(p) )))) 241 val s1_tag_match_vec = VecInit((0 until PortNumber).map( k => VecInit(s1_tag_eq_vec(k).zipWithIndex.map{ case(way_tag_eq, w) => way_tag_eq && s1_meta_cohs(k)(w).isValid()}))) 242 val s1_tag_match = VecInit(s1_tag_match_vec.map(vector => ParallelOR(vector))) 243 244 val s1_port_hit = VecInit(Seq(s1_tag_match(0) && s1_valid && !tlbExcpPF(0) && !tlbExcpAF(0), s1_tag_match(1) && s1_valid && s1_double_line && !tlbExcpPF(1) && !tlbExcpAF(1) )) 245 val s1_bank_miss = VecInit(Seq(!s1_tag_match(0) && s1_valid && !tlbExcpPF(0) && !tlbExcpAF(0), !s1_tag_match(1) && s1_valid && s1_double_line && !tlbExcpPF(1) && !tlbExcpAF(1) )) 246 val s1_hit = (s1_port_hit(0) && s1_port_hit(1)) || (!s1_double_line && s1_port_hit(0)) 247 248 /** choose victim cacheline */ 249 val replacers = Seq.fill(PortNumber)(ReplacementPolicy.fromString(cacheParams.replacer,nWays,nSets/PortNumber)) 250 val s1_victim_oh = ResultHoldBypass(data = VecInit(replacers.zipWithIndex.map{case (replacer, i) => UIntToOH(replacer.way(s1_req_vsetIdx(i)))}), valid = RegNext(s0_fire)) 251 252 val s1_victim_coh = VecInit(s1_victim_oh.zipWithIndex.map {case(oh, port) => Mux1H(oh, s1_meta_cohs(port))}) 253 254 assert(PopCount(s1_tag_match_vec(0)) <= 1.U && PopCount(s1_tag_match_vec(1)) <= 1.U, "Multiple hit in main pipe") 255 256 for(i <- 0 until PortNumber){ 257 io.errors(i).valid := RegNext(s1_parity_error(i) && RegNext(s0_fire)) 258 io.errors(i).ecc_error.valid := RegNext(s1_parity_error(i) && RegNext(s0_fire)) 259 io.errors(i).ecc_error.bits := RegNext(tlbRespPAddr(i)) 260 io.errors(i).source := DontCare 261 io.errors(i).source.tag := RegNext(s1_parity_meta_error(i)) 262 io.errors(i).source.data := RegNext(s1_parity_data_error(i)) 263 io.errors(i).source.l2 := false.B 264 io.errors(i).opType := DontCare 265 io.errors(i).opType.fetch := true.B 266 } 267 268 ((replacers zip touch_sets) zip touch_ways).map{case ((r, s),w) => r.access(s,w)} 269 270 val s1_hit_data = VecInit(s1_data_cacheline.zipWithIndex.map { case(bank, i) => 271 val port_hit_data = Mux1H(s1_tag_match_vec(i).asUInt, bank) 272 port_hit_data 273 }) 274 275 /** <PERF> replace victim way number */ 276 277 (0 until nWays).map{ w => 278 XSPerfAccumulate("line_0_hit_way_" + Integer.toString(w, 10), s1_fire && s1_port_hit(0) && OHToUInt(s1_tag_match_vec(0)) === w.U) 279 } 280 281 (0 until nWays).map{ w => 282 XSPerfAccumulate("line_0_victim_way_" + Integer.toString(w, 10), s1_fire && !s1_port_hit(0) && OHToUInt(s1_victim_oh(0)) === w.U) 283 } 284 285 (0 until nWays).map{ w => 286 XSPerfAccumulate("line_1_hit_way_" + Integer.toString(w, 10), s1_fire && s1_double_line && s1_port_hit(1) && OHToUInt(s1_tag_match_vec(1)) === w.U) 287 } 288 289 (0 until nWays).map{ w => 290 XSPerfAccumulate("line_1_victim_way_" + Integer.toString(w, 10), s1_fire && s1_double_line && !s1_port_hit(1) && OHToUInt(s1_victim_oh(1)) === w.U) 291 } 292 293 XSPerfAccumulate("ifu_bubble_s1_tlb_miss", s1_valid && !tlbRespAllValid ) 294 295 /** 296 ****************************************************************************** 297 * ICache Stage 2 298 * - send request to MSHR if ICache miss 299 * - generate secondary miss status/data registers 300 * - response to IFU 301 ****************************************************************************** 302 */ 303 304 /** s2 control */ 305 val s2_fetch_finish = Wire(Bool()) 306 307 val s2_valid = generatePipeControl(lastFire = s1_fire, thisFire = s2_fire, thisFlush = false.B, lastFlush = false.B) 308 val s2_miss_available = Wire(Bool()) 309 310 s2_ready := (s2_valid && s2_fetch_finish && !io.respStall) || (!s2_valid && s2_miss_available) 311 s2_fire := s2_valid && s2_fetch_finish && !io.respStall 312 313 /** s2 data */ 314 val mmio = fromPMP.map(port => port.mmio) // TODO: handle it 315 316 val (s2_req_paddr , s2_req_vaddr) = (RegEnable(next = s1_req_paddr, enable = s1_fire), RegEnable(next = s1_req_vaddr, enable = s1_fire)) 317 val s2_req_vsetIdx = RegEnable(next = s1_req_vsetIdx, enable = s1_fire) 318 val s2_req_ptags = RegEnable(next = s1_req_ptags, enable = s1_fire) 319 val s2_only_fisrt = RegEnable(next = s1_only_fisrt, enable = s1_fire) 320 val s2_double_line = RegEnable(next = s1_double_line, enable = s1_fire) 321 val s2_hit = RegEnable(next = s1_hit , enable = s1_fire) 322 val s2_port_hit = RegEnable(next = s1_port_hit, enable = s1_fire) 323 val s2_bank_miss = RegEnable(next = s1_bank_miss, enable = s1_fire) 324 val s2_waymask = RegEnable(next = s1_victim_oh, enable = s1_fire) 325 val s2_victim_coh = RegEnable(next = s1_victim_coh, enable = s1_fire) 326 327 /** status imply that s2 is a secondary miss (no need to resend miss request) */ 328 val sec_meet_vec = Wire(Vec(2, Bool())) 329 val s2_fixed_hit_vec = VecInit((0 until 2).map(i => s2_port_hit(i) || sec_meet_vec(i))) 330 val s2_fixed_hit = (s2_valid && s2_fixed_hit_vec(0) && s2_fixed_hit_vec(1) && s2_double_line) || (s2_valid && s2_fixed_hit_vec(0) && !s2_double_line) 331 332 /** exception and pmp logic **/ 333 //PMP Result 334 val pmpExcpAF = Wire(Vec(PortNumber, Bool())) 335 pmpExcpAF(0) := fromPMP(0).instr 336 pmpExcpAF(1) := fromPMP(1).instr && s2_double_line 337 //exception information 338 val s2_except_pf = RegEnable(next =tlbExcpPF, enable = s1_fire) 339 val s2_except_af = VecInit(RegEnable(next = tlbExcpAF, enable = s1_fire).zip(RegEnable(next = s1_parity_error, enable = s1_fire)).zip(pmpExcpAF).map{ 340 case((tlbAf, parityError), pmpAf) => tlbAf || parityError || DataHoldBypass(pmpAf, RegNext(s1_fire)).asBool}) 341 val s2_except = VecInit((0 until 2).map{i => s2_except_pf(i) || s2_except_af(i)}) 342 val s2_has_except = s2_valid && (s2_except_af.reduce(_||_) || s2_except_pf.reduce(_||_)) 343 //MMIO 344 val s2_mmio = DataHoldBypass(io.pmp(0).resp.mmio && !s2_except_af(0) && !s2_except_pf(0), RegNext(s1_fire)).asBool() 345 346 //send physical address to PMP 347 io.pmp.zipWithIndex.map { case (p, i) => 348 p.req.valid := s2_valid && !missSwitchBit 349 p.req.bits.addr := s2_req_paddr(i) 350 p.req.bits.size := 3.U // TODO 351 p.req.bits.cmd := TlbCmd.exec 352 } 353 354 /*** cacheline miss logic ***/ 355 val wait_idle :: wait_queue_ready :: wait_send_req :: wait_two_resp :: wait_0_resp :: wait_1_resp :: wait_one_resp ::wait_finish :: Nil = Enum(8) 356 val wait_state = RegInit(wait_idle) 357 358 val port_miss_fix = VecInit(Seq(fromMSHR(0).fire() && !s2_port_hit(0), fromMSHR(1).fire() && s2_double_line && !s2_port_hit(1) )) 359 360 // secondary miss record registers 361 class MissSlot(implicit p: Parameters) extends ICacheBundle { 362 val m_vSetIdx = UInt(idxBits.W) 363 val m_pTag = UInt(tagBits.W) 364 val m_data = UInt(blockBits.W) 365 val m_corrupt = Bool() 366 } 367 368 val missSlot = Seq.fill(2)(RegInit(0.U.asTypeOf(new MissSlot))) 369 val m_invalid :: m_valid :: m_refilled :: m_flushed :: m_wait_sec_miss :: m_check_final ::Nil = Enum(6) 370 val missStateQueue = RegInit(VecInit(Seq.fill(2)(m_invalid)) ) 371 val reservedRefillData = Wire(Vec(2, UInt(blockBits.W))) 372 373 s2_miss_available := VecInit(missStateQueue.map(entry => entry === m_invalid || entry === m_wait_sec_miss)).reduce(_&&_) 374 375 val fix_sec_miss = Wire(Vec(4, Bool())) 376 val sec_meet_0_miss = fix_sec_miss(0) || fix_sec_miss(2) 377 val sec_meet_1_miss = fix_sec_miss(1) || fix_sec_miss(3) 378 sec_meet_vec := VecInit(Seq(sec_meet_0_miss,sec_meet_1_miss )) 379 380 /*** miss/hit pattern: <Control Signal> only raise at the first cycle of s2_valid ***/ 381 val cacheline_0_hit = (s2_port_hit(0) || sec_meet_0_miss) 382 val cacheline_0_miss = !s2_port_hit(0) && !sec_meet_0_miss 383 384 val cacheline_1_hit = (s2_port_hit(1) || sec_meet_1_miss) 385 val cacheline_1_miss = !s2_port_hit(1) && !sec_meet_1_miss 386 387 val only_0_miss = RegNext(s1_fire) && cacheline_0_miss && !s2_double_line && !s2_has_except && !s2_mmio 388 val only_0_hit = RegNext(s1_fire) && cacheline_0_hit && !s2_double_line && !s2_mmio 389 val hit_0_hit_1 = RegNext(s1_fire) && cacheline_0_hit && cacheline_1_hit && s2_double_line && !s2_mmio 390 val hit_0_miss_1 = RegNext(s1_fire) && cacheline_0_hit && cacheline_1_miss && s2_double_line && !s2_has_except && !s2_mmio 391 val miss_0_hit_1 = RegNext(s1_fire) && cacheline_0_miss && cacheline_1_hit && s2_double_line && !s2_has_except && !s2_mmio 392 val miss_0_miss_1 = RegNext(s1_fire) && cacheline_0_miss && cacheline_1_miss && s2_double_line && !s2_has_except && !s2_mmio 393 394 val hit_0_except_1 = RegNext(s1_fire) && s2_double_line && !s2_except(0) && s2_except(1) && cacheline_0_hit 395 val miss_0_except_1 = RegNext(s1_fire) && s2_double_line && !s2_except(0) && s2_except(1) && cacheline_0_miss 396 val except_0 = RegNext(s1_fire) && s2_except(0) 397 398 def holdReleaseLatch(valid: Bool, release: Bool, flush: Bool): Bool ={ 399 val bit = RegInit(false.B) 400 when(flush) { bit := false.B } 401 .elsewhen(valid && !release) { bit := true.B } 402 .elsewhen(release) { bit := false.B} 403 bit || valid 404 } 405 406 /*** miss/hit pattern latch: <Control Signal> latch the miss/hit patter if pipeline stop ***/ 407 val miss_0_hit_1_latch = holdReleaseLatch(valid = miss_0_hit_1, release = s2_fire, flush = false.B) 408 val miss_0_miss_1_latch = holdReleaseLatch(valid = miss_0_miss_1, release = s2_fire, flush = false.B) 409 val only_0_miss_latch = holdReleaseLatch(valid = only_0_miss, release = s2_fire, flush = false.B) 410 val hit_0_miss_1_latch = holdReleaseLatch(valid = hit_0_miss_1, release = s2_fire, flush = false.B) 411 412 val miss_0_except_1_latch = holdReleaseLatch(valid = miss_0_except_1, release = s2_fire, flush = false.B) 413 val except_0_latch = holdReleaseLatch(valid = except_0, release = s2_fire, flush = false.B) 414 val hit_0_except_1_latch = holdReleaseLatch(valid = hit_0_except_1, release = s2_fire, flush = false.B) 415 416 val only_0_hit_latch = holdReleaseLatch(valid = only_0_hit, release = s2_fire, flush = false.B) 417 val hit_0_hit_1_latch = holdReleaseLatch(valid = hit_0_hit_1, release = s2_fire, flush = false.B) 418 419 420 /*** secondary miss judegment ***/ 421 422 def waitSecondComeIn(missState: UInt): Bool = (missState === m_wait_sec_miss) 423 424 def getMissSituat(slotNum : Int, missNum : Int ) :Bool = { 425 RegNext(s1_fire) && (missSlot(slotNum).m_vSetIdx === s2_req_vsetIdx(missNum)) && (missSlot(slotNum).m_pTag === s2_req_ptags(missNum)) && !s2_port_hit(missNum) && waitSecondComeIn(missStateQueue(slotNum)) && !s2_mmio 426 } 427 428 val miss_0_s2_0 = getMissSituat(slotNum = 0, missNum = 0) 429 val miss_0_s2_1 = getMissSituat(slotNum = 0, missNum = 1) 430 val miss_1_s2_0 = getMissSituat(slotNum = 1, missNum = 0) 431 val miss_1_s2_1 = getMissSituat(slotNum = 1, missNum = 1) 432 433 val miss_0_s2_0_latch = holdReleaseLatch(valid = miss_0_s2_0, release = s2_fire, flush = false.B) 434 val miss_0_s2_1_latch = holdReleaseLatch(valid = miss_0_s2_1, release = s2_fire, flush = false.B) 435 val miss_1_s2_0_latch = holdReleaseLatch(valid = miss_1_s2_0, release = s2_fire, flush = false.B) 436 val miss_1_s2_1_latch = holdReleaseLatch(valid = miss_1_s2_1, release = s2_fire, flush = false.B) 437 438 439 val slot_0_solve = fix_sec_miss(0) || fix_sec_miss(1) 440 val slot_1_solve = fix_sec_miss(2) || fix_sec_miss(3) 441 val slot_slove = VecInit(Seq(slot_0_solve, slot_1_solve)) 442 443 fix_sec_miss := VecInit(Seq(miss_0_s2_0_latch, miss_0_s2_1_latch, miss_1_s2_0_latch, miss_1_s2_1_latch)) 444 445 /*** reserved data for secondary miss ***/ 446 447 reservedRefillData(0) := DataHoldBypass(data = missSlot(0).m_data, valid = miss_0_s2_0 || miss_0_s2_1) 448 reservedRefillData(1) := DataHoldBypass(data = missSlot(1).m_data, valid = miss_1_s2_0 || miss_1_s2_1) 449 450 /*** miss state machine ***/ 451 452 switch(wait_state){ 453 is(wait_idle){ 454 when(miss_0_except_1_latch){ 455 wait_state := Mux(toMSHR(0).ready, wait_queue_ready ,wait_idle ) 456 }.elsewhen( only_0_miss_latch || miss_0_hit_1_latch){ 457 wait_state := Mux(toMSHR(0).ready, wait_queue_ready ,wait_idle ) 458 }.elsewhen(hit_0_miss_1_latch){ 459 wait_state := Mux(toMSHR(1).ready, wait_queue_ready ,wait_idle ) 460 }.elsewhen( miss_0_miss_1_latch ){ 461 wait_state := Mux(toMSHR(0).ready && toMSHR(1).ready, wait_queue_ready ,wait_idle) 462 } 463 } 464 465 is(wait_queue_ready){ 466 wait_state := wait_send_req 467 } 468 469 is(wait_send_req) { 470 when(miss_0_except_1_latch || only_0_miss_latch || hit_0_miss_1_latch || miss_0_hit_1_latch){ 471 wait_state := wait_one_resp 472 }.elsewhen( miss_0_miss_1_latch ){ 473 wait_state := wait_two_resp 474 } 475 } 476 477 is(wait_one_resp) { 478 when( (miss_0_except_1_latch ||only_0_miss_latch || miss_0_hit_1_latch) && fromMSHR(0).fire()){ 479 wait_state := wait_finish 480 }.elsewhen( hit_0_miss_1_latch && fromMSHR(1).fire()){ 481 wait_state := wait_finish 482 } 483 } 484 485 is(wait_two_resp) { 486 when(fromMSHR(0).fire() && fromMSHR(1).fire()){ 487 wait_state := wait_finish 488 }.elsewhen( !fromMSHR(0).fire() && fromMSHR(1).fire() ){ 489 wait_state := wait_0_resp 490 }.elsewhen(fromMSHR(0).fire() && !fromMSHR(1).fire()){ 491 wait_state := wait_1_resp 492 } 493 } 494 495 is(wait_0_resp) { 496 when(fromMSHR(0).fire()){ 497 wait_state := wait_finish 498 } 499 } 500 501 is(wait_1_resp) { 502 when(fromMSHR(1).fire()){ 503 wait_state := wait_finish 504 } 505 } 506 507 is(wait_finish) {when(s2_fire) {wait_state := wait_idle } 508 } 509 } 510 511 512 /*** send request to MissUnit ***/ 513 514 (0 until 2).map { i => 515 if(i == 1) toMSHR(i).valid := (hit_0_miss_1_latch || miss_0_miss_1_latch) && wait_state === wait_queue_ready && !s2_mmio 516 else toMSHR(i).valid := (only_0_miss_latch || miss_0_hit_1_latch || miss_0_miss_1_latch || miss_0_except_1_latch) && wait_state === wait_queue_ready && !s2_mmio 517 toMSHR(i).bits.paddr := s2_req_paddr(i) 518 toMSHR(i).bits.vaddr := s2_req_vaddr(i) 519 toMSHR(i).bits.waymask := s2_waymask(i) 520 toMSHR(i).bits.coh := s2_victim_coh(i) 521 522 523 when(toMSHR(i).fire() && missStateQueue(i) === m_invalid){ 524 missStateQueue(i) := m_valid 525 missSlot(i).m_vSetIdx := s2_req_vsetIdx(i) 526 missSlot(i).m_pTag := get_phy_tag(s2_req_paddr(i)) 527 } 528 529 when(fromMSHR(i).fire() && missStateQueue(i) === m_valid ){ 530 missStateQueue(i) := m_refilled 531 missSlot(i).m_data := fromMSHR(i).bits.data 532 missSlot(i).m_corrupt := fromMSHR(i).bits.corrupt 533 } 534 535 536 when(s2_fire && missStateQueue(i) === m_refilled){ 537 missStateQueue(i) := m_wait_sec_miss 538 } 539 540 /*** Only the first cycle to check whether meet the secondary miss ***/ 541 when(missStateQueue(i) === m_wait_sec_miss){ 542 /*** The seondary req has been fix by this slot and another also hit || the secondary req for other cacheline and hit ***/ 543 when((slot_slove(i) && s2_fire) || (!slot_slove(i) && s2_fire) ) { 544 missStateQueue(i) := m_invalid 545 } 546 /*** The seondary req has been fix by this slot but another miss/f3 not ready || the seondary req for other cacheline and miss ***/ 547 .elsewhen((slot_slove(i) && !s2_fire && s2_valid) || (s2_valid && !slot_slove(i) && !s2_fire) ){ 548 missStateQueue(i) := m_check_final 549 } 550 } 551 552 when(missStateQueue(i) === m_check_final && toMSHR(i).fire()){ 553 missStateQueue(i) := m_valid 554 missSlot(i).m_vSetIdx := s2_req_vsetIdx(i) 555 missSlot(i).m_pTag := get_phy_tag(s2_req_paddr(i)) 556 }.elsewhen(missStateQueue(i) === m_check_final) { 557 missStateQueue(i) := m_invalid 558 } 559 } 560 561 when(toMSHR.map(_.valid).reduce(_||_)){ 562 missSwitchBit := true.B 563 }.elsewhen(missSwitchBit && s2_fetch_finish){ 564 missSwitchBit := false.B 565 } 566 567 val miss_all_fix = wait_state === wait_finish 568 s2_fetch_finish := ((s2_valid && s2_fixed_hit) || miss_all_fix || hit_0_except_1_latch || except_0_latch || s2_mmio) 569 570 /** update replacement status register: 0 is hit access/ 1 is miss access */ 571 (touch_ways zip touch_sets).zipWithIndex.map{ case((t_w,t_s), i) => 572 t_s(0) := s1_req_vsetIdx(i) 573 t_w(0).valid := s1_port_hit(i) 574 t_w(0).bits := OHToUInt(s1_tag_match_vec(i)) 575 576 t_s(1) := s2_req_vsetIdx(i) 577 t_w(1).valid := s2_valid && !s2_port_hit(i) 578 t_w(1).bits := OHToUInt(s2_waymask(i)) 579 } 580 581 val s2_hit_datas = RegEnable(next = s1_hit_data, enable = s1_fire) 582 val s2_datas = Wire(Vec(2, UInt(blockBits.W))) 583 584 s2_datas.zipWithIndex.map{case(bank,i) => 585 if(i == 0) bank := Mux(s2_port_hit(i), s2_hit_datas(i),Mux(miss_0_s2_0_latch,reservedRefillData(0), Mux(miss_1_s2_0_latch,reservedRefillData(1), missSlot(0).m_data))) 586 else bank := Mux(s2_port_hit(i), s2_hit_datas(i),Mux(miss_0_s2_1_latch,reservedRefillData(0), Mux(miss_1_s2_1_latch,reservedRefillData(1), missSlot(1).m_data))) 587 } 588 589 /** response to IFU */ 590 591 (0 until PortNumber).map{ i => 592 if(i ==0) toIFU(i).valid := s2_fire 593 else toIFU(i).valid := s2_fire && s2_double_line 594 toIFU(i).bits.readData := s2_datas(i) 595 toIFU(i).bits.paddr := s2_req_paddr(i) 596 toIFU(i).bits.vaddr := s2_req_vaddr(i) 597 toIFU(i).bits.tlbExcp.pageFault := s2_except_pf(i) 598 toIFU(i).bits.tlbExcp.accessFault := s2_except_af(i) || missSlot(i).m_corrupt 599 toIFU(i).bits.tlbExcp.mmio := s2_mmio 600 601 when(RegNext(s2_fire && missSlot(i).m_corrupt)){ 602 io.errors(i).valid := true.B 603 io.errors(i).ecc_error.valid := false.B // l2 should have report that to bus error unit, no need to do it again 604 io.errors(i).ecc_error.bits := RegNext(s2_req_paddr(i)) 605 io.errors(i).source.tag := false.B 606 io.errors(i).source.data := false.B 607 io.errors(i).source.l2 := true.B 608 } 609 } 610 611 io.perfInfo.only_0_hit := only_0_miss_latch 612 io.perfInfo.only_0_miss := only_0_miss_latch 613 io.perfInfo.hit_0_hit_1 := hit_0_hit_1_latch 614 io.perfInfo.hit_0_miss_1 := hit_0_miss_1_latch 615 io.perfInfo.miss_0_hit_1 := miss_0_hit_1_latch 616 io.perfInfo.miss_0_miss_1 := miss_0_miss_1_latch 617 io.perfInfo.bank_hit(0) := only_0_miss_latch || hit_0_hit_1_latch || hit_0_miss_1_latch || hit_0_except_1_latch 618 io.perfInfo.bank_hit(1) := miss_0_hit_1_latch || hit_0_hit_1_latch 619 io.perfInfo.hit := hit_0_hit_1_latch 620 621 /** <PERF> fetch bubble generated by icache miss*/ 622 623 XSPerfAccumulate("ifu_bubble_s2_miss", s2_valid && !s2_fetch_finish ) 624 625} 626