1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend.icache 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import difftest.DifftestRefillEvent 23import freechips.rocketchip.tilelink.ClientStates 24import xiangshan._ 25import xiangshan.cache.mmu._ 26import utils._ 27import utility._ 28import xiangshan.backend.fu.{PMPReqBundle, PMPRespBundle} 29import xiangshan.frontend.{FtqICacheInfo, FtqToICacheRequestBundle} 30 31class ICacheMainPipeReq(implicit p: Parameters) extends ICacheBundle 32{ 33 val vaddr = UInt(VAddrBits.W) 34 def vsetIdx = get_idx(vaddr) 35} 36 37class ICacheMainPipeResp(implicit p: Parameters) extends ICacheBundle 38{ 39 val vaddr = UInt(VAddrBits.W) 40 val registerData = UInt(blockBits.W) 41 val sramData = UInt(blockBits.W) 42 val select = Bool() 43 val paddr = UInt(PAddrBits.W) 44 val tlbExcp = new Bundle{ 45 val pageFault = Bool() 46 val accessFault = Bool() 47 val mmio = Bool() 48 } 49} 50 51class ICacheMainPipeBundle(implicit p: Parameters) extends ICacheBundle 52{ 53 val req = Flipped(Decoupled(new FtqToICacheRequestBundle)) 54 val resp = Vec(PortNumber, ValidIO(new ICacheMainPipeResp)) 55 val topdownIcacheMiss = Output(Bool()) 56 val topdownItlbMiss = Output(Bool()) 57} 58 59class ICacheMetaReqBundle(implicit p: Parameters) extends ICacheBundle{ 60 val toIMeta = DecoupledIO(new ICacheReadBundle) 61 val fromIMeta = Input(new ICacheMetaRespBundle) 62} 63 64class ICacheDataReqBundle(implicit p: Parameters) extends ICacheBundle{ 65 val toIData = DecoupledIO(Vec(partWayNum, new ICacheReadBundle)) 66 val fromIData = Input(new ICacheDataRespBundle) 67} 68 69class ICacheMSHRBundle(implicit p: Parameters) extends ICacheBundle{ 70 val toMSHR = Decoupled(new ICacheMissReq) 71 val fromMSHR = Flipped(ValidIO(new ICacheMissResp)) 72} 73 74class ICachePMPBundle(implicit p: Parameters) extends ICacheBundle{ 75 val req = Valid(new PMPReqBundle()) 76 val resp = Input(new PMPRespBundle()) 77} 78 79class ICachePerfInfo(implicit p: Parameters) extends ICacheBundle{ 80 val only_0_hit = Bool() 81 val only_0_miss = Bool() 82 val hit_0_hit_1 = Bool() 83 val hit_0_miss_1 = Bool() 84 val miss_0_hit_1 = Bool() 85 val miss_0_miss_1 = Bool() 86 val hit_0_except_1 = Bool() 87 val miss_0_except_1 = Bool() 88 val except_0 = Bool() 89 val bank_hit = Vec(2,Bool()) 90 val hit = Bool() 91} 92 93class ICacheMainPipeInterface(implicit p: Parameters) extends ICacheBundle { 94 val hartId = Input(UInt(8.W)) 95 /*** internal interface ***/ 96 val metaArray = new ICacheMetaReqBundle 97 val dataArray = new ICacheDataReqBundle 98 /** prefetch io */ 99 val iprefetchBuf = Flipped(new IPFBufferRead) 100 val PIQ = Flipped(Vec(nPrefetchEntries,new PIQToMainPipe)) 101 val IPFBufMove = Flipped(new IPFBufferMove) 102 val mainPipeMissInfo = new MainPipeMissInfo() 103 val missSlotInfo = Vec(PortNumber, ValidIO(new MainPipeToPrefetchPipe)) 104 105 val mshr = Vec(PortNumber, new ICacheMSHRBundle) 106 val errors = Output(Vec(PortNumber, new L1CacheErrorInfo)) 107 /*** outside interface ***/ 108 //val fetch = Vec(PortNumber, new ICacheMainPipeBundle) 109 /* when ftq.valid is high in T + 1 cycle 110 * the ftq component must be valid in T cycle 111 */ 112 val fetch = new ICacheMainPipeBundle 113 val pmp = Vec(PortNumber, new ICachePMPBundle) 114 val itlb = Vec(PortNumber, new TlbRequestIO) 115 val respStall = Input(Bool()) 116 val perfInfo = Output(new ICachePerfInfo) 117 118 val prefetchEnable = Output(Bool()) 119 val prefetchDisable = Output(Bool()) 120 val csr_parity_enable = Input(Bool()) 121 122} 123 124class ICacheMainPipe(implicit p: Parameters) extends ICacheModule 125{ 126 val io = IO(new ICacheMainPipeInterface) 127 128 /** Input/Output port */ 129 val (fromFtq, toIFU) = (io.fetch.req, io.fetch.resp) 130 val (toMeta, metaResp) = (io.metaArray.toIMeta, io.metaArray.fromIMeta) 131 val (toData, dataResp) = (io.dataArray.toIData, io.dataArray.fromIData) 132 val (toIPF, fromIPF) = (io.iprefetchBuf.req, io.iprefetchBuf.resp) 133 val (toMSHR, fromMSHR) = (io.mshr.map(_.toMSHR), io.mshr.map(_.fromMSHR)) 134 val (toITLB, fromITLB) = (io.itlb.map(_.req), io.itlb.map(_.resp)) 135 val (toPMP, fromPMP) = (io.pmp.map(_.req), io.pmp.map(_.resp)) 136 val fromPIQ = io.PIQ.map(_.info) 137 val IPFBufferMove = io.IPFBufMove 138 val missSlotInfo = io.missSlotInfo 139 val mainPipeMissInfo = io.mainPipeMissInfo 140 141 io.itlb.foreach(_.req_kill := false.B) 142 143 144 //Ftq RegNext Register 145 val fromFtqReq = fromFtq.bits.pcMemRead 146 147 /** pipeline control signal */ 148 val s1_ready, s2_ready = Wire(Bool()) 149 val s0_fire, s1_fire , s2_fire = Wire(Bool()) 150 151 val missSwitchBit = RegInit(false.B) 152 153 /** replacement status register */ 154 val touch_sets = Seq.fill(2)(Wire(Vec(2, UInt(log2Ceil(nSets/2).W)))) 155 val touch_ways = Seq.fill(2)(Wire(Vec(2, Valid(UInt(log2Ceil(nWays).W)))) ) 156 157 /** 158 ****************************************************************************** 159 * ICache Stage 0 160 * - send req to ITLB and wait for tlb miss fixing 161 * - send req to Meta/Data SRAM 162 ****************************************************************************** 163 */ 164 165 /** s0 control */ 166 val s0_valid = fromFtq.valid 167 val s0_req_vaddr = (0 until partWayNum + 1).map(i => VecInit(Seq(fromFtqReq(i).startAddr, fromFtqReq(i).nextlineStart))) 168 val s0_req_vsetIdx = (0 until partWayNum + 1).map(i => VecInit(s0_req_vaddr(i).map(get_idx(_)))) 169 val s0_only_first = (0 until partWayNum + 1).map(i => fromFtq.bits.readValid(i) && !fromFtqReq(i).crossCacheline) 170 val s0_double_line = (0 until partWayNum + 1).map(i => fromFtq.bits.readValid(i) && fromFtqReq(i).crossCacheline) 171 172 val s0_final_valid = s0_valid 173 val s0_final_vaddr = s0_req_vaddr.head 174 val s0_final_vsetIdx = s0_req_vsetIdx.head 175 val s0_final_only_first = s0_only_first.head 176 val s0_final_double_line = s0_double_line.head 177 178 /** SRAM request */ 179 //0 -> metaread, 1,2,3 -> data, 3 -> code 4 -> itlb 180 // TODO: it seems like 0,1,2,3 -> dataArray(data); 3 -> dataArray(code); 0 -> metaArray; 4 -> itlb 181 val ftq_req_to_data_doubleline = s0_double_line.init 182 val ftq_req_to_data_vset_idx = s0_req_vsetIdx.init 183 val ftq_req_to_data_valid = fromFtq.bits.readValid.init 184 185 val ftq_req_to_meta_doubleline = s0_double_line.head 186 val ftq_req_to_meta_vset_idx = s0_req_vsetIdx.head 187 188 val ftq_req_to_itlb_only_first = s0_only_first.last 189 val ftq_req_to_itlb_doubleline = s0_double_line.last 190 val ftq_req_to_itlb_vaddr = s0_req_vaddr.last 191 val ftq_req_to_itlb_vset_idx = s0_req_vsetIdx.last 192 193 194 for(i <- 0 until partWayNum) { 195 toData.valid := ftq_req_to_data_valid(i) && !missSwitchBit 196 toData.bits(i).isDoubleLine := ftq_req_to_data_doubleline(i) 197 toData.bits(i).vSetIdx := ftq_req_to_data_vset_idx(i) 198 } 199 200 toMeta.valid := s0_valid && !missSwitchBit 201 toMeta.bits.isDoubleLine := ftq_req_to_meta_doubleline 202 toMeta.bits.vSetIdx := ftq_req_to_meta_vset_idx 203 204 205 toITLB(0).valid := s0_valid 206 toITLB(0).bits.size := 3.U // TODO: fix the size 207 toITLB(0).bits.vaddr := ftq_req_to_itlb_vaddr(0) 208 toITLB(0).bits.debug.pc := ftq_req_to_itlb_vaddr(0) 209 210 toITLB(1).valid := s0_valid && ftq_req_to_itlb_doubleline 211 toITLB(1).bits.size := 3.U // TODO: fix the size 212 toITLB(1).bits.vaddr := ftq_req_to_itlb_vaddr(1) 213 toITLB(1).bits.debug.pc := ftq_req_to_itlb_vaddr(1) 214 215 toITLB.map{port => 216 port.bits.cmd := TlbCmd.exec 217 port.bits.memidx := DontCare 218 port.bits.debug.robIdx := DontCare 219 port.bits.no_translate := false.B 220 port.bits.debug.isFirstIssue := DontCare 221 } 222 223 /** ITLB & ICACHE sync case 224 * when icache is not ready, but itlb is ready 225 * because itlb is non-block, then the req will take the port 226 * then itlb will unset the ready?? itlb is wrongly blocked. 227 * Solution: maybe give itlb a signal to tell whether acquire the slot? 228 */ 229 230 val itlb_can_go = toITLB(0).ready && toITLB(1).ready 231 val icache_can_go = toData.ready && toMeta.ready 232 val pipe_can_go = !missSwitchBit && s1_ready 233 val s0_can_go = itlb_can_go && icache_can_go && pipe_can_go 234 val s0_fetch_fire = s0_valid && s0_can_go 235 s0_fire := s0_fetch_fire 236 toITLB.map{port => port.bits.kill := !icache_can_go || !pipe_can_go} 237 238 //TODO: fix GTimer() condition 239 fromFtq.ready := s0_can_go 240 241 /** 242 ****************************************************************************** 243 * ICache Stage 1 244 * - get tlb resp data (exceptiong info and physical addresses) 245 * - get Meta/Data SRAM read responses (latched for pipeline stop) 246 * - tag compare/hit check 247 ****************************************************************************** 248 */ 249 250 /** s1 control */ 251 252 val s1_valid = generatePipeControl(lastFire = s0_fire, thisFire = s1_fire, thisFlush = false.B, lastFlush = false.B) 253 254 val s1_req_vaddr = RegEnable(s0_final_vaddr, s0_fire) 255 val s1_req_vsetIdx = RegEnable(s0_final_vsetIdx, s0_fire) 256 val s1_only_first = RegEnable(s0_final_only_first, s0_fire) 257 val s1_double_line = RegEnable(s0_final_double_line, s0_fire) 258 val s1_wait = Wire(Bool()) 259 260 /** tlb response latch for pipeline stop */ 261 val tlb_back = fromITLB.map(_.fire()) 262 val tlb_need_back = VecInit((0 until PortNumber).map(i => ValidHold(s0_fire && toITLB(i).fire(), s1_fire, false.B))) 263 val tlb_already_recv = RegInit(VecInit(Seq.fill(PortNumber)(false.B))) 264 val tlb_ready_recv = VecInit((0 until PortNumber).map(i => RegNext(s0_fire, false.B) || (s1_valid && !tlb_already_recv(i)))) 265 val tlb_resp_valid = Wire(Vec(2, Bool())) 266 for (i <- 0 until PortNumber) { 267 tlb_resp_valid(i) := tlb_already_recv(i) || (tlb_ready_recv(i) && tlb_back(i)) 268 when (tlb_already_recv(i) && s1_fire) { 269 tlb_already_recv(i) := false.B 270 } 271 when (tlb_back(i) && tlb_ready_recv(i) && !s1_fire) { 272 tlb_already_recv(i) := true.B 273 } 274 fromITLB(i).ready := tlb_ready_recv(i) 275 } 276 assert(RegNext(Cat((0 until PortNumber).map(i => tlb_need_back(i) || !tlb_resp_valid(i))).andR(), true.B), 277 "when tlb should not back, tlb should not resp valid") 278 assert(RegNext(!s1_valid || Cat(tlb_need_back).orR, true.B), "when s1_valid, need at least one tlb_need_back") 279 assert(RegNext(s1_valid || !Cat(tlb_need_back).orR, true.B), "when !s1_valid, all the tlb_need_back should be false") 280 assert(RegNext(s1_valid || !Cat(tlb_already_recv).orR, true.B), "when !s1_valid, should not tlb_already_recv") 281 assert(RegNext(s1_valid || !Cat(tlb_resp_valid).orR, true.B), "when !s1_valid, should not tlb_resp_valid") 282 283 val tlbRespPAddr = VecInit((0 until PortNumber).map(i => ResultHoldBypass(valid = tlb_back(i), data = fromITLB(i).bits.paddr(0)))) 284 val tlbExcpPF = VecInit((0 until PortNumber).map(i => ResultHoldBypass(valid = tlb_back(i), data = fromITLB(i).bits.excp(0).pf.instr) && tlb_need_back(i))) 285 val tlbExcpAF = VecInit((0 until PortNumber).map(i => ResultHoldBypass(valid = tlb_back(i), data = fromITLB(i).bits.excp(0).af.instr) && tlb_need_back(i))) 286 val tlbExcp = VecInit((0 until PortNumber).map(i => tlbExcpPF(i) || tlbExcpPF(i))) 287 288 val tlbRespAllValid = Cat((0 until PortNumber).map(i => !tlb_need_back(i) || tlb_resp_valid(i))).andR 289 s1_ready := s2_ready && tlbRespAllValid && !s1_wait || !s1_valid 290 s1_fire := s1_valid && tlbRespAllValid && s2_ready && !s1_wait 291 292 def numOfStage = 3 293 val itlbMissStage = RegInit(VecInit(Seq.fill(numOfStage - 1)(0.B))) 294 itlbMissStage(0) := !tlbRespAllValid 295 for (i <- 1 until numOfStage - 1) { 296 itlbMissStage(i) := itlbMissStage(i - 1) 297 } 298 299 300 /** s1 hit check/tag compare */ 301 val s1_req_paddr = tlbRespPAddr 302 val s1_req_ptags = VecInit(s1_req_paddr.map(get_phy_tag(_))) 303 304 val s1_meta_ptags = ResultHoldBypass(data = metaResp.tags, valid = RegNext(s0_fire)) 305 val s1_meta_valids = ResultHoldBypass(data = metaResp.entryValid, valid = RegNext(s0_fire)) 306 val s1_meta_errors = ResultHoldBypass(data = metaResp.errors, valid = RegNext(s0_fire)) 307 308 val s1_data_cacheline = ResultHoldBypass(data = dataResp.datas, valid = RegNext(s0_fire)) 309 val s1_data_errorBits = ResultHoldBypass(data = dataResp.codes, valid = RegNext(s0_fire)) 310 311 val s1_tag_eq_vec = VecInit((0 until PortNumber).map( p => VecInit((0 until nWays).map( w => s1_meta_ptags(p)(w) === s1_req_ptags(p) )))) 312 val s1_tag_match_vec = VecInit((0 until PortNumber).map( k => VecInit(s1_tag_eq_vec(k).zipWithIndex.map{ case(way_tag_eq, w) => way_tag_eq && s1_meta_valids(k)(w) /*s1_meta_cohs(k)(w).isValid()*/}))) 313 val s1_tag_match = VecInit(s1_tag_match_vec.map(vector => ParallelOR(vector))) 314 315 val s1_port_hit = VecInit(Seq(s1_tag_match(0) && s1_valid && !tlbExcp(0), s1_tag_match(1) && s1_valid && s1_double_line && !tlbExcp(1) )) 316 val s1_bank_miss = VecInit(Seq(!s1_tag_match(0) && s1_valid && !tlbExcp(0), !s1_tag_match(1) && s1_valid && s1_double_line && !tlbExcp(1) )) 317 val s1_hit = (s1_port_hit(0) && s1_port_hit(1)) || (!s1_double_line && s1_port_hit(0)) 318 319 /** choose victim cacheline */ 320 val replacers = Seq.fill(PortNumber)(ReplacementPolicy.fromString(cacheParams.replacer,nWays,nSets/PortNumber)) 321 val s1_victim_oh = ResultHoldBypass(data = VecInit(replacers.zipWithIndex.map{case (replacer, i) => UIntToOH(replacer.way(s1_req_vsetIdx(i)(highestIdxBit, 1)))}), valid = RegNext(s0_fire)) 322 323 324 when(s1_fire){ 325// when (!(PopCount(s1_tag_match_vec(0)) <= 1.U && (PopCount(s1_tag_match_vec(1)) <= 1.U || !s1_double_line))) { 326// printf("Multiple hit in main pipe\n") 327// } 328 assert(PopCount(s1_tag_match_vec(0)) <= 1.U && (PopCount(s1_tag_match_vec(1)) <= 1.U || !s1_double_line), 329 "Multiple hit in main pipe, port0:is=%d,ptag=0x%x,vidx=0x%x,vaddr=0x%x port1:is=%d,ptag=0x%x,vidx=0x%x,vaddr=0x%x ", 330 PopCount(s1_tag_match_vec(0)) > 1.U,s1_req_ptags(0), get_idx(s1_req_vaddr(0)), s1_req_vaddr(0), 331 PopCount(s1_tag_match_vec(1)) > 1.U && s1_double_line, s1_req_ptags(1), get_idx(s1_req_vaddr(1)), s1_req_vaddr(1)) 332 } 333 334 ((replacers zip touch_sets) zip touch_ways).map{case ((r, s),w) => r.access(s,w)} 335 336 IPFBufferMove.waymask := UIntToOH(replacers(0).way(IPFBufferMove.vsetIdx)) 337 /** check ipf */ 338 toIPF(0).valid := s1_valid && tlb_resp_valid(0) 339 toIPF(1).valid := s1_valid && s1_double_line && tlb_resp_valid(1) 340 (0 until PortNumber).foreach { i => 341 toIPF(i).bits.vaddr := s1_req_vaddr(i) 342 toIPF(i).bits.paddr := s1_req_paddr(i) 343 } 344 val s1_ipf_hit = VecInit((0 until PortNumber).map(i => toIPF(i).valid && fromIPF(i).valid && fromIPF(i).bits.ipf_hit)) // check in same cycle 345 val s1_ipf_hit_latch = VecInit((0 until PortNumber).map(i => holdReleaseLatch(valid = s1_ipf_hit(i), release = s1_fire, flush = false.B))) // when ipf return hit data, latch it! 346 val s1_ipf_data = VecInit((0 until PortNumber).map(i => ResultHoldBypass(data = fromIPF(i).bits.cacheline, valid = s1_ipf_hit(i)))) 347 348 /** check in PIQ, if hit, wait until prefetch port hit */ 349 //TODO: move this to PIQ 350 val PIQ_hold_res = RegInit(VecInit(Seq.fill(PortNumber)(false.B))) 351 fromPIQ.foreach(_.ready := true.B) 352 val PIQ_hit_oh = VecInit((0 until PortNumber).map(i => 353 VecInit(fromPIQ.map(entry => entry.valid && 354 entry.bits.vSetIdx === s1_req_vsetIdx(i) && 355 entry.bits.ptage === s1_req_ptags(i))))) // TODO : when piq1 has data piq0 miss but both hit,now we still need stall 356 (0 until PortNumber).foreach(i => assert(PopCount(PIQ_hit_oh(i)) <= 1.U, "multiple hit in PIQ\n")) 357 val PIQ_hit = VecInit(Seq(PIQ_hit_oh(0).reduce(_||_) && s1_valid && tlbRespAllValid, PIQ_hit_oh(1).reduce(_||_) && s1_valid && s1_double_line && tlbRespAllValid)) // TODO: Handle TLB blocking in the PIQ 358 val PIQ_hit_data = VecInit((0 until PortNumber).map(i => Mux1H(PIQ_hit_oh(i), fromPIQ.map(_.bits.cacheline)))) 359 val PIQ_data_valid = VecInit((0 until PortNumber).map(i => Mux1H(PIQ_hit_oh(i), fromPIQ.map(_.bits.writeBack)))) 360 val s1_wait_vec = VecInit((0 until PortNumber).map(i => !s1_port_hit(i) && !s1_ipf_hit_latch(i) && PIQ_hit(i) && !PIQ_data_valid(i) && !PIQ_hold_res(i))) 361 val PIQ_write_back = VecInit((0 until PortNumber).map(i => !s1_port_hit(i) && !s1_ipf_hit_latch(i) && PIQ_hit(i) && PIQ_data_valid(i))) 362 val s1_PIQ_hit = VecInit((0 until PortNumber).map(i => PIQ_write_back(i) || PIQ_hold_res(i))) 363 s1_wait := s1_valid && ((s1_wait_vec(0) && !tlbExcp(0)) || (s1_double_line && s1_wait_vec(1) && !tlbExcp(0) && !tlbExcp(1))) 364 365 (0 until PortNumber).foreach(i => 366 when(s1_fire){ 367 PIQ_hold_res(i) := false.B 368 }.elsewhen(PIQ_write_back(i)){ 369 PIQ_hold_res(i) := true.B 370 } 371 ) 372 373 val s1_PIQ_data = VecInit((0 until PortNumber).map( 374 i => 375 ResultHoldBypass(data = PIQ_hit_data(i), valid = PIQ_write_back(i)) 376 )) 377 378 val s1_prefetch_hit = VecInit((0 until PortNumber).map(i => s1_ipf_hit_latch(i) || s1_PIQ_hit(i))) 379 val s1_prefetch_hit_data = VecInit((0 until PortNumber).map(i => Mux(s1_ipf_hit_latch(i),s1_ipf_data(i), s1_PIQ_data(i)))) 380 381 if (env.EnableDifftest) { 382 (0 until PortNumber).foreach { i => 383 val diffPIQ = Module(new DifftestRefillEvent) 384 diffPIQ.io.clock := clock 385 diffPIQ.io.coreid := io.hartId 386 diffPIQ.io.cacheid := (i + 7).U 387 if (i == 0) diffPIQ.io.valid := s1_fire && !s1_port_hit(i) && !s1_ipf_hit_latch(i) && s1_PIQ_hit(i) && !tlbExcp(0) 388 else diffPIQ.io.valid := s1_fire && !s1_port_hit(i) && !s1_ipf_hit_latch(i) && s1_PIQ_hit(i) && s1_double_line && !tlbExcp(0) && !tlbExcp(1) 389 diffPIQ.io.addr := s1_req_paddr(i) 390 diffPIQ.io.data := s1_PIQ_data(i).asTypeOf(diffPIQ.io.data) 391 } 392 } 393 394 /** when tlb stall, ipfBuffer stage2 need also stall */ 395 mainPipeMissInfo.s1_already_check_ipf := s1_valid && tlbRespAllValid // when tlb back, s1 must has already check ipf 396 397 /** <PERF> replace victim way number */ 398 399 (0 until nWays).map{ w => 400 XSPerfAccumulate("line_0_hit_way_" + Integer.toString(w, 10), s1_fire && s1_port_hit(0) && OHToUInt(s1_tag_match_vec(0)) === w.U) 401 } 402 403 (0 until nWays).map{ w => 404 XSPerfAccumulate("line_0_victim_way_" + Integer.toString(w, 10), s1_fire && !s1_port_hit(0) && OHToUInt(s1_victim_oh(0)) === w.U) 405 } 406 407 (0 until nWays).map{ w => 408 XSPerfAccumulate("line_1_hit_way_" + Integer.toString(w, 10), s1_fire && s1_double_line && s1_port_hit(1) && OHToUInt(s1_tag_match_vec(1)) === w.U) 409 } 410 411 (0 until nWays).map{ w => 412 XSPerfAccumulate("line_1_victim_way_" + Integer.toString(w, 10), s1_fire && s1_double_line && !s1_port_hit(1) && OHToUInt(s1_victim_oh(1)) === w.U) 413 } 414 415 XSPerfAccumulate("mainPipe_stage1_block_by_piq_cycles", s1_valid && s1_wait) 416 417 /** 418 ****************************************************************************** 419 * ICache Stage 2 420 * - send request to MSHR if ICache miss 421 * - generate secondary miss status/data registers 422 * - response to IFU 423 ****************************************************************************** 424 */ 425 426 /** s2 control */ 427 val s2_fetch_finish = Wire(Bool()) 428 429 val s2_valid = generatePipeControl(lastFire = s1_fire, thisFire = s2_fire, thisFlush = false.B, lastFlush = false.B) 430 val s2_miss_available = Wire(Bool()) 431 432 s2_ready := (s2_valid && s2_fetch_finish && !io.respStall) || (!s2_valid && s2_miss_available) 433 s2_fire := s2_valid && s2_fetch_finish && !io.respStall 434 435 /** s2 data */ 436 val mmio = fromPMP.map(port => port.mmio) // TODO: handle it 437 438 val (s2_req_paddr , s2_req_vaddr) = (RegEnable(s1_req_paddr, s1_fire), RegEnable(s1_req_vaddr, s1_fire)) 439 val s2_req_vsetIdx = RegEnable(s1_req_vsetIdx, s1_fire) 440 val s2_req_ptags = RegEnable(s1_req_ptags, s1_fire) 441 val s2_only_first = RegEnable(s1_only_first, s1_fire) 442 val s2_double_line = RegEnable(s1_double_line, s1_fire) 443 val s2_hit = RegEnable(s1_hit , s1_fire) 444 val s2_port_hit = RegEnable(s1_port_hit, s1_fire) 445 val s2_bank_miss = RegEnable(s1_bank_miss, s1_fire) 446 val s2_waymask = RegEnable(s1_victim_oh, s1_fire) 447 val s2_tag_match_vec = RegEnable(s1_tag_match_vec, s1_fire) 448 val s2_prefetch_hit = RegEnable(s1_prefetch_hit, s1_fire) 449 val s2_prefetch_hit_data = RegEnable(s1_prefetch_hit_data, s1_fire) 450 val s2_prefetch_hit_in_ipf = RegEnable(s1_ipf_hit_latch, s1_fire) 451 val s2_prefetch_hit_in_piq = RegEnable(s1_PIQ_hit, s1_fire) 452 453 val icacheMissStage = RegInit(VecInit(Seq.fill(numOfStage - 2)(0.B))) 454 icacheMissStage(0) := !s2_hit 455 456 assert(RegNext(!s2_valid || s2_req_paddr(0)(11,0) === s2_req_vaddr(0)(11,0), true.B)) 457 458 /** status imply that s2 is a secondary miss (no need to resend miss request) */ 459 val sec_meet_vec = Wire(Vec(2, Bool())) 460 val s2_fixed_hit_vec = VecInit((0 until 2).map(i => s2_port_hit(i) || s2_prefetch_hit(i) || sec_meet_vec(i))) 461 val s2_fixed_hit = (s2_valid && s2_fixed_hit_vec(0) && s2_fixed_hit_vec(1) && s2_double_line) || (s2_valid && s2_fixed_hit_vec(0) && !s2_double_line) 462 463 val s2_meta_errors = RegEnable(s1_meta_errors, s1_fire) 464 val s2_data_errorBits = RegEnable(s1_data_errorBits, s1_fire) 465 val s2_data_cacheline = RegEnable(s1_data_cacheline, s1_fire) 466 467 val s2_data_errors = Wire(Vec(PortNumber,Vec(nWays, Bool()))) 468 469 (0 until PortNumber).map{ i => 470 val read_datas = s2_data_cacheline(i).asTypeOf(Vec(nWays,Vec(dataCodeUnitNum, UInt(dataCodeUnit.W)))) 471 val read_codes = s2_data_errorBits(i).asTypeOf(Vec(nWays,Vec(dataCodeUnitNum, UInt(dataCodeBits.W)))) 472 val data_full_wayBits = VecInit((0 until nWays).map( w => 473 VecInit((0 until dataCodeUnitNum).map(u => 474 Cat(read_codes(w)(u), read_datas(w)(u)))))) 475 val data_error_wayBits = VecInit((0 until nWays).map( w => 476 VecInit((0 until dataCodeUnitNum).map(u => 477 cacheParams.dataCode.decode(data_full_wayBits(w)(u)).error )))) 478 if(i == 0){ 479 (0 until nWays).map{ w => 480 s2_data_errors(i)(w) := RegNext(RegNext(s1_fire)) && RegNext(data_error_wayBits(w)).reduce(_||_) 481 } 482 } else { 483 (0 until nWays).map{ w => 484 s2_data_errors(i)(w) := RegNext(RegNext(s1_fire)) && RegNext(RegNext(s1_double_line)) && RegNext(data_error_wayBits(w)).reduce(_||_) 485 } 486 } 487 } 488 489 val s2_parity_meta_error = VecInit((0 until PortNumber).map(i => s2_meta_errors(i).reduce(_||_) && io.csr_parity_enable)) 490 val s2_parity_data_error = VecInit((0 until PortNumber).map(i => s2_data_errors(i).reduce(_||_) && io.csr_parity_enable)) 491 val s2_parity_error = VecInit((0 until PortNumber).map(i => RegNext(s2_parity_meta_error(i)) || s2_parity_data_error(i))) 492 493 for(i <- 0 until PortNumber){ 494 io.errors(i).valid := RegNext(s2_parity_error(i) && RegNext(RegNext(s1_fire))) 495 io.errors(i).report_to_beu := RegNext(s2_parity_error(i) && RegNext(RegNext(s1_fire))) 496 io.errors(i).paddr := RegNext(RegNext(s2_req_paddr(i))) 497 io.errors(i).source := DontCare 498 io.errors(i).source.tag := RegNext(RegNext(s2_parity_meta_error(i))) 499 io.errors(i).source.data := RegNext(s2_parity_data_error(i)) 500 io.errors(i).source.l2 := false.B 501 io.errors(i).opType := DontCare 502 io.errors(i).opType.fetch := true.B 503 } 504 XSError(s2_parity_error.reduce(_||_) && RegNext(RegNext(s1_fire)), "ICache has parity error in MainPaipe!") 505 506 507 /** exception and pmp logic **/ 508 //PMP Result 509 val s2_tlb_need_back = VecInit((0 until PortNumber).map(i => ValidHold(tlb_need_back(i) && s1_fire, s2_fire, false.B))) 510 val pmpExcpAF = Wire(Vec(PortNumber, Bool())) 511 pmpExcpAF(0) := fromPMP(0).instr && s2_tlb_need_back(0) 512 pmpExcpAF(1) := fromPMP(1).instr && s2_double_line && s2_tlb_need_back(1) 513 //exception information 514 //short delay exception signal 515 val s2_except_pf = RegEnable(tlbExcpPF, s1_fire) 516 val s2_except_tlb_af = RegEnable(tlbExcpAF, s1_fire) 517 //long delay exception signal 518 val s2_except_pmp_af = DataHoldBypass(pmpExcpAF, RegNext(s1_fire)) 519 // val s2_except_parity_af = VecInit(s2_parity_error(i) && RegNext(RegNext(s1_fire)) ) 520 521 val s2_except = VecInit((0 until 2).map{i => s2_except_pf(i) || s2_except_tlb_af(i)}) 522 val s2_has_except = s2_valid && (s2_except_tlb_af.reduce(_||_) || s2_except_pf.reduce(_||_)) 523 //MMIO 524 val s2_mmio = DataHoldBypass(io.pmp(0).resp.mmio && !s2_except_tlb_af(0) && !s2_except_pmp_af(0) && !s2_except_pf(0), RegNext(s1_fire)).asBool() && s2_valid 525 526 //send physical address to PMP 527 io.pmp.zipWithIndex.map { case (p, i) => 528 p.req.valid := s2_valid && !missSwitchBit 529 p.req.bits.addr := s2_req_paddr(i) 530 p.req.bits.size := 3.U // TODO 531 p.req.bits.cmd := TlbCmd.exec 532 } 533 534 /*** cacheline miss logic ***/ 535 val wait_idle :: wait_queue_ready :: wait_send_req :: wait_two_resp :: wait_0_resp :: wait_1_resp :: wait_one_resp ::wait_finish :: wait_pmp_except :: Nil = Enum(9) 536 val wait_state = RegInit(wait_idle) 537 538// val port_miss_fix = VecInit(Seq(fromMSHR(0).fire() && !s2_port_hit(0), fromMSHR(1).fire() && s2_double_line && !s2_port_hit(1) )) 539 540 // secondary miss record registers 541 class MissSlot(implicit p: Parameters) extends ICacheBundle { 542 val m_vSetIdx = UInt(idxBits.W) 543 val m_pTag = UInt(tagBits.W) 544 val m_data = UInt(blockBits.W) 545 val m_corrupt = Bool() 546 } 547 548 val missSlot = Seq.fill(2)(RegInit(0.U.asTypeOf(new MissSlot))) 549 val m_invalid :: m_valid :: m_refilled :: m_flushed :: m_wait_sec_miss :: m_check_final ::Nil = Enum(6) 550 val missStateQueue = RegInit(VecInit(Seq.fill(2)(m_invalid)) ) 551 val reservedRefillData = Wire(Vec(2, UInt(blockBits.W))) 552 553 s2_miss_available := VecInit(missStateQueue.map(entry => entry === m_invalid || entry === m_wait_sec_miss)).reduce(_&&_) 554 555 val fix_sec_miss = Wire(Vec(4, Bool())) 556 val sec_meet_0_miss = fix_sec_miss(0) || fix_sec_miss(2) 557 val sec_meet_1_miss = fix_sec_miss(1) || fix_sec_miss(3) 558 sec_meet_vec := VecInit(Seq(sec_meet_0_miss,sec_meet_1_miss )) 559 560 /*** miss/hit pattern: <Control Signal> only raise at the first cycle of s2_valid ***/ 561 val cacheline_0_hit = (s2_port_hit(0) || s2_prefetch_hit(0) || sec_meet_0_miss) 562 val cacheline_0_miss = !s2_port_hit(0) && !s2_prefetch_hit(0) && !sec_meet_0_miss 563 564 val cacheline_1_hit = (s2_port_hit(1) || s2_prefetch_hit(1) || sec_meet_1_miss) 565 val cacheline_1_miss = !s2_port_hit(1) && !s2_prefetch_hit(1) && !sec_meet_1_miss 566 567 val only_0_miss = RegNext(s1_fire) && cacheline_0_miss && !s2_double_line && !s2_has_except && !s2_mmio 568 val only_0_hit = RegNext(s1_fire) && cacheline_0_hit && !s2_double_line && !s2_mmio 569 val hit_0_hit_1 = RegNext(s1_fire) && cacheline_0_hit && cacheline_1_hit && s2_double_line && !s2_mmio 570 val hit_0_miss_1 = RegNext(s1_fire) && cacheline_0_hit && cacheline_1_miss && s2_double_line && !s2_has_except && !s2_mmio 571 val miss_0_hit_1 = RegNext(s1_fire) && cacheline_0_miss && cacheline_1_hit && s2_double_line && !s2_has_except && !s2_mmio 572 val miss_0_miss_1 = RegNext(s1_fire) && cacheline_0_miss && cacheline_1_miss && s2_double_line && !s2_has_except && !s2_mmio 573 574 val hit_0_except_1 = RegNext(s1_fire) && s2_double_line && !s2_except(0) && s2_except(1) && cacheline_0_hit 575 val miss_0_except_1 = RegNext(s1_fire) && s2_double_line && !s2_except(0) && s2_except(1) && cacheline_0_miss 576 val except_0 = RegNext(s1_fire) && s2_except(0) 577 578 /*** miss/hit pattern latch: <Control Signal> latch the miss/hit patter if pipeline stop ***/ 579 val miss_0_hit_1_latch = holdReleaseLatch(valid = miss_0_hit_1, release = s2_fire, flush = false.B) 580 val miss_0_miss_1_latch = holdReleaseLatch(valid = miss_0_miss_1, release = s2_fire, flush = false.B) 581 val only_0_miss_latch = holdReleaseLatch(valid = only_0_miss, release = s2_fire, flush = false.B) 582 val hit_0_miss_1_latch = holdReleaseLatch(valid = hit_0_miss_1, release = s2_fire, flush = false.B) 583 584 val miss_0_except_1_latch = holdReleaseLatch(valid = miss_0_except_1, release = s2_fire, flush = false.B) 585 val except_0_latch = holdReleaseLatch(valid = except_0, release = s2_fire, flush = false.B) 586 val hit_0_except_1_latch = holdReleaseLatch(valid = hit_0_except_1, release = s2_fire, flush = false.B) 587 588 val only_0_hit_latch = holdReleaseLatch(valid = only_0_hit, release = s2_fire, flush = false.B) 589 val hit_0_hit_1_latch = holdReleaseLatch(valid = hit_0_hit_1, release = s2_fire, flush = false.B) 590 591 592 /*** secondary miss judgment ***/ 593 594 def waitSecondComeIn(missState: UInt): Bool = (missState === m_wait_sec_miss) 595 596 def getMissSituat(slotNum : Int, missNum : Int ) :Bool = { 597 RegNext(s1_fire) && 598 RegNext(missSlot(slotNum).m_vSetIdx === s1_req_vsetIdx(missNum)) && 599 RegNext(missSlot(slotNum).m_pTag === s1_req_ptags(missNum)) && 600 !s2_port_hit(missNum) && !s2_prefetch_hit(missNum) && 601 waitSecondComeIn(missStateQueue(slotNum)) 602 } 603 604 val miss_0_s2_0 = getMissSituat(slotNum = 0, missNum = 0) 605 val miss_0_s2_1 = getMissSituat(slotNum = 0, missNum = 1) 606 val miss_1_s2_0 = getMissSituat(slotNum = 1, missNum = 0) 607 val miss_1_s2_1 = getMissSituat(slotNum = 1, missNum = 1) 608 609 val miss_0_s2_0_latch = holdReleaseLatch(valid = miss_0_s2_0, release = s2_fire, flush = false.B) 610 val miss_0_s2_1_latch = holdReleaseLatch(valid = miss_0_s2_1, release = s2_fire, flush = false.B) 611 val miss_1_s2_0_latch = holdReleaseLatch(valid = miss_1_s2_0, release = s2_fire, flush = false.B) 612 val miss_1_s2_1_latch = holdReleaseLatch(valid = miss_1_s2_1, release = s2_fire, flush = false.B) 613 614 615 val slot_0_solve = fix_sec_miss(0) || fix_sec_miss(1) 616 val slot_1_solve = fix_sec_miss(2) || fix_sec_miss(3) 617 val slot_slove = VecInit(Seq(slot_0_solve, slot_1_solve)) 618 619 fix_sec_miss := VecInit(Seq(miss_0_s2_0_latch, miss_0_s2_1_latch, miss_1_s2_0_latch, miss_1_s2_1_latch)) 620 621 /*** reserved data for secondary miss ***/ 622 623 reservedRefillData(0) := DataHoldBypass(data = missSlot(0).m_data, valid = miss_0_s2_0 || miss_0_s2_1) 624 reservedRefillData(1) := DataHoldBypass(data = missSlot(1).m_data, valid = miss_1_s2_0 || miss_1_s2_1) 625 626 /*** miss state machine ***/ 627 628 //deal with not-cache-hit pmp af 629 val only_pmp_af = Wire(Vec(2, Bool())) 630 only_pmp_af(0) := s2_except_pmp_af(0) && cacheline_0_miss && !s2_except(0) && s2_valid 631 only_pmp_af(1) := s2_except_pmp_af(1) && cacheline_1_miss && !s2_except(1) && s2_valid && s2_double_line 632 633 switch(wait_state){ 634 is(wait_idle){ 635 when(only_pmp_af(0) || only_pmp_af(1) || s2_mmio){ 636 //should not send req to MissUnit when there is an access exception in PMP 637 //But to avoid using pmp exception in control signal (like s2_fire), should delay 1 cycle. 638 //NOTE: pmp exception cache line also could hit in ICache, but the result is meaningless. Just give the exception signals. 639 wait_state := wait_finish 640 }.elsewhen(miss_0_except_1_latch){ 641 wait_state := Mux(toMSHR(0).ready, wait_queue_ready ,wait_idle ) 642 }.elsewhen( only_0_miss_latch || miss_0_hit_1_latch){ 643 wait_state := Mux(toMSHR(0).ready, wait_queue_ready ,wait_idle ) 644 }.elsewhen(hit_0_miss_1_latch){ 645 wait_state := Mux(toMSHR(1).ready, wait_queue_ready ,wait_idle ) 646 }.elsewhen( miss_0_miss_1_latch ){ 647 wait_state := Mux(toMSHR(0).ready && toMSHR(1).ready, wait_queue_ready ,wait_idle) 648 } 649 } 650 651 is(wait_queue_ready){ 652 wait_state := wait_send_req 653 } 654 655 is(wait_send_req) { 656 when(miss_0_except_1_latch || only_0_miss_latch || hit_0_miss_1_latch || miss_0_hit_1_latch){ 657 wait_state := wait_one_resp 658 }.elsewhen( miss_0_miss_1_latch ){ 659 wait_state := wait_two_resp 660 } 661 } 662 663 is(wait_one_resp) { 664 when( (miss_0_except_1_latch ||only_0_miss_latch || miss_0_hit_1_latch) && fromMSHR(0).fire()){ 665 wait_state := wait_finish 666 }.elsewhen( hit_0_miss_1_latch && fromMSHR(1).fire()){ 667 wait_state := wait_finish 668 } 669 } 670 671 is(wait_two_resp) { 672 when(fromMSHR(0).fire() && fromMSHR(1).fire()){ 673 wait_state := wait_finish 674 }.elsewhen( !fromMSHR(0).fire() && fromMSHR(1).fire() ){ 675 wait_state := wait_0_resp 676 }.elsewhen(fromMSHR(0).fire() && !fromMSHR(1).fire()){ 677 wait_state := wait_1_resp 678 } 679 } 680 681 is(wait_0_resp) { 682 when(fromMSHR(0).fire()){ 683 wait_state := wait_finish 684 } 685 } 686 687 is(wait_1_resp) { 688 when(fromMSHR(1).fire()){ 689 wait_state := wait_finish 690 } 691 } 692 693 is(wait_finish) {when(s2_fire) {wait_state := wait_idle } 694 } 695 } 696 697 698 /*** send request to MissUnit ***/ 699 700 (0 until 2).map { i => 701 if(i == 1) toMSHR(i).valid := (hit_0_miss_1_latch || miss_0_miss_1_latch) && wait_state === wait_queue_ready && !s2_mmio 702 else toMSHR(i).valid := (only_0_miss_latch || miss_0_hit_1_latch || miss_0_miss_1_latch || miss_0_except_1_latch) && wait_state === wait_queue_ready && !s2_mmio 703 toMSHR(i).bits.paddr := s2_req_paddr(i) 704 toMSHR(i).bits.vaddr := s2_req_vaddr(i) 705 toMSHR(i).bits.waymask := s2_waymask(i) 706 707 708 when(toMSHR(i).fire() && missStateQueue(i) === m_invalid){ 709 missStateQueue(i) := m_valid 710 missSlot(i).m_vSetIdx := s2_req_vsetIdx(i) 711 missSlot(i).m_pTag := get_phy_tag(s2_req_paddr(i)) 712 } 713 714 when(fromMSHR(i).fire() && missStateQueue(i) === m_valid ){ 715 missStateQueue(i) := m_refilled 716 missSlot(i).m_data := fromMSHR(i).bits.data 717 missSlot(i).m_corrupt := fromMSHR(i).bits.corrupt 718 } 719 720 721 when(s2_fire && missStateQueue(i) === m_refilled){ 722 missStateQueue(i) := m_wait_sec_miss 723 } 724 725 /*** Only the first cycle to check whether meet the secondary miss ***/ 726 when(missStateQueue(i) === m_wait_sec_miss){ 727 /*** The seondary req has been fix by this slot and another also hit || the secondary req for other cacheline and hit ***/ 728 when((slot_slove(i) && s2_fire) || (!slot_slove(i) && s2_fire) ) { 729 missStateQueue(i) := m_invalid 730 } 731 /*** The seondary req has been fix by this slot but another miss/f3 not ready || the seondary req for other cacheline and miss ***/ 732 .elsewhen((slot_slove(i) && !s2_fire && s2_valid) || (s2_valid && !slot_slove(i) && !s2_fire) ){ 733 missStateQueue(i) := m_check_final 734 } 735 } 736 737 when(missStateQueue(i) === m_check_final && toMSHR(i).fire()){ 738 missStateQueue(i) := m_valid 739 missSlot(i).m_vSetIdx := s2_req_vsetIdx(i) 740 missSlot(i).m_pTag := get_phy_tag(s2_req_paddr(i)) 741 }.elsewhen(missStateQueue(i) === m_check_final) { 742 missStateQueue(i) := m_invalid 743 } 744 } 745 746 io.prefetchEnable := false.B 747 io.prefetchDisable := false.B 748 when(toMSHR.map(_.valid).reduce(_||_)){ 749 missSwitchBit := true.B 750 io.prefetchEnable := true.B 751 }.elsewhen(missSwitchBit && s2_fetch_finish){ 752 missSwitchBit := false.B 753 io.prefetchDisable := true.B 754 } 755 756 (0 until PortNumber).foreach{ 757 i => 758 missSlotInfo(i).valid := missStateQueue(i) =/= m_invalid 759 missSlotInfo(i).bits.vSetIdx := missSlot(i).m_vSetIdx 760 missSlotInfo(i).bits.ptage := missSlot(i).m_pTag 761 } 762 763 764 val miss_all_fix = wait_state === wait_finish 765 766 s2_fetch_finish := ((s2_valid && s2_fixed_hit) || miss_all_fix || hit_0_except_1_latch || except_0_latch) 767 768 /** update replacement status register: 0 is hit access/ 1 is miss access */ 769 (touch_ways zip touch_sets).zipWithIndex.map{ case((t_w,t_s), i) => 770 t_s(0) := s2_req_vsetIdx(i)(highestIdxBit, 1) 771 t_w(0).valid := s2_valid && s2_port_hit(i) 772 t_w(0).bits := OHToUInt(s2_tag_match_vec(i)) 773 774 t_s(1) := s2_req_vsetIdx(i)(highestIdxBit, 1) 775 t_w(1).valid := s2_valid && !s2_port_hit(i) 776 t_w(1).bits := OHToUInt(s2_waymask(i)) 777 } 778 779 //** use hit one-hot select data 780 val s2_hit_datas = VecInit(s2_data_cacheline.zipWithIndex.map { case(bank, i) => 781 val port_hit_data = Mux1H(s2_tag_match_vec(i).asUInt, bank) 782 port_hit_data 783 }) 784 785 val s2_register_datas = Wire(Vec(2, UInt(blockBits.W))) 786 787 s2_register_datas.zipWithIndex.map{case(bank,i) => 788 // if(i == 0) bank := Mux(s2_port_hit(i), s2_hit_datas(i), Mux(miss_0_s2_0_latch,reservedRefillData(0), Mux(miss_1_s2_0_latch,reservedRefillData(1), missSlot(0).m_data))) 789 // else bank := Mux(s2_port_hit(i), s2_hit_datas(i), Mux(miss_0_s2_1_latch,reservedRefillData(0), Mux(miss_1_s2_1_latch,reservedRefillData(1), missSlot(1).m_data))) 790 if(i == 0) bank := Mux(miss_0_s2_0_latch,reservedRefillData(0), Mux(miss_1_s2_0_latch,reservedRefillData(1), missSlot(0).m_data)) 791 else bank := Mux(miss_0_s2_1_latch,reservedRefillData(0), Mux(miss_1_s2_1_latch,reservedRefillData(1), missSlot(1).m_data)) 792 } 793 794 /** response to IFU */ 795 796 (0 until PortNumber).map{ i => 797 if(i ==0) toIFU(i).valid := s2_fire 798 else toIFU(i).valid := s2_fire && s2_double_line 799 //when select is high, use sramData. Otherwise, use registerData. 800 toIFU(i).bits.registerData := s2_register_datas(i) 801 toIFU(i).bits.sramData := Mux(s2_port_hit(i), s2_hit_datas(i), s2_prefetch_hit_data(i)) 802 toIFU(i).bits.select := s2_port_hit(i) || s2_prefetch_hit(i) 803 toIFU(i).bits.paddr := s2_req_paddr(i) 804 toIFU(i).bits.vaddr := s2_req_vaddr(i) 805 toIFU(i).bits.tlbExcp.pageFault := s2_except_pf(i) 806 toIFU(i).bits.tlbExcp.accessFault := s2_except_tlb_af(i) || missSlot(i).m_corrupt || s2_except_pmp_af(i) 807 toIFU(i).bits.tlbExcp.mmio := s2_mmio 808 809 when(RegNext(s2_fire && missSlot(i).m_corrupt)){ 810 io.errors(i).valid := true.B 811 io.errors(i).report_to_beu := false.B // l2 should have report that to bus error unit, no need to do it again 812 io.errors(i).paddr := RegNext(s2_req_paddr(i)) 813 io.errors(i).source.tag := false.B 814 io.errors(i).source.data := false.B 815 io.errors(i).source.l2 := true.B 816 } 817 } 818 io.fetch.topdownIcacheMiss := !s2_hit 819 io.fetch.topdownItlbMiss := itlbMissStage(0) 820 821 (0 until 2).map {i => 822 XSPerfAccumulate("port_" + i + "_only_hit_in_ipf", !s2_port_hit(i) && s2_prefetch_hit(i) && s2_fire) 823 } 824 825 /** s2 mainPipe miss info */ 826 mainPipeMissInfo.s2_miss_info(0).valid := s2_valid && (miss_0_hit_1_latch || miss_0_miss_1_latch || only_0_miss_latch || miss_0_except_1_latch) && !except_0_latch 827 mainPipeMissInfo.s2_miss_info(1).valid := s2_valid && (miss_0_miss_1_latch || hit_0_miss_1_latch) 828 (0 until 2).foreach { i => 829 mainPipeMissInfo.s2_miss_info(i).bits.vSetIdx := s2_req_vsetIdx(i) 830 mainPipeMissInfo.s2_miss_info(i).bits.ptage := s2_req_ptags(i) 831 } 832 833 io.perfInfo.only_0_hit := only_0_hit_latch 834 io.perfInfo.only_0_miss := only_0_miss_latch 835 io.perfInfo.hit_0_hit_1 := hit_0_hit_1_latch 836 io.perfInfo.hit_0_miss_1 := hit_0_miss_1_latch 837 io.perfInfo.miss_0_hit_1 := miss_0_hit_1_latch 838 io.perfInfo.miss_0_miss_1 := miss_0_miss_1_latch 839 io.perfInfo.hit_0_except_1 := hit_0_except_1_latch 840 io.perfInfo.miss_0_except_1 := miss_0_except_1_latch 841 io.perfInfo.except_0 := except_0_latch 842 io.perfInfo.bank_hit(0) := only_0_miss_latch || hit_0_hit_1_latch || hit_0_miss_1_latch || hit_0_except_1_latch 843 io.perfInfo.bank_hit(1) := miss_0_hit_1_latch || hit_0_hit_1_latch 844 io.perfInfo.hit := hit_0_hit_1_latch || only_0_hit_latch || hit_0_except_1_latch || except_0_latch 845 846 /** <PERF> fetch bubble generated by icache miss*/ 847 848 XSPerfAccumulate("icache_bubble_s2_miss", s2_valid && !s2_fetch_finish ) 849 850 val tlb_miss_vec = VecInit((0 until PortNumber).map(i => toITLB(i).valid && s0_can_go && fromITLB(i).bits.miss)) 851 val tlb_has_miss = tlb_miss_vec.reduce(_ || _) 852 XSPerfAccumulate("icache_bubble_s0_tlb_miss", s0_valid && tlb_has_miss ) 853 854 if (env.EnableDifftest) { 855 val discards = (0 until PortNumber).map { i => 856 val discard = toIFU(i).bits.tlbExcp.pageFault || toIFU(i).bits.tlbExcp.accessFault || toIFU(i).bits.tlbExcp.mmio 857 discard 858 } 859 (0 until PortNumber).map { i => 860 val diffMainPipeOut = Module(new DifftestRefillEvent) 861 diffMainPipeOut.io.clock := clock 862 diffMainPipeOut.io.coreid := io.hartId 863 diffMainPipeOut.io.cacheid := (4 + i).U 864 if (i == 0) diffMainPipeOut.io.valid := s2_fire && !discards(0) 865 else diffMainPipeOut.io.valid := s2_fire && s2_double_line && !discards(0) && !discards(1) 866 diffMainPipeOut.io.addr := s2_req_paddr(i) 867 when (toIFU(i).bits.select.asBool) { 868 diffMainPipeOut.io.data := toIFU(i).bits.sramData.asTypeOf(diffMainPipeOut.io.data) 869 } .otherwise { 870 diffMainPipeOut.io.data := toIFU(i).bits.registerData.asTypeOf(diffMainPipeOut.io.data) 871 } 872 // idtfr: 1 -> data from icache 2 -> data from ipf 3 -> data from piq 4 -> data from missUnit 873 when (s2_port_hit(i)) { diffMainPipeOut.io.idtfr := 1.U } 874 .elsewhen(s2_prefetch_hit(i)) { 875 when (s2_prefetch_hit_in_ipf(i)) { diffMainPipeOut.io.idtfr := 2.U } 876 .elsewhen(s2_prefetch_hit_in_piq(i)) { diffMainPipeOut.io.idtfr := 3.U } 877 .otherwise { XSWarn(true.B, "should not in this situation\n")} 878 } 879 .otherwise { diffMainPipeOut.io.idtfr := 4.U } 880 diffMainPipeOut 881 } 882 } 883} 884