xref: /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala (revision eb163ef08fc5ac1da1f32d948699bd6de053e444) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.frontend.icache
18
19import chipsalliance.rocketchip.config.Parameters
20import chisel3._
21import chisel3.util._
22import freechips.rocketchip.tilelink.{ClientMetadata, TLPermissions}
23import xiangshan._
24import utils._
25
26class ICacheReadBundle(implicit p: Parameters) extends ICacheBundle
27{
28  val isDoubleLine  = Bool()
29  val vSetIdx       = Vec(2,UInt(log2Ceil(nSets).W))
30
31  def port_0_read_0 =  !vSetIdx(0)(0)
32  def port_0_read_1 =   vSetIdx(0)(0)
33  def port_1_read_0 =  !vSetIdx(1)(0) && isDoubleLine
34  def port_1_read_1 =   vSetIdx(1)(0) && isDoubleLine
35
36  def read_bank_0 = port_0_read_0 || port_1_read_0
37  def read_bank_1 =  port_0_read_1 || port_1_read_1
38}
39
40
41class ICacheMetaRespBundle(implicit p: Parameters) extends ICacheBundle
42{
43  val metaData   = Vec(2, Vec(nWays, new ICacheMetadata))
44  val errors     = Vec(2, Vec(nWays ,Bool() ))
45
46  def tags = VecInit(metaData.map(port => VecInit(port.map( way=> way.tag ))))
47  def cohs = VecInit(metaData.map(port => VecInit(port.map( way=> way.coh ))))
48}
49
50class ICacheMetaWriteBundle(implicit p: Parameters) extends ICacheBundle
51{
52  val virIdx  = UInt(idxBits.W)
53  val phyTag  = UInt(tagBits.W)
54  val coh     = new ClientMetadata
55  val waymask = UInt(nWays.W)
56  val bankIdx = Bool()
57
58  def generate(tag:UInt, coh: ClientMetadata, idx:UInt, waymask:UInt, bankIdx: Bool){
59    this.virIdx  := idx
60    this.phyTag  := tag
61    this.coh     := coh
62    this.waymask := waymask
63    this.bankIdx   := bankIdx
64  }
65
66}
67
68class ICacheDataWriteBundle(implicit p: Parameters) extends ICacheBundle
69{
70  val virIdx  = UInt(idxBits.W)
71  val data    = UInt(blockBits.W)
72  val waymask = UInt(nWays.W)
73  val bankIdx = Bool()
74  val paddr   = UInt(PAddrBits.W)
75
76  def generate(data:UInt, idx:UInt, waymask:UInt, bankIdx: Bool, paddr: UInt){
77    this.virIdx  := idx
78    this.data    := data
79    this.waymask := waymask
80    this.bankIdx := bankIdx
81    this.paddr   := paddr
82  }
83
84}
85
86class ICacheDataRespBundle(implicit p: Parameters) extends ICacheBundle
87{
88  val datas = Vec(2, Vec(nWays,  UInt(blockBits.W)))
89  val codes = Vec(2, Vec(nWays , UInt(dataCodeEntryBits.W)))
90}
91
92class ICacheMetaReadBundle(implicit p: Parameters) extends ICacheBundle
93{
94    val req     = Flipped(DecoupledIO(new ICacheReadBundle))
95    val resp = Output(new ICacheMetaRespBundle)
96}
97
98class ICacheCommonReadBundle(isMeta: Boolean)(implicit p: Parameters) extends ICacheBundle
99{
100    val req     = Flipped(DecoupledIO(new ICacheReadBundle))
101    val resp    = if(isMeta) Output(new ICacheMetaRespBundle) else Output(new ICacheDataRespBundle)
102}
103
104class ICacheProbeReq(implicit p: Parameters) extends ICacheBundle {
105  val miss = Bool()
106  val probe_param = UInt(TLPermissions.bdWidth.W)
107  val addr = UInt(PAddrBits.W)
108  val vaddr = UInt(VAddrBits.W)
109}
110
111class ICacheVictimInfor(implicit p: Parameters) extends ICacheBundle {
112  val valid = Bool()
113  val vidx  = UInt(idxBits.W)
114}