xref: /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala (revision dc4fac130426dbec49b49d778b9105d79b4a8eab) 
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
4* Copyright (c) 2020-2021 Peng Cheng Laboratory
5*
6* XiangShan is licensed under Mulan PSL v2.
7* You can use this software according to the terms and conditions of the Mulan PSL v2.
8* You may obtain a copy of Mulan PSL v2 at:
9*          http://license.coscl.org.cn/MulanPSL2
10*
11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
14*
15* See the Mulan PSL v2 for more details.
16***************************************************************************************/
17
18package xiangshan.frontend.icache
19
20import chisel3._
21import chisel3.util._
22import org.chipsalliance.cde.config.Parameters
23
24class ICacheReadBundle(implicit p: Parameters) extends ICacheBundle {
25  val vSetIdx:      Vec[UInt]      = Vec(2, UInt(idxBits.W))
26  val waymask:      Vec[Vec[Bool]] = Vec(2, Vec(nWays, Bool()))
27  val blkOffset:    UInt           = UInt(log2Ceil(blockBytes).W)
28  val isDoubleLine: Bool           = Bool()
29}
30
31class ICacheMetaWriteBundle(implicit p: Parameters) extends ICacheBundle {
32  val virIdx:  UInt = UInt(idxBits.W)
33  val phyTag:  UInt = UInt(tagBits.W)
34  val waymask: UInt = UInt(nWays.W)
35  val bankIdx: Bool = Bool()
36
37  def generate(tag: UInt, idx: UInt, waymask: UInt, bankIdx: Bool): Unit = {
38    this.virIdx  := idx
39    this.phyTag  := tag
40    this.waymask := waymask
41    this.bankIdx := bankIdx
42  }
43}
44
45class ICacheMetaFlushBundle(implicit p: Parameters) extends ICacheBundle {
46  val virIdx:  UInt = UInt(idxBits.W)
47  val waymask: UInt = UInt(nWays.W)
48}
49
50class ICacheDataWriteBundle(implicit p: Parameters) extends ICacheBundle {
51  val virIdx:  UInt = UInt(idxBits.W)
52  val data:    UInt = UInt(blockBits.W)
53  val waymask: UInt = UInt(nWays.W)
54  val bankIdx: Bool = Bool()
55
56  def generate(data: UInt, idx: UInt, waymask: UInt, bankIdx: Bool): Unit = {
57    this.virIdx  := idx
58    this.data    := data
59    this.waymask := waymask
60    this.bankIdx := bankIdx
61  }
62}
63
64class ICacheMetaRespBundle(implicit p: Parameters) extends ICacheBundle {
65  val metas:      Vec[Vec[ICacheMetadata]] = Vec(PortNumber, Vec(nWays, new ICacheMetadata))
66  val codes:      Vec[Vec[UInt]]           = Vec(PortNumber, Vec(nWays, UInt(ICacheMetaCodeBits.W)))
67  val entryValid: Vec[Vec[Bool]]           = Vec(PortNumber, Vec(nWays, Bool()))
68
69  // for compatibility
70  def tags: Vec[Vec[UInt]] = VecInit(metas.map(port => VecInit(port.map(way => way.tag))))
71}
72
73class ICacheDataRespBundle(implicit p: Parameters) extends ICacheBundle {
74  val datas: Vec[UInt] = Vec(ICacheDataBanks, UInt(ICacheDataBits.W))
75  val codes: Vec[UInt] = Vec(ICacheDataBanks, UInt(ICacheDataCodeBits.W))
76}
77
78class ReplacerTouch(implicit p: Parameters) extends ICacheBundle {
79  val vSetIdx: UInt = UInt(idxBits.W)
80  val way:     UInt = UInt(wayBits.W)
81}
82
83class ReplacerVictim(implicit p: Parameters) extends ICacheBundle {
84  val vSetIdx: Valid[UInt] = ValidIO(UInt(idxBits.W))
85  val way:     UInt        = Input(UInt(wayBits.W))
86}
87