xref: /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala (revision 887862dbb8debde8ab099befc426493834a69ee7) 
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
4* Copyright (c) 2020-2021 Peng Cheng Laboratory
5*
6* XiangShan is licensed under Mulan PSL v2.
7* You can use this software according to the terms and conditions of the Mulan PSL v2.
8* You may obtain a copy of Mulan PSL v2 at:
9*          http://license.coscl.org.cn/MulanPSL2
10*
11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
14*
15* See the Mulan PSL v2 for more details.
16***************************************************************************************/
17
18package xiangshan.frontend.icache
19
20import org.chipsalliance.cde.config.Parameters
21import chisel3._
22import chisel3.util._
23import freechips.rocketchip.tilelink.{ClientMetadata, TLPermissions}
24import xiangshan._
25import utils._
26import utility._
27
28class ICacheReadBundle(implicit p: Parameters) extends ICacheBundle
29{
30  val vSetIdx       = Vec(2,UInt(log2Ceil(nSets).W))
31  val wayMask       = Vec(2,Vec(nWays, Bool()))
32  val blkOffset     = UInt(log2Ceil(blockBytes).W)
33  val isDoubleLine  = Bool()
34}
35
36class ICacheMetaWriteBundle(implicit p: Parameters) extends ICacheBundle
37{
38  val virIdx  = UInt(idxBits.W)
39  val phyTag  = UInt(tagBits.W)
40  val waymask = UInt(nWays.W)
41  val bankIdx = Bool()
42
43  def generate(tag:UInt, idx:UInt, waymask:UInt, bankIdx: Bool): Unit = {
44    this.virIdx  := idx
45    this.phyTag  := tag
46    this.waymask := waymask
47    this.bankIdx   := bankIdx
48  }
49
50}
51
52class ICacheDataWriteBundle(implicit p: Parameters) extends ICacheBundle
53{
54  val virIdx  = UInt(idxBits.W)
55  val data    = UInt(blockBits.W)
56  val waymask = UInt(nWays.W)
57  val bankIdx = Bool()
58
59  def generate(data:UInt, idx:UInt, waymask:UInt, bankIdx: Bool): Unit = {
60    this.virIdx  := idx
61    this.data    := data
62    this.waymask := waymask
63    this.bankIdx := bankIdx
64  }
65
66}
67
68class ICacheMetaRespBundle(implicit p: Parameters) extends ICacheBundle
69{
70  val metas      = Vec(PortNumber, Vec(nWays, new ICacheMetadata))
71  val codes      = Vec(PortNumber, Vec(nWays, UInt(ICacheMetaCodeBits.W)))
72  val entryValid = Vec(PortNumber, Vec(nWays, Bool()))
73
74  // for compatibility
75  def tags = VecInit(metas.map(port => VecInit(port.map( way => way.tag ))))
76}
77
78class ICacheDataRespBundle(implicit p: Parameters) extends ICacheBundle
79{
80  val datas   = Vec(ICacheDataBanks, UInt(ICacheDataBits.W))
81  val codes   = Vec(ICacheDataBanks, UInt(ICacheDataCodeBits.W))
82}
83
84class ICacheMetaReadBundle(implicit p: Parameters) extends ICacheBundle
85{
86    val req     = Flipped(DecoupledIO(new ICacheReadBundle))
87    val resp = Output(new ICacheMetaRespBundle)
88}
89
90class ReplacerTouch(implicit p: Parameters) extends ICacheBundle {
91  val vSetIdx = UInt(log2Ceil(nSets).W)
92  val way     = UInt(log2Ceil(nWays).W)
93}
94
95class ReplacerVictim(implicit p: Parameters) extends ICacheBundle {
96  val vSetIdx = ValidIO(UInt(log2Ceil(nSets).W))
97  val way     = Input(UInt(log2Ceil(nWays).W))
98}