xref: /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala (revision 7a2fc509e2d355879c4db3dc3f17a6ccacd3d09e) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.frontend.icache
18
19import chipsalliance.rocketchip.config.Parameters
20import chisel3._
21import chisel3.util._
22import freechips.rocketchip.tilelink.{ClientMetadata, TLPermissions}
23import xiangshan._
24import utils._
25
26
27class ICacheReadBundle(implicit p: Parameters) extends ICacheBundle
28{
29  val isDoubleLine  = Bool()
30  val vSetIdx       = Vec(2,UInt(log2Ceil(nSets).W))
31}
32
33class ICacheMetaRespBundle(implicit p: Parameters) extends ICacheBundle
34{
35  val metaData   = Vec(2, Vec(nWays, new ICacheMetadata))
36  val errors = Vec(2, Vec(nWays ,Bool() ))
37
38  def tags = VecInit(metaData.map(port => VecInit(port.map( way=> way.tag ))))
39  def cohs = VecInit(metaData.map(port => VecInit(port.map( way=> way.coh ))))
40}
41
42class ICacheMetaWriteBundle(implicit p: Parameters) extends ICacheBundle
43{
44  val virIdx  = UInt(idxBits.W)
45  val phyTag  = UInt(tagBits.W)
46  val coh     = new ClientMetadata
47  val waymask = UInt(nWays.W)
48  val bankIdx = Bool()
49
50  def generate(tag:UInt, coh: ClientMetadata, idx:UInt, waymask:UInt, bankIdx: Bool){
51    this.virIdx  := idx
52    this.phyTag  := tag
53    this.coh     := coh
54    this.waymask := waymask
55    this.bankIdx   := bankIdx
56  }
57
58}
59
60class ICacheDataWriteBundle(implicit p: Parameters) extends ICacheBundle
61{
62  val virIdx  = UInt(idxBits.W)
63  val data    = UInt(blockBits.W)
64  val waymask = UInt(nWays.W)
65  val bankIdx = Bool()
66  val paddr   = UInt(PAddrBits.W)
67
68  def generate(data:UInt, idx:UInt, waymask:UInt, bankIdx: Bool, paddr: UInt){
69    this.virIdx  := idx
70    this.data    := data
71    this.waymask := waymask
72    this.bankIdx := bankIdx
73    this.paddr   := paddr
74  }
75
76}
77
78class ICacheDataRespBundle(implicit p: Parameters) extends ICacheBundle
79{
80  val datas = Vec(2, Vec(nWays,  UInt(blockBits.W)))
81  val codes = Vec(2, Vec(nWays , UInt(dataCodeEntryBits.W)))
82}
83
84class ICacheMetaReadBundle(implicit p: Parameters) extends ICacheBundle
85{
86    val req     = Flipped(DecoupledIO(new ICacheReadBundle))
87    val resp = Output(new ICacheMetaRespBundle)
88}
89
90class ICacheCommonReadBundle(isMeta: Boolean)(implicit p: Parameters) extends ICacheBundle
91{
92    val req     = Flipped(DecoupledIO(new ICacheReadBundle))
93    val resp    = if(isMeta) Output(new ICacheMetaRespBundle) else Output(new ICacheDataRespBundle)
94}
95
96class ICacheProbeReq(implicit p: Parameters) extends ICacheBundle {
97  val miss = Bool()
98  val probe_param = UInt(TLPermissions.bdWidth.W)
99  val addr = UInt(PAddrBits.W)
100  val vaddr = UInt(VAddrBits.W)
101}
102
103class ICacheVictimInfor(implicit p: Parameters) extends ICacheBundle {
104  val valid = Bool()
105  val vidx  = UInt(idxBits.W)
106}