xref: /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala (revision 51e45dbbf87325e45ff2af6ca86ed6c7eed04464) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.frontend.icache
18
19import org.chipsalliance.cde.config.Parameters
20import chisel3._
21import chisel3.util._
22import freechips.rocketchip.tilelink.{ClientMetadata, TLPermissions}
23import xiangshan._
24import utils._
25import utility._
26
27class ICacheReadBundle(implicit p: Parameters) extends ICacheBundle
28{
29  val isDoubleLine  = Bool()
30  val vSetIdx       = Vec(2,UInt(log2Ceil(nSets).W))
31
32  def port_0_read_0 =  !vSetIdx(0)(0)
33  def port_0_read_1 =   vSetIdx(0)(0)
34  def port_1_read_0 =  !vSetIdx(1)(0) && isDoubleLine
35  def port_1_read_1 =   vSetIdx(1)(0) && isDoubleLine
36
37  def read_bank_0 = port_0_read_0 || port_1_read_0
38  def read_bank_1 =  port_0_read_1 || port_1_read_1
39}
40
41
42class ICacheMetaRespBundle(implicit p: Parameters) extends ICacheBundle
43{
44  val metaData   = Vec(2, Vec(nWays, new ICacheMetadata))
45  val errors     = Vec(2, Vec(nWays ,Bool() ))
46  val entryValid = Vec(2, Vec(nWays, Bool()))
47
48  def tags = VecInit(metaData.map(port => VecInit(port.map( way=> way.tag ))))
49}
50
51class ICacheMetaWriteBundle(implicit p: Parameters) extends ICacheBundle
52{
53  val virIdx  = UInt(idxBits.W)
54  val phyTag  = UInt(tagBits.W)
55  val waymask = UInt(nWays.W)
56  val bankIdx = Bool()
57
58  def generate(tag:UInt, idx:UInt, waymask:UInt, bankIdx: Bool){
59    this.virIdx  := idx
60    this.phyTag  := tag
61    this.waymask := waymask
62    this.bankIdx   := bankIdx
63  }
64
65}
66
67class ICacheDataWriteBundle(implicit p: Parameters) extends ICacheBundle
68{
69  val virIdx  = UInt(idxBits.W)
70  val data    = UInt(blockBits.W)
71  val waymask = UInt(nWays.W)
72  val bankIdx = Bool()
73  val paddr   = UInt(PAddrBits.W)
74
75  def generate(data:UInt, idx:UInt, waymask:UInt, bankIdx: Bool, paddr: UInt){
76    this.virIdx  := idx
77    this.data    := data
78    this.waymask := waymask
79    this.bankIdx := bankIdx
80    this.paddr   := paddr
81  }
82
83}
84
85class ICacheDataRespBundle(implicit p: Parameters) extends ICacheBundle
86{
87  val datas = Vec(2, Vec(nWays,  UInt(blockBits.W)))
88  val codes = Vec(2, Vec(nWays , UInt(dataCodeEntryBits.W)))
89}
90
91class ICacheMetaReadBundle(implicit p: Parameters) extends ICacheBundle
92{
93    val req     = Flipped(DecoupledIO(new ICacheReadBundle))
94    val resp = Output(new ICacheMetaRespBundle)
95}
96
97class IPFBufferFilterRead(implicit p: Parameters) extends IPrefetchBundle{
98  /** input */
99  val req = new Bundle {
100    val paddr  = Input(UInt(PAddrBits.W))
101  }
102  /** output */
103  val resp = new Bundle {
104    val ipf_hit = Output(Bool())
105  }
106}
107
108class IPFBufferRead(implicit p: Parameters) extends IPrefetchBundle{
109  /** input */
110  val req = Vec(PortNumber, Flipped(DecoupledIO(new Bundle {
111    val paddr   = UInt(PAddrBits.W)
112  })))
113  /** output */
114  val resp = Vec(PortNumber, Output(new Bundle {
115    val ipf_hit   = Bool()
116    val cacheline = UInt(blockBits.W)
117  }))
118}
119
120class PIQFilterRead(implicit p: Parameters) extends IPrefetchBundle{
121  /** input */
122  val req = new Bundle {
123    val paddr  = Input(UInt(PAddrBits.W))
124  }
125  /** output */
126  val resp = new Bundle {
127    val piq_hit = Output(Bool())
128  }
129}
130
131class PIQRead(implicit p: Parameters) extends IPrefetchBundle{
132  /** input */
133  val req = Vec(PortNumber, Flipped(DecoupledIO(new Bundle {
134    val paddr   = UInt(PAddrBits.W)
135  })))
136  /** output */
137  val resp = Vec(PortNumber, Output(((new Bundle {
138    val piq_hit     = Bool()
139    val cacheline   = UInt(blockBits.W)
140    val data_valid  = Bool()
141  }))))
142}
143
144class IPFBufferWrite(implicit p: Parameters) extends  IPrefetchBundle{
145  val paddr     = UInt(PAddrBits.W)
146  val cacheline = UInt(blockBits.W)
147  val vSetIdx   = UInt(idxBits.W)
148  val has_hit   = Bool()
149}
150
151class IPFReplacer(implicit p: Parameters) extends  IPrefetchBundle{
152  val vsetIdx = Output(UInt(idxBits.W))
153  val waymask = Input(UInt(nWays.W))
154}
155
156class FilterInfo(implicit p: Parameters) extends ICacheBundle{
157  val paddr = UInt(PAddrBits.W)
158  val valid = Bool()
159}
160
161class MissSlotInfo(implicit p: Parameters) extends ICacheBundle{
162  val ptag    = UInt(tagBits.W)
163  val vSetIdx = UInt(idxBits.W)
164  val valid   = Bool()
165}
166
167class ICacheMissUnitInfo(implicit p: Parameters) extends IPrefetchBundle{
168  val mshr        = Output(Vec(PortNumber, new FilterInfo))
169  val recentWrite = Output(Vec(2, new FilterInfo))
170}
171
172class ICacheMainPipeInfo(implicit p: Parameters) extends IPrefetchBundle{
173  val s1Info = Output(Vec(PortNumber, new FilterInfo))
174  val s2Info = Output(Vec(PortNumber, new FilterInfo))
175  val missSlot = Output(Vec(PortNumber, new MissSlotInfo))
176}