xref: /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala (revision 2a3050c2e8117b17b696d8d20582def0e1751b5e) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.frontend.icache
18
19import chipsalliance.rocketchip.config.Parameters
20import chisel3._
21import chisel3.util._
22import freechips.rocketchip.tilelink.{ClientMetadata, TLPermissions}
23import xiangshan._
24import utils._
25
26
27class ICacheReadBundle(implicit p: Parameters) extends ICacheBundle
28{
29  val isDoubleLine  = Bool()
30  val vSetIdx       = Vec(2,UInt(log2Ceil(nSets).W))
31}
32
33class ICacheMetaRespBundle(implicit p: Parameters) extends ICacheBundle
34{
35  val metaData   = Vec(2, Vec(nWays, new ICacheMetadata))
36  val valid      = Vec(2, Vec(nWays ,Bool()))
37  val errors     = Vec(2, Vec(nWays ,Bool()))
38
39  def tags = VecInit(metaData.map(port => VecInit(port.map( way=> way.tag ))))
40  def cohs = VecInit(metaData.map(port => VecInit(port.map( way=> way.coh ))))
41}
42
43class ICacheMetaWriteBundle(implicit p: Parameters) extends ICacheBundle
44{
45  val virIdx  = UInt(idxBits.W)
46  val phyTag  = UInt(tagBits.W)
47  val coh     = new ClientMetadata
48  val waymask = UInt(nWays.W)
49  val bankIdx = Bool()
50
51  def generate(tag:UInt, coh: ClientMetadata, idx:UInt, waymask:UInt, bankIdx: Bool){
52    this.virIdx  := idx
53    this.phyTag  := tag
54    this.coh     := coh
55    this.waymask := waymask
56    this.bankIdx   := bankIdx
57  }
58
59}
60
61class ICacheDataWriteBundle(implicit p: Parameters) extends ICacheBundle
62{
63  val virIdx  = UInt(idxBits.W)
64  val data    = UInt(blockBits.W)
65  val waymask = UInt(nWays.W)
66  val bankIdx = Bool()
67
68  def generate(data:UInt, idx:UInt, waymask:UInt, bankIdx: Bool){
69    this.virIdx  := idx
70    this.data    := data
71    this.waymask := waymask
72    this.bankIdx := bankIdx
73  }
74
75}
76
77class ICacheDataRespBundle(implicit p: Parameters) extends ICacheBundle
78{
79  val datas = Vec(2,Vec(nWays,UInt(blockBits.W)))
80  val errors = Vec(2, Vec(nWays ,Bool() ))
81}
82
83class ICacheMetaReadBundle(implicit p: Parameters) extends ICacheBundle
84{
85    val req     = Flipped(DecoupledIO(new ICacheReadBundle))
86    val resp = Output(new ICacheMetaRespBundle)
87}
88
89class ICacheCommonReadBundle(isMeta: Boolean)(implicit p: Parameters) extends ICacheBundle
90{
91    val req     = Flipped(DecoupledIO(new ICacheReadBundle))
92    val resp    = if(isMeta) Output(new ICacheMetaRespBundle) else Output(new ICacheDataRespBundle)
93}
94
95class ICacheProbeReq(implicit p: Parameters) extends ICacheBundle {
96  val miss = Bool()
97  val probe_param = UInt(TLPermissions.bdWidth.W)
98  val addr = UInt(PAddrBits.W)
99  val vaddr = UInt(VAddrBits.W)
100}
101
102class ICacheVictimInfor(implicit p: Parameters) extends ICacheBundle {
103  val valid = Bool()
104  val vidx  = UInt(idxBits.W)
105}