xref: /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala (revision 211d620b07edb797ba35b635d24fef4e7294bae2) 
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
4* Copyright (c) 2020-2021 Peng Cheng Laboratory
5*
6* XiangShan is licensed under Mulan PSL v2.
7* You can use this software according to the terms and conditions of the Mulan PSL v2.
8* You may obtain a copy of Mulan PSL v2 at:
9*          http://license.coscl.org.cn/MulanPSL2
10*
11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
14*
15* See the Mulan PSL v2 for more details.
16***************************************************************************************/
17
18package xiangshan.frontend.icache
19
20import chisel3._
21import chisel3.util._
22import freechips.rocketchip.tilelink.ClientMetadata
23import freechips.rocketchip.tilelink.TLPermissions
24import org.chipsalliance.cde.config.Parameters
25import utility._
26import utils._
27import xiangshan._
28
29class ICacheReadBundle(implicit p: Parameters) extends ICacheBundle {
30  val vSetIdx      = Vec(2, UInt(log2Ceil(nSets).W))
31  val wayMask      = Vec(2, Vec(nWays, Bool()))
32  val blkOffset    = UInt(log2Ceil(blockBytes).W)
33  val isDoubleLine = Bool()
34}
35
36class ICacheMetaWriteBundle(implicit p: Parameters) extends ICacheBundle {
37  val virIdx  = UInt(idxBits.W)
38  val phyTag  = UInt(tagBits.W)
39  val waymask = UInt(nWays.W)
40  val bankIdx = Bool()
41
42  def generate(tag: UInt, idx: UInt, waymask: UInt, bankIdx: Bool): Unit = {
43    this.virIdx  := idx
44    this.phyTag  := tag
45    this.waymask := waymask
46    this.bankIdx := bankIdx
47  }
48
49}
50
51class ICacheDataWriteBundle(implicit p: Parameters) extends ICacheBundle {
52  val virIdx  = UInt(idxBits.W)
53  val data    = UInt(blockBits.W)
54  val waymask = UInt(nWays.W)
55  val bankIdx = Bool()
56
57  def generate(data: UInt, idx: UInt, waymask: UInt, bankIdx: Bool): Unit = {
58    this.virIdx  := idx
59    this.data    := data
60    this.waymask := waymask
61    this.bankIdx := bankIdx
62  }
63
64}
65
66class ICacheMetaRespBundle(implicit p: Parameters) extends ICacheBundle {
67  val metas      = Vec(PortNumber, Vec(nWays, new ICacheMetadata))
68  val codes      = Vec(PortNumber, Vec(nWays, UInt(ICacheMetaCodeBits.W)))
69  val entryValid = Vec(PortNumber, Vec(nWays, Bool()))
70
71  // for compatibility
72  def tags = VecInit(metas.map(port => VecInit(port.map(way => way.tag))))
73}
74
75class ICacheDataRespBundle(implicit p: Parameters) extends ICacheBundle {
76  val datas = Vec(ICacheDataBanks, UInt(ICacheDataBits.W))
77  val codes = Vec(ICacheDataBanks, UInt(ICacheDataCodeBits.W))
78}
79
80class ICacheMetaReadBundle(implicit p: Parameters) extends ICacheBundle {
81  val req  = Flipped(DecoupledIO(new ICacheReadBundle))
82  val resp = Output(new ICacheMetaRespBundle)
83}
84
85class ReplacerTouch(implicit p: Parameters) extends ICacheBundle {
86  val vSetIdx = UInt(log2Ceil(nSets).W)
87  val way     = UInt(log2Ceil(nWays).W)
88}
89
90class ReplacerVictim(implicit p: Parameters) extends ICacheBundle {
91  val vSetIdx = ValidIO(UInt(log2Ceil(nSets).W))
92  val way     = Input(UInt(log2Ceil(nWays).W))
93}
94