xref: /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala (revision 039cdc35f5f3b68b6295ec5ace90f22a77322e02) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.frontend.icache
18
19import org.chipsalliance.cde.config.Parameters
20import chisel3._
21import chisel3.util._
22import freechips.rocketchip.tilelink.{ClientMetadata, TLPermissions}
23import xiangshan._
24import utils._
25import utility._
26
27class ICacheReadBundle(implicit p: Parameters) extends ICacheBundle
28{
29  val vSetIdx       = Vec(2,UInt(log2Ceil(nSets).W))
30  val wayMask       = Vec(2,Vec(nWays, Bool()))
31  val blkOffset     = UInt(log2Ceil(blockBytes).W)
32  val isDoubleLine  = Bool()
33}
34
35
36class ICacheMetaRespBundle(implicit p: Parameters) extends ICacheBundle
37{
38  val metaData   = Vec(2, Vec(nWays, new ICacheMetadata))
39  val errors     = Vec(2, Vec(nWays ,Bool() ))
40  val entryValid = Vec(2, Vec(nWays, Bool()))
41
42  def tags = VecInit(metaData.map(port => VecInit(port.map( way=> way.tag ))))
43}
44
45class ICacheMetaWriteBundle(implicit p: Parameters) extends ICacheBundle
46{
47  val virIdx  = UInt(idxBits.W)
48  val phyTag  = UInt(tagBits.W)
49  val waymask = UInt(nWays.W)
50  val bankIdx = Bool()
51
52  def generate(tag:UInt, idx:UInt, waymask:UInt, bankIdx: Bool){
53    this.virIdx  := idx
54    this.phyTag  := tag
55    this.waymask := waymask
56    this.bankIdx   := bankIdx
57  }
58
59}
60
61class ICacheDataWriteBundle(implicit p: Parameters) extends ICacheBundle
62{
63  val virIdx  = UInt(idxBits.W)
64  val data    = UInt(blockBits.W)
65  val waymask = UInt(nWays.W)
66  val bankIdx = Bool()
67
68  def generate(data:UInt, idx:UInt, waymask:UInt, bankIdx: Bool){
69    this.virIdx  := idx
70    this.data    := data
71    this.waymask := waymask
72    this.bankIdx := bankIdx
73  }
74
75}
76
77class ICacheDataRespBundle(implicit p: Parameters) extends ICacheBundle
78{
79  val datas   = Vec(ICacheDataBanks, UInt(ICacheDataBits.W))
80  val codes   = Vec(ICacheDataBanks, UInt(ICacheCodeBits.W))
81}
82
83class ICacheMetaReadBundle(implicit p: Parameters) extends ICacheBundle
84{
85    val req     = Flipped(DecoupledIO(new ICacheReadBundle))
86    val resp = Output(new ICacheMetaRespBundle)
87}
88
89class ReplacerTouch(implicit p: Parameters) extends ICacheBundle {
90  val vSetIdx = UInt(log2Ceil(nSets).W)
91  val way     = UInt(log2Ceil(nWays).W)
92}
93
94class ReplacerVictim(implicit p: Parameters) extends ICacheBundle {
95  val vSetIdx = ValidIO(UInt(log2Ceil(nSets).W))
96  val way     = Input(UInt(log2Ceil(nWays).W))
97}