1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend.icache 18 19import chisel3._ 20import chisel3.util._ 21import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp} 22import freechips.rocketchip.tilelink._ 23import freechips.rocketchip.util.BundleFieldBase 24import huancun.{AliasField, PrefetchField} 25import org.chipsalliance.cde.config.Parameters 26import utility._ 27import utils._ 28import xiangshan._ 29import xiangshan.cache._ 30import xiangshan.cache.mmu.TlbRequestIO 31import xiangshan.frontend._ 32import firrtl.ir.Block 33 34case class ICacheParameters( 35 nSets: Int = 256, 36 nWays: Int = 4, 37 rowBits: Int = 64, 38 nTLBEntries: Int = 32, 39 tagECC: Option[String] = None, 40 dataECC: Option[String] = None, 41 replacer: Option[String] = Some("random"), 42 nMissEntries: Int = 2, 43 nReleaseEntries: Int = 1, 44 nProbeEntries: Int = 2, 45 // fdip default config 46 enableICachePrefetch: Boolean = true, 47 prefetchToL1: Boolean = false, 48 prefetchPipeNum: Int = 1, 49 nPrefetchEntries: Int = 12, 50 nPrefBufferEntries: Int = 32, 51 maxIPFMoveConf: Int = 1, // temporary use small value to cause more "move" operation 52 minRangeFromIFUptr: Int = 2, 53 maxRangeFromIFUptr: Int = 32, 54 55 nMMIOs: Int = 1, 56 blockBytes: Int = 64 57)extends L1CacheParameters { 58 59 val setBytes = nSets * blockBytes 60 val aliasBitsOpt = DCacheParameters().aliasBitsOpt //if(setBytes > pageSize) Some(log2Ceil(setBytes / pageSize)) else None 61 val reqFields: Seq[BundleFieldBase] = Seq( 62 PrefetchField(), 63 ReqSourceField() 64 ) ++ aliasBitsOpt.map(AliasField) 65 val echoFields: Seq[BundleFieldBase] = Nil 66 def tagCode: Code = Code.fromString(tagECC) 67 def dataCode: Code = Code.fromString(dataECC) 68 def replacement = ReplacementPolicy.fromString(replacer,nWays,nSets) 69} 70 71trait HasICacheParameters extends HasL1CacheParameters with HasInstrMMIOConst with HasIFUConst{ 72 val cacheParams = icacheParameters 73 val dataCodeUnit = 16 74 val dataCodeUnitNum = blockBits/2/dataCodeUnit 75 76 def highestIdxBit = log2Ceil(nSets) - 1 77 def encDataUnitBits = cacheParams.dataCode.width(dataCodeUnit) 78 def dataCodeBits = encDataUnitBits - dataCodeUnit 79 def dataCodeEntryBits = dataCodeBits * dataCodeUnitNum 80 81 val ICacheSets = cacheParams.nSets 82 val ICacheWays = cacheParams.nWays 83 84 val ICacheSameVPAddrLength = 12 85 val ReplaceIdWid = 5 86 87 val ICacheWordOffset = 0 88 val ICacheSetOffset = ICacheWordOffset + log2Up(blockBytes) 89 val ICacheAboveIndexOffset = ICacheSetOffset + log2Up(ICacheSets) 90 val ICacheTagOffset = ICacheAboveIndexOffset min ICacheSameVPAddrLength 91 92 def PortNumber = 2 93 94 def partWayNum = 4 95 def pWay = nWays/partWayNum 96 97 def enableICachePrefetch = cacheParams.enableICachePrefetch 98 def prefetchToL1 = cacheParams.prefetchToL1 99 def prefetchPipeNum = cacheParams.prefetchPipeNum 100 def nPrefetchEntries = cacheParams.nPrefetchEntries 101 def nPrefBufferEntries = cacheParams.nPrefBufferEntries 102 def maxIPFMoveConf = cacheParams.maxIPFMoveConf 103 def minRangeFromIFUptr = cacheParams.minRangeFromIFUptr 104 def maxRangeFromIFUptr = cacheParams.maxRangeFromIFUptr 105 106 def getBits(num: Int) = log2Ceil(num).W 107 108 109 def generatePipeControl(lastFire: Bool, thisFire: Bool, thisFlush: Bool, lastFlush: Bool): Bool = { 110 val valid = RegInit(false.B) 111 when(thisFlush) {valid := false.B} 112 .elsewhen(lastFire && !lastFlush) {valid := true.B} 113 .elsewhen(thisFire) {valid := false.B} 114 valid 115 } 116 117 def ResultHoldBypass[T<:Data](data: T, valid: Bool): T = { 118 Mux(valid, data, RegEnable(data, valid)) 119 } 120 121 def holdReleaseLatch(valid: Bool, release: Bool, flush: Bool): Bool ={ 122 val bit = RegInit(false.B) 123 when(flush) { bit := false.B } 124 .elsewhen(valid && !release) { bit := true.B } 125 .elsewhen(release) { bit := false.B } 126 bit || valid 127 } 128 129 def blockCounter(block: Bool, flush: Bool, threshold: Int): Bool = { 130 val counter = RegInit(0.U(log2Up(threshold + 1).W)) 131 when (block) { counter := counter + 1.U } 132 when (flush) { counter := 0.U} 133 counter > threshold.U 134 } 135 136 def InitQueue[T <: Data](entry: T, size: Int): Vec[T] ={ 137 return RegInit(VecInit(Seq.fill(size)(0.U.asTypeOf(entry.cloneType)))) 138 } 139 140 def getBlkAddr(addr: UInt) = addr >> log2Ceil(blockBytes) 141 142 require(isPow2(nSets), s"nSets($nSets) must be pow2") 143 require(isPow2(nWays), s"nWays($nWays) must be pow2") 144} 145 146abstract class ICacheBundle(implicit p: Parameters) extends XSBundle 147 with HasICacheParameters 148 149abstract class ICacheModule(implicit p: Parameters) extends XSModule 150 with HasICacheParameters 151 152abstract class ICacheArray(implicit p: Parameters) extends XSModule 153 with HasICacheParameters 154 155class ICacheMetadata(implicit p: Parameters) extends ICacheBundle { 156 val tag = UInt(tagBits.W) 157} 158 159object ICacheMetadata { 160 def apply(tag: Bits)(implicit p: Parameters) = { 161 val meta = Wire(new ICacheMetadata) 162 meta.tag := tag 163 meta 164 } 165} 166 167 168class ICacheMetaArray()(implicit p: Parameters) extends ICacheArray 169{ 170 def onReset = ICacheMetadata(0.U) 171 val metaBits = onReset.getWidth 172 val metaEntryBits = cacheParams.tagCode.width(metaBits) 173 174 val io=IO{new Bundle{ 175 val write = Flipped(DecoupledIO(new ICacheMetaWriteBundle)) 176 val read = Flipped(DecoupledIO(new ICacheReadBundle)) 177 val readResp = Output(new ICacheMetaRespBundle) 178 val cacheOp = Flipped(new L1CacheInnerOpIO) // customized cache op port 179 val fencei = Input(Bool()) 180 }} 181 182 io.read.ready := !io.write.valid 183 184 val port_0_read_0 = io.read.valid && !io.read.bits.vSetIdx(0)(0) 185 val port_0_read_1 = io.read.valid && io.read.bits.vSetIdx(0)(0) 186 val port_1_read_1 = io.read.valid && io.read.bits.vSetIdx(1)(0) && io.read.bits.isDoubleLine 187 val port_1_read_0 = io.read.valid && !io.read.bits.vSetIdx(1)(0) && io.read.bits.isDoubleLine 188 189 val port_0_read_0_reg = RegEnable(port_0_read_0, io.read.fire) 190 val port_0_read_1_reg = RegEnable(port_0_read_1, io.read.fire) 191 val port_1_read_1_reg = RegEnable(port_1_read_1, io.read.fire) 192 val port_1_read_0_reg = RegEnable(port_1_read_0, io.read.fire) 193 194 val bank_0_idx = Mux(port_0_read_0, io.read.bits.vSetIdx(0), io.read.bits.vSetIdx(1)) 195 val bank_1_idx = Mux(port_0_read_1, io.read.bits.vSetIdx(0), io.read.bits.vSetIdx(1)) 196 val bank_idx = Seq(bank_0_idx, bank_1_idx) 197 198 val write_bank_0 = io.write.valid && !io.write.bits.bankIdx 199 val write_bank_1 = io.write.valid && io.write.bits.bankIdx 200 201 val write_meta_bits = Wire(UInt(metaEntryBits.W)) 202 203 val tagArrays = (0 until 2) map { bank => 204 val tagArray = Module(new SRAMTemplate( 205 UInt(metaEntryBits.W), 206 set=nSets/2, 207 way=nWays, 208 shouldReset = true, 209 holdRead = true, 210 singlePort = true 211 )) 212 213 //meta connection 214 if(bank == 0) { 215 tagArray.io.r.req.valid := port_0_read_0 || port_1_read_0 216 tagArray.io.r.req.bits.apply(setIdx=bank_0_idx(highestIdxBit,1)) 217 tagArray.io.w.req.valid := write_bank_0 218 tagArray.io.w.req.bits.apply(data=write_meta_bits, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 219 } 220 else { 221 tagArray.io.r.req.valid := port_0_read_1 || port_1_read_1 222 tagArray.io.r.req.bits.apply(setIdx=bank_1_idx(highestIdxBit,1)) 223 tagArray.io.w.req.valid := write_bank_1 224 tagArray.io.w.req.bits.apply(data=write_meta_bits, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 225 } 226 227 tagArray 228 } 229 230 val read_set_idx_next = RegEnable(io.read.bits.vSetIdx, io.read.fire) 231 val valid_array = RegInit(VecInit(Seq.fill(nWays)(0.U(nSets.W)))) 232 val valid_metas = Wire(Vec(PortNumber, Vec(nWays, Bool()))) 233 // valid read 234 (0 until PortNumber).foreach( i => 235 (0 until nWays).foreach( way => 236 valid_metas(i)(way) := valid_array(way)(read_set_idx_next(i)) 237 )) 238 io.readResp.entryValid := valid_metas 239 240 io.read.ready := !io.write.valid && !io.fencei && tagArrays.map(_.io.r.req.ready).reduce(_&&_) 241 242 //Parity Decode 243 val read_metas = Wire(Vec(2,Vec(nWays,new ICacheMetadata()))) 244 for((tagArray,i) <- tagArrays.zipWithIndex){ 245 val read_meta_bits = tagArray.io.r.resp.asTypeOf(Vec(nWays,UInt(metaEntryBits.W))) 246 val read_meta_decoded = read_meta_bits.map{ way_bits => cacheParams.tagCode.decode(way_bits)} 247 val read_meta_wrong = read_meta_decoded.map{ way_bits_decoded => way_bits_decoded.error} 248 val read_meta_corrected = VecInit(read_meta_decoded.map{ way_bits_decoded => way_bits_decoded.corrected}) 249 read_metas(i) := read_meta_corrected.asTypeOf(Vec(nWays,new ICacheMetadata())) 250 (0 until nWays).map{ w => io.readResp.errors(i)(w) := RegNext(read_meta_wrong(w)) && RegNext(RegNext(io.read.fire))} 251 } 252 253 //Parity Encode 254 val write = io.write.bits 255 write_meta_bits := cacheParams.tagCode.encode(ICacheMetadata(tag = write.phyTag).asUInt) 256 257 // valid write 258 val way_num = OHToUInt(io.write.bits.waymask) 259 when (io.write.valid) { 260 valid_array(way_num) := valid_array(way_num).bitSet(io.write.bits.virIdx, true.B) 261 } 262 263 XSPerfAccumulate("meta_refill_num", io.write.valid) 264 265 io.readResp.metaData <> DontCare 266 when(port_0_read_0_reg){ 267 io.readResp.metaData(0) := read_metas(0) 268 }.elsewhen(port_0_read_1_reg){ 269 io.readResp.metaData(0) := read_metas(1) 270 } 271 272 when(port_1_read_0_reg){ 273 io.readResp.metaData(1) := read_metas(0) 274 }.elsewhen(port_1_read_1_reg){ 275 io.readResp.metaData(1) := read_metas(1) 276 } 277 278 279 io.write.ready := true.B // TODO : has bug ? should be !io.cacheOp.req.valid 280 // deal with customized cache op 281 require(nWays <= 32) 282 io.cacheOp.resp.bits := DontCare 283 val cacheOpShouldResp = WireInit(false.B) 284 when(io.cacheOp.req.valid){ 285 when( 286 CacheInstrucion.isReadTag(io.cacheOp.req.bits.opCode) || 287 CacheInstrucion.isReadTagECC(io.cacheOp.req.bits.opCode) 288 ){ 289 for (i <- 0 until 2) { 290 tagArrays(i).io.r.req.valid := true.B 291 tagArrays(i).io.r.req.bits.apply(setIdx = io.cacheOp.req.bits.index) 292 } 293 cacheOpShouldResp := true.B 294 } 295 when(CacheInstrucion.isWriteTag(io.cacheOp.req.bits.opCode)){ 296 for (i <- 0 until 2) { 297 tagArrays(i).io.w.req.valid := true.B 298 tagArrays(i).io.w.req.bits.apply( 299 data = io.cacheOp.req.bits.write_tag_low, 300 setIdx = io.cacheOp.req.bits.index, 301 waymask = UIntToOH(io.cacheOp.req.bits.wayNum(log2Ceil(nWays) - 1, 0)) 302 ) 303 } 304 cacheOpShouldResp := true.B 305 } 306 // TODO 307 // when(CacheInstrucion.isWriteTagECC(io.cacheOp.req.bits.opCode)){ 308 // for (i <- 0 until readPorts) { 309 // array(i).io.ecc_write.valid := true.B 310 // array(i).io.ecc_write.bits.idx := io.cacheOp.req.bits.index 311 // array(i).io.ecc_write.bits.way_en := UIntToOH(io.cacheOp.req.bits.wayNum(4, 0)) 312 // array(i).io.ecc_write.bits.ecc := io.cacheOp.req.bits.write_tag_ecc 313 // } 314 // cacheOpShouldResp := true.B 315 // } 316 } 317 io.cacheOp.resp.valid := RegNext(io.cacheOp.req.valid && cacheOpShouldResp) 318 io.cacheOp.resp.bits.read_tag_low := Mux(io.cacheOp.resp.valid, 319 tagArrays(0).io.r.resp.asTypeOf(Vec(nWays, UInt(tagBits.W)))(io.cacheOp.req.bits.wayNum), 320 0.U 321 ) 322 io.cacheOp.resp.bits.read_tag_ecc := DontCare // TODO 323 // TODO: deal with duplicated array 324 325 // fencei logic : reset valid_array 326 when (io.fencei) { 327 (0 until nWays).foreach( way => 328 valid_array(way) := 0.U 329 ) 330 } 331} 332 333 334 335class ICacheDataArray(implicit p: Parameters) extends ICacheArray 336{ 337 338 def getECCFromEncUnit(encUnit: UInt) = { 339 require(encUnit.getWidth == encDataUnitBits) 340 if (encDataUnitBits == dataCodeUnit) { 341 0.U.asTypeOf(UInt(1.W)) 342 } else { 343 encUnit(encDataUnitBits - 1, dataCodeUnit) 344 } 345 } 346 347 def getECCFromBlock(cacheblock: UInt) = { 348 // require(cacheblock.getWidth == blockBits) 349 VecInit((0 until dataCodeUnitNum).map { w => 350 val unit = cacheblock(dataCodeUnit * (w + 1) - 1, dataCodeUnit * w) 351 getECCFromEncUnit(cacheParams.dataCode.encode(unit)) 352 }) 353 } 354 355 val halfBlockBits = blockBits / 2 356 val codeBits = dataCodeEntryBits 357 358 val io=IO{new Bundle{ 359 val write = Flipped(DecoupledIO(new ICacheDataWriteBundle)) 360 val read = Flipped(DecoupledIO(Vec(partWayNum, new ICacheReadBundle))) 361 val readResp = Output(new ICacheDataRespBundle) 362 val cacheOp = Flipped(new L1CacheInnerOpIO) // customized cache op port 363 }} 364 io.cacheOp := DontCare 365 /** 366 ****************************************************************************** 367 * data array 368 ****************************************************************************** 369 */ 370 val write_data_bits = io.write.bits.data.asTypeOf(Vec(2, UInt(halfBlockBits.W))) 371 val dataArrays = (0 until partWayNum).map{ bank => 372 (0 until 2).map { i => 373 val sramBank = Module(new SRAMTemplate( 374 UInt(halfBlockBits.W), 375 set=nSets, 376 way=pWay, 377 shouldReset = true, 378 holdRead = true, 379 singlePort = true 380 )) 381 // SRAM read logic 382 sramBank.io.r.req.valid := io.read.valid 383 if (i == 1) { 384 sramBank.io.r.req.bits.apply(setIdx= io.read.bits(bank).vSetIdx(0)) 385 } else { 386 // read low of startline if cross cacheline 387 val setIdx = Mux(io.read.bits(bank).isDoubleLine, io.read.bits(bank).vSetIdx(1), io.read.bits(bank).vSetIdx(0)) 388 sramBank.io.r.req.bits.apply(setIdx= setIdx) 389 } 390 391 // SRAM write logic 392 val waymask = io.write.bits.waymask.asTypeOf(Vec(partWayNum, Vec(pWay, Bool())))(bank) 393 // waymask is invalid when way of SRAMTemplate is 1 394 sramBank.io.w.req.valid := io.write.valid && waymask.asUInt.orR 395 sramBank.io.w.req.bits.apply( 396 data = write_data_bits(i), 397 setIdx = io.write.bits.virIdx, 398 waymask = waymask.asUInt 399 ) 400 sramBank 401 } 402 } 403 404 /** 405 ****************************************************************************** 406 * data code array 407 ****************************************************************************** 408 */ 409 val write_code_bits = write_data_bits.map(getECCFromBlock(_).asUInt) 410 val codeArrays = (0 until 2) map { i => 411 val codeArray = Module(new SRAMTemplate( 412 UInt(codeBits.W), 413 set=nSets, 414 way=nWays, 415 shouldReset = true, 416 holdRead = true, 417 singlePort = true 418 )) 419 // SRAM read logic 420 codeArray.io.r.req.valid := io.read.valid 421 if (i == 1) { 422 codeArray.io.r.req.bits.apply(setIdx= io.read.bits.last.vSetIdx(0)) 423 } else { 424 val setIdx = Mux(io.read.bits.last.isDoubleLine, io.read.bits.last.vSetIdx(1), io.read.bits.last.vSetIdx(0)) 425 codeArray.io.r.req.bits.apply(setIdx= setIdx) 426 } 427 // SRAM write logic 428 codeArray.io.w.req.valid := io.write.valid 429 codeArray.io.w.req.bits.apply( 430 data = write_code_bits(i), 431 setIdx = io.write.bits.virIdx, 432 waymask = io.write.bits.waymask 433 ) 434 codeArray 435 } 436 437 /** 438 ****************************************************************************** 439 * read logic 440 ****************************************************************************** 441 */ 442 val isDoubleLineReg = RegEnable(io.read.bits.last.isDoubleLine, io.read.fire) 443 val read_data_bits = Wire(Vec(2,Vec(nWays,UInt(halfBlockBits.W)))) 444 val read_code_bits = Wire(Vec(2,Vec(nWays,UInt(codeBits.W)))) 445 446 (0 until nWays).map { w => 447 // first data 448 read_data_bits(0)(w) := Mux(isDoubleLineReg, 449 dataArrays(w/pWay)(1).io.r.resp.asTypeOf(Vec(pWay, UInt(halfBlockBits.W)))(w%pWay), 450 dataArrays(w/pWay)(0).io.r.resp.asTypeOf(Vec(pWay, UInt(halfBlockBits.W)))(w%pWay)) 451 // second data 452 read_data_bits(1)(w) := Mux(isDoubleLineReg, 453 dataArrays(w/pWay)(0).io.r.resp.asTypeOf(Vec(pWay, UInt(halfBlockBits.W)))(w%pWay), 454 dataArrays(w/pWay)(1).io.r.resp.asTypeOf(Vec(pWay, UInt(halfBlockBits.W)))(w%pWay)) 455 } 456 // first data code 457 read_code_bits(0) := Mux(isDoubleLineReg, 458 codeArrays(1).io.r.resp.asTypeOf(Vec(nWays, UInt(codeBits.W))), 459 codeArrays(0).io.r.resp.asTypeOf(Vec(nWays, UInt(codeBits.W)))) 460 // second data code 461 read_code_bits(1) := Mux(isDoubleLineReg, 462 codeArrays(0).io.r.resp.asTypeOf(Vec(nWays, UInt(codeBits.W))), 463 codeArrays(1).io.r.resp.asTypeOf(Vec(nWays, UInt(codeBits.W)))) 464 465 if (ICacheECCForceError) { 466 read_code_bits.foreach(_.foreach(_ := 0.U)) // force ecc to fail 467 } 468 469 /** 470 ****************************************************************************** 471 * IO 472 ****************************************************************************** 473 */ 474 io.readResp.datas := read_data_bits 475 io.readResp.codes := read_code_bits 476 io.write.ready := true.B 477 io.read.ready := !io.write.valid && 478 dataArrays.map(_.map(_.io.r.req.ready).reduce(_&&_)).reduce(_&&_) && 479 codeArrays.map(_.io.r.req.ready).reduce(_&&_) 480} 481 482 483class ICacheIO(implicit p: Parameters) extends ICacheBundle 484{ 485 val hartId = Input(UInt(hartIdLen.W)) 486 val prefetch = Flipped(new FtqPrefechBundle) 487 val stop = Input(Bool()) 488 val fetch = new ICacheMainPipeBundle 489 val toIFU = Output(Bool()) 490 val pmp = Vec(PortNumber + prefetchPipeNum, new ICachePMPBundle) 491 val itlb = Vec(PortNumber + prefetchPipeNum, new TlbRequestIO) 492 val perfInfo = Output(new ICachePerfInfo) 493 val error = new L1CacheErrorInfo 494 /* Cache Instruction */ 495 val csr = new L1CacheToCsrIO 496 /* CSR control signal */ 497 val csr_pf_enable = Input(Bool()) 498 val csr_parity_enable = Input(Bool()) 499 val fencei = Input(Bool()) 500} 501 502class ICache()(implicit p: Parameters) extends LazyModule with HasICacheParameters { 503 override def shouldBeInlined: Boolean = false 504 505 val clientParameters = TLMasterPortParameters.v1( 506 Seq(TLMasterParameters.v1( 507 name = "icache", 508 sourceId = IdRange(0, cacheParams.nMissEntries + 1), 509 )), 510 requestFields = cacheParams.reqFields, 511 echoFields = cacheParams.echoFields 512 ) 513 514 val clientNode = TLClientNode(Seq(clientParameters)) 515 516 lazy val module = new ICacheImp(this) 517} 518 519class ICacheImp(outer: ICache) extends LazyModuleImp(outer) with HasICacheParameters with HasPerfEvents { 520 val io = IO(new ICacheIO) 521 522 println("ICache:") 523 println(" ICacheSets: " + cacheParams.nSets) 524 println(" ICacheWays: " + cacheParams.nWays) 525 println(" ICacheBanks: " + PortNumber) 526 527 println(" enableICachePrefetch: " + cacheParams.enableICachePrefetch) 528 println(" prefetchToL1: " + cacheParams.prefetchToL1) 529 println(" prefetchPipeNum: " + cacheParams.prefetchPipeNum) 530 println(" nPrefetchEntries: " + cacheParams.nPrefetchEntries) 531 println(" nPrefBufferEntries: " + cacheParams.nPrefBufferEntries) 532 println(" maxIPFMoveConf: " + cacheParams.maxIPFMoveConf) 533 534 val (bus, edge) = outer.clientNode.out.head 535 536 val metaArray = Module(new ICacheMetaArray) 537 val dataArray = Module(new ICacheDataArray) 538 val prefetchMetaArray = Module(new ICacheMetaArrayNoBanked) 539 val mainPipe = Module(new ICacheMainPipe) 540 val missUnit = Module(new ICacheMissUnit(edge)) 541 val fdipPrefetch = Module(new FDIPPrefetch(edge)) 542 543 fdipPrefetch.io.hartId := io.hartId 544 fdipPrefetch.io.fencei := io.fencei 545 fdipPrefetch.io.ftqReq <> io.prefetch 546 fdipPrefetch.io.metaReadReq <> prefetchMetaArray.io.read 547 fdipPrefetch.io.metaReadResp <> prefetchMetaArray.io.readResp 548 fdipPrefetch.io.ICacheMissUnitInfo <> missUnit.io.ICacheMissUnitInfo 549 fdipPrefetch.io.ICacheMainPipeInfo <> mainPipe.io.ICacheMainPipeInfo 550 fdipPrefetch.io.IPFBufferRead <> mainPipe.io.IPFBufferRead 551 fdipPrefetch.io.IPFReplacer <> mainPipe.io.IPFReplacer 552 fdipPrefetch.io.PIQRead <> mainPipe.io.PIQRead 553 fdipPrefetch.io.metaWrite <> DontCare 554 fdipPrefetch.io.dataWrite <> DontCare 555 556 // Meta Array. Priority: missUnit > fdipPrefetch 557 if (prefetchToL1) { 558 val meta_write_arb = Module(new Arbiter(new ICacheMetaWriteBundle(), 2)) 559 meta_write_arb.io.in(0) <> missUnit.io.meta_write 560 meta_write_arb.io.in(1) <> fdipPrefetch.io.metaWrite 561 meta_write_arb.io.out <> metaArray.io.write 562 // prefetch Meta Array. Connect meta_write_arb to ensure the data is same as metaArray 563 prefetchMetaArray.io.write <> meta_write_arb.io.out 564 } else { 565 missUnit.io.meta_write <> metaArray.io.write 566 missUnit.io.meta_write <> prefetchMetaArray.io.write 567 // ensure together wirte to metaArray and prefetchMetaArray 568 missUnit.io.meta_write.ready := metaArray.io.write.ready && prefetchMetaArray.io.write.ready 569 } 570 571 // Data Array. Priority: missUnit > fdipPrefetch 572 if (prefetchToL1) { 573 val data_write_arb = Module(new Arbiter(new ICacheDataWriteBundle(), 2)) 574 data_write_arb.io.in(0) <> missUnit.io.data_write 575 data_write_arb.io.in(1) <> fdipPrefetch.io.dataWrite 576 data_write_arb.io.out <> dataArray.io.write 577 } else { 578 missUnit.io.data_write <> dataArray.io.write 579 } 580 581 mainPipe.io.dataArray.toIData <> dataArray.io.read 582 mainPipe.io.dataArray.fromIData <> dataArray.io.readResp 583 mainPipe.io.metaArray.toIMeta <> metaArray.io.read 584 mainPipe.io.metaArray.fromIMeta <> metaArray.io.readResp 585 mainPipe.io.metaArray.fromIMeta <> metaArray.io.readResp 586 mainPipe.io.respStall := io.stop 587 mainPipe.io.csr_parity_enable := io.csr_parity_enable 588 mainPipe.io.hartId := io.hartId 589 590 io.pmp(0) <> mainPipe.io.pmp(0) 591 io.pmp(1) <> mainPipe.io.pmp(1) 592 io.pmp(2) <> fdipPrefetch.io.pmp 593 594 io.itlb(0) <> mainPipe.io.itlb(0) 595 io.itlb(1) <> mainPipe.io.itlb(1) 596 io.itlb(2) <> fdipPrefetch.io.iTLBInter 597 598 //notify IFU that Icache pipeline is available 599 io.toIFU := mainPipe.io.fetch.req.ready 600 io.perfInfo := mainPipe.io.perfInfo 601 602 io.fetch.resp <> mainPipe.io.fetch.resp 603 io.fetch.topdownIcacheMiss := mainPipe.io.fetch.topdownIcacheMiss 604 io.fetch.topdownItlbMiss := mainPipe.io.fetch.topdownItlbMiss 605 606 for(i <- 0 until PortNumber){ 607 missUnit.io.req(i) <> mainPipe.io.mshr(i).toMSHR 608 mainPipe.io.mshr(i).fromMSHR <> missUnit.io.resp(i) 609 } 610 611 missUnit.io.hartId := io.hartId 612 missUnit.io.fencei := io.fencei 613 missUnit.io.fdip_acquire <> fdipPrefetch.io.mem_acquire 614 missUnit.io.fdip_grant <> fdipPrefetch.io.mem_grant 615 616 bus.b.ready := false.B 617 bus.c.valid := false.B 618 bus.c.bits := DontCare 619 bus.e.valid := false.B 620 bus.e.bits := DontCare 621 622 bus.a <> missUnit.io.mem_acquire 623 624 // connect bus d 625 missUnit.io.mem_grant.valid := false.B 626 missUnit.io.mem_grant.bits := DontCare 627 628 //Parity error port 629 val errors = mainPipe.io.errors 630 io.error <> RegNext(Mux1H(errors.map(e => e.valid -> e))) 631 632 633 mainPipe.io.fetch.req <> io.fetch.req 634 bus.d.ready := false.B 635 missUnit.io.mem_grant <> bus.d 636 637 // fencei connect 638 metaArray.io.fencei := io.fencei 639 prefetchMetaArray.io.fencei := io.fencei 640 641 val perfEvents = Seq( 642 ("icache_miss_cnt ", false.B), 643 ("icache_miss_penalty", BoolStopWatch(start = false.B, stop = false.B || false.B, startHighPriority = true)), 644 ) 645 generatePerfEvent() 646 647 // Customized csr cache op support 648 val cacheOpDecoder = Module(new CSRCacheOpDecoder("icache", CacheInstrucion.COP_ID_ICACHE)) 649 cacheOpDecoder.io.csr <> io.csr 650 dataArray.io.cacheOp.req := cacheOpDecoder.io.cache.req 651 metaArray.io.cacheOp.req := cacheOpDecoder.io.cache.req 652 prefetchMetaArray.io.cacheOp.req := cacheOpDecoder.io.cache.req 653 cacheOpDecoder.io.cache.resp.valid := 654 dataArray.io.cacheOp.resp.valid || 655 metaArray.io.cacheOp.resp.valid 656 cacheOpDecoder.io.cache.resp.bits := Mux1H(List( 657 dataArray.io.cacheOp.resp.valid -> dataArray.io.cacheOp.resp.bits, 658 metaArray.io.cacheOp.resp.valid -> metaArray.io.cacheOp.resp.bits, 659 )) 660 cacheOpDecoder.io.error := io.error 661 assert(!((dataArray.io.cacheOp.resp.valid +& metaArray.io.cacheOp.resp.valid) > 1.U)) 662} 663 664class ICachePartWayReadBundle[T <: Data](gen: T, pWay: Int)(implicit p: Parameters) 665 extends ICacheBundle 666{ 667 val req = Flipped(Vec(PortNumber, Decoupled(new Bundle{ 668 val ridx = UInt((log2Ceil(nSets) - 1).W) 669 }))) 670 val resp = Output(new Bundle{ 671 val rdata = Vec(PortNumber,Vec(pWay, gen)) 672 }) 673} 674 675class ICacheWriteBundle[T <: Data](gen: T, pWay: Int)(implicit p: Parameters) 676 extends ICacheBundle 677{ 678 val wdata = gen 679 val widx = UInt((log2Ceil(nSets) - 1).W) 680 val wbankidx = Bool() 681 val wmask = Vec(pWay, Bool()) 682} 683 684class ICachePartWayArray[T <: Data](gen: T, pWay: Int)(implicit p: Parameters) extends ICacheArray 685{ 686 687 //including part way data 688 val io = IO{new Bundle { 689 val read = new ICachePartWayReadBundle(gen,pWay) 690 val write = Flipped(ValidIO(new ICacheWriteBundle(gen, pWay))) 691 }} 692 693 io.read.req.map(_.ready := !io.write.valid) 694 695 val srams = (0 until PortNumber) map { bank => 696 val sramBank = Module(new SRAMTemplate( 697 gen, 698 set=nSets/2, 699 way=pWay, 700 shouldReset = true, 701 holdRead = true, 702 singlePort = true 703 )) 704 705 sramBank.io.r.req.valid := io.read.req(bank).valid 706 sramBank.io.r.req.bits.apply(setIdx= io.read.req(bank).bits.ridx) 707 708 if(bank == 0) sramBank.io.w.req.valid := io.write.valid && !io.write.bits.wbankidx 709 else sramBank.io.w.req.valid := io.write.valid && io.write.bits.wbankidx 710 sramBank.io.w.req.bits.apply(data=io.write.bits.wdata, setIdx=io.write.bits.widx, waymask=io.write.bits.wmask.asUInt) 711 712 sramBank 713 } 714 715 io.read.req.map(_.ready := !io.write.valid && srams.map(_.io.r.req.ready).reduce(_&&_)) 716 717 io.read.resp.rdata := VecInit(srams.map(bank => bank.io.r.resp.asTypeOf(Vec(pWay,gen)))) 718 719} 720