1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend.icache 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util.{DecoupledIO, _} 22import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp, TransferSizes} 23import freechips.rocketchip.tilelink._ 24import freechips.rocketchip.util.BundleFieldBase 25import huancun.{AliasField, DirtyField, PreferCacheField, PrefetchField} 26import xiangshan._ 27import xiangshan.frontend._ 28import xiangshan.cache._ 29import utils.{SRAMTemplate, _} 30import xiangshan.backend.fu.PMPReqBundle 31import xiangshan.cache.mmu.{TlbRequestIO, TlbReq} 32 33case class ICacheParameters( 34 nSets: Int = 256, 35 nWays: Int = 8, 36 rowBits: Int = 64, 37 nTLBEntries: Int = 32, 38 tagECC: Option[String] = None, 39 dataECC: Option[String] = None, 40 replacer: Option[String] = Some("random"), 41 nMissEntries: Int = 2, 42 nReleaseEntries: Int = 1, 43 nProbeEntries: Int = 2, 44 nPrefetchEntries: Int = 4, 45 hasPrefetch: Boolean = false, 46 nMMIOs: Int = 1, 47 blockBytes: Int = 64 48)extends L1CacheParameters { 49 50 val setBytes = nSets * blockBytes 51 val aliasBitsOpt = if(setBytes > pageSize) Some(log2Ceil(setBytes / pageSize)) else None 52 val reqFields: Seq[BundleFieldBase] = Seq( 53 PrefetchField(), 54 PreferCacheField() 55 ) ++ aliasBitsOpt.map(AliasField) 56 val echoFields: Seq[BundleFieldBase] = Seq(DirtyField()) 57 def tagCode: Code = Code.fromString(tagECC) 58 def dataCode: Code = Code.fromString(dataECC) 59 def replacement = ReplacementPolicy.fromString(replacer,nWays,nSets) 60} 61 62trait HasICacheParameters extends HasL1CacheParameters with HasInstrMMIOConst with HasIFUConst{ 63 val cacheParams = icacheParameters 64 val dataCodeUnit = 16 65 val dataCodeUnitNum = blockBits/dataCodeUnit 66 67 def highestIdxBit = log2Ceil(nSets) - 1 68 def encDataUnitBits = cacheParams.dataCode.width(dataCodeUnit) 69 def dataCodeBits = encDataUnitBits - dataCodeUnit 70 def dataCodeEntryBits = dataCodeBits * dataCodeUnitNum 71 72 val ICacheSets = cacheParams.nSets 73 val ICacheWays = cacheParams.nWays 74 75 val ICacheSameVPAddrLength = 12 76 val ReplaceIdWid = 5 77 78 val ICacheWordOffset = 0 79 val ICacheSetOffset = ICacheWordOffset + log2Up(blockBytes) 80 val ICacheAboveIndexOffset = ICacheSetOffset + log2Up(ICacheSets) 81 val ICacheTagOffset = ICacheAboveIndexOffset min ICacheSameVPAddrLength 82 83 def ReplacePipeKey = 0 84 def MainPipeKey = 1 85 def PortNumber = 2 86 def ProbeKey = 3 87 88 def partWayNum = 4 89 def pWay = nWays/partWayNum 90 91 def nPrefetchEntries = cacheParams.nPrefetchEntries 92 93 def getBits(num: Int) = log2Ceil(num).W 94 95 96 def generatePipeControl(lastFire: Bool, thisFire: Bool, thisFlush: Bool, lastFlush: Bool): Bool = { 97 val valid = RegInit(false.B) 98 when(thisFlush) {valid := false.B} 99 .elsewhen(lastFire && !lastFlush) {valid := true.B} 100 .elsewhen(thisFire) {valid := false.B} 101 valid 102 } 103 104 def ResultHoldBypass[T<:Data](data: T, valid: Bool): T = { 105 Mux(valid, data, RegEnable(data, valid)) 106 } 107 108 require(isPow2(nSets), s"nSets($nSets) must be pow2") 109 require(isPow2(nWays), s"nWays($nWays) must be pow2") 110} 111 112abstract class ICacheBundle(implicit p: Parameters) extends XSBundle 113 with HasICacheParameters 114 115abstract class ICacheModule(implicit p: Parameters) extends XSModule 116 with HasICacheParameters 117 118abstract class ICacheArray(implicit p: Parameters) extends XSModule 119 with HasICacheParameters 120 121class ICacheMetadata(implicit p: Parameters) extends ICacheBundle { 122 val coh = new ClientMetadata 123 val tag = UInt(tagBits.W) 124} 125 126object ICacheMetadata { 127 def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = { 128 val meta = Wire(new L1Metadata) 129 meta.tag := tag 130 meta.coh := coh 131 meta 132 } 133} 134 135 136class ICacheMetaArray()(implicit p: Parameters) extends ICacheArray 137{ 138 def onReset = ICacheMetadata(0.U, ClientMetadata.onReset) 139 val metaBits = onReset.getWidth 140 val metaEntryBits = cacheParams.tagCode.width(metaBits) 141 142 val io=IO{new Bundle{ 143 val write = Flipped(DecoupledIO(new ICacheMetaWriteBundle)) 144 val read = Flipped(DecoupledIO(new ICacheReadBundle)) 145 val readResp = Output(new ICacheMetaRespBundle) 146 val cacheOp = Flipped(new L1CacheInnerOpIO) // customized cache op port 147 }} 148 149 io.read.ready := !io.write.valid 150 151 val port_0_read_0 = io.read.valid && !io.read.bits.vSetIdx(0)(0) 152 val port_0_read_1 = io.read.valid && io.read.bits.vSetIdx(0)(0) 153 val port_1_read_1 = io.read.valid && io.read.bits.vSetIdx(1)(0) && io.read.bits.isDoubleLine 154 val port_1_read_0 = io.read.valid && !io.read.bits.vSetIdx(1)(0) && io.read.bits.isDoubleLine 155 156 val port_0_read_0_reg = RegEnable(next = port_0_read_0, enable = io.read.fire()) 157 val port_0_read_1_reg = RegEnable(next = port_0_read_1, enable = io.read.fire()) 158 val port_1_read_1_reg = RegEnable(next = port_1_read_1, enable = io.read.fire()) 159 val port_1_read_0_reg = RegEnable(next = port_1_read_0, enable = io.read.fire()) 160 161 val bank_0_idx = Mux(port_0_read_0, io.read.bits.vSetIdx(0), io.read.bits.vSetIdx(1)) 162 val bank_1_idx = Mux(port_0_read_1, io.read.bits.vSetIdx(0), io.read.bits.vSetIdx(1)) 163 val bank_idx = Seq(bank_0_idx, bank_1_idx) 164 165 val write_bank_0 = io.write.valid && !io.write.bits.bankIdx 166 val write_bank_1 = io.write.valid && io.write.bits.bankIdx 167 168 val write_meta_bits = Wire(UInt(metaEntryBits.W)) 169 170 val tagArrays = (0 until 2) map { bank => 171 val tagArray = Module(new SRAMTemplate( 172 UInt(metaEntryBits.W), 173 set=nSets/2, 174 way=nWays, 175 shouldReset = true, 176 holdRead = true, 177 singlePort = true 178 )) 179 180 //meta connection 181 if(bank == 0) { 182 tagArray.io.r.req.valid := port_0_read_0 || port_1_read_0 183 tagArray.io.r.req.bits.apply(setIdx=bank_0_idx(highestIdxBit,1)) 184 tagArray.io.w.req.valid := write_bank_0 185 tagArray.io.w.req.bits.apply(data=write_meta_bits, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 186 } 187 else { 188 tagArray.io.r.req.valid := port_0_read_1 || port_1_read_1 189 tagArray.io.r.req.bits.apply(setIdx=bank_1_idx(highestIdxBit,1)) 190 tagArray.io.w.req.valid := write_bank_1 191 tagArray.io.w.req.bits.apply(data=write_meta_bits, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 192 } 193 194 tagArray 195 } 196 197 io.read.ready := !io.write.valid && tagArrays.map(_.io.r.req.ready).reduce(_&&_) 198 199 //Parity Decode 200 val read_metas = Wire(Vec(2,Vec(nWays,new ICacheMetadata()))) 201 for((tagArray,i) <- tagArrays.zipWithIndex){ 202 val read_meta_bits = tagArray.io.r.resp.asTypeOf(Vec(nWays,UInt(metaEntryBits.W))) 203 val read_meta_decoded = read_meta_bits.map{ way_bits => cacheParams.tagCode.decode(way_bits)} 204 val read_meta_wrong = read_meta_decoded.map{ way_bits_decoded => way_bits_decoded.error} 205 val read_meta_corrected = VecInit(read_meta_decoded.map{ way_bits_decoded => way_bits_decoded.corrected}) 206 read_metas(i) := read_meta_corrected.asTypeOf(Vec(nWays,new ICacheMetadata())) 207 (0 until nWays).map{ w => io.readResp.errors(i)(w) := RegNext(read_meta_wrong(w)) && RegNext(RegNext(io.read.fire))} 208 } 209 210 //Parity Encode 211 val write = io.write.bits 212 write_meta_bits := cacheParams.tagCode.encode(ICacheMetadata(tag = write.phyTag, coh = write.coh).asUInt) 213 214 val wayNum = OHToUInt(io.write.bits.waymask) 215 val validPtr = Cat(io.write.bits.virIdx, wayNum) 216 217 io.readResp.metaData <> DontCare 218 when(port_0_read_0_reg){ 219 io.readResp.metaData(0) := read_metas(0) 220 }.elsewhen(port_0_read_1_reg){ 221 io.readResp.metaData(0) := read_metas(1) 222 } 223 224 when(port_1_read_0_reg){ 225 io.readResp.metaData(1) := read_metas(0) 226 }.elsewhen(port_1_read_1_reg){ 227 io.readResp.metaData(1) := read_metas(1) 228 } 229 230 231 io.write.ready := true.B 232 // deal with customized cache op 233 require(nWays <= 32) 234 io.cacheOp.resp.bits := DontCare 235 val cacheOpShouldResp = WireInit(false.B) 236 when(io.cacheOp.req.valid){ 237 when( 238 CacheInstrucion.isReadTag(io.cacheOp.req.bits.opCode) || 239 CacheInstrucion.isReadTagECC(io.cacheOp.req.bits.opCode) 240 ){ 241 for (i <- 0 until 2) { 242 tagArrays(i).io.r.req.valid := true.B 243 tagArrays(i).io.r.req.bits.apply(setIdx = io.cacheOp.req.bits.index) 244 } 245 cacheOpShouldResp := true.B 246 } 247 when(CacheInstrucion.isWriteTag(io.cacheOp.req.bits.opCode)){ 248 for (i <- 0 until 2) { 249 tagArrays(i).io.w.req.valid := true.B 250 tagArrays(i).io.w.req.bits.apply( 251 data = io.cacheOp.req.bits.write_tag_low, 252 setIdx = io.cacheOp.req.bits.index, 253 waymask = UIntToOH(io.cacheOp.req.bits.wayNum(4, 0)) 254 ) 255 } 256 cacheOpShouldResp := true.B 257 } 258 // TODO 259 // when(CacheInstrucion.isWriteTagECC(io.cacheOp.req.bits.opCode)){ 260 // for (i <- 0 until readPorts) { 261 // array(i).io.ecc_write.valid := true.B 262 // array(i).io.ecc_write.bits.idx := io.cacheOp.req.bits.index 263 // array(i).io.ecc_write.bits.way_en := UIntToOH(io.cacheOp.req.bits.wayNum(4, 0)) 264 // array(i).io.ecc_write.bits.ecc := io.cacheOp.req.bits.write_tag_ecc 265 // } 266 // cacheOpShouldResp := true.B 267 // } 268 } 269 io.cacheOp.resp.valid := RegNext(io.cacheOp.req.valid && cacheOpShouldResp) 270 io.cacheOp.resp.bits.read_tag_low := Mux(io.cacheOp.resp.valid, 271 tagArrays(0).io.r.resp.asTypeOf(Vec(nWays, UInt(tagBits.W)))(io.cacheOp.req.bits.wayNum), 272 0.U 273 ) 274 io.cacheOp.resp.bits.read_tag_ecc := DontCare // TODO 275 // TODO: deal with duplicated array 276} 277 278 279 280class ICacheDataArray(implicit p: Parameters) extends ICacheArray 281{ 282 283 def getECCFromEncUnit(encUnit: UInt) = { 284 require(encUnit.getWidth == encDataUnitBits) 285 if (encDataUnitBits == dataCodeUnit) { 286 0.U.asTypeOf(UInt(1.W)) 287 } else { 288 encUnit(encDataUnitBits - 1, dataCodeUnit) 289 } 290 } 291 292 def getECCFromBlock(cacheblock: UInt) = { 293 // require(cacheblock.getWidth == blockBits) 294 VecInit((0 until dataCodeUnitNum).map { w => 295 val unit = cacheblock(dataCodeUnit * (w + 1) - 1, dataCodeUnit * w) 296 getECCFromEncUnit(cacheParams.dataCode.encode(unit)) 297 }) 298 } 299 300 val io=IO{new Bundle{ 301 val write = Flipped(DecoupledIO(new ICacheDataWriteBundle)) 302 val read = Flipped(DecoupledIO(Vec(partWayNum, new ICacheReadBundle))) 303 val readResp = Output(new ICacheDataRespBundle) 304 val cacheOp = Flipped(new L1CacheInnerOpIO) // customized cache op port 305 }} 306 307 val write_data_bits = Wire(UInt(blockBits.W)) 308 309 val port_0_read_0_reg = RegEnable(next = io.read.valid && io.read.bits.head.port_0_read_0, enable = io.read.fire()) 310 val port_0_read_1_reg = RegEnable(next = io.read.valid && io.read.bits.head.port_0_read_1, enable = io.read.fire()) 311 val port_1_read_1_reg = RegEnable(next = io.read.valid && io.read.bits.head.port_1_read_1, enable = io.read.fire()) 312 val port_1_read_0_reg = RegEnable(next = io.read.valid && io.read.bits.head.port_1_read_0, enable = io.read.fire()) 313 314 val bank_0_idx_vec = io.read.bits.map(copy => Mux(io.read.valid && copy.port_0_read_0, copy.vSetIdx(0), copy.vSetIdx(1))) 315 val bank_1_idx_vec = io.read.bits.map(copy => Mux(io.read.valid && copy.port_0_read_1, copy.vSetIdx(0), copy.vSetIdx(1))) 316 317 val dataArrays = (0 until partWayNum).map{ i => 318 val dataArray = Module(new ICachePartWayArray( 319 UInt(blockBits.W), 320 pWay, 321 )) 322 323 dataArray.io.read.req(0).valid := io.read.bits(i).read_bank_0 && io.read.valid 324 dataArray.io.read.req(0).bits.ridx := bank_0_idx_vec(i)(highestIdxBit,1) 325 dataArray.io.read.req(1).valid := io.read.bits(i).read_bank_1 && io.read.valid 326 dataArray.io.read.req(1).bits.ridx := bank_1_idx_vec(i)(highestIdxBit,1) 327 328 329 dataArray.io.write.valid := io.write.valid 330 dataArray.io.write.bits.wdata := write_data_bits 331 dataArray.io.write.bits.widx := io.write.bits.virIdx(highestIdxBit,1) 332 dataArray.io.write.bits.wbankidx := io.write.bits.bankIdx 333 dataArray.io.write.bits.wmask := io.write.bits.waymask.asTypeOf(Vec(partWayNum, Vec(pWay, Bool())))(i) 334 335 dataArray 336 } 337 338 val read_datas = Wire(Vec(2,Vec(nWays,UInt(blockBits.W) ))) 339 340 (0 until PortNumber).map { port => 341 (0 until nWays).map { w => 342 read_datas(port)(w) := dataArrays(w / pWay).io.read.resp.rdata(port).asTypeOf(Vec(pWay, UInt(blockBits.W)))(w % pWay) 343 } 344 } 345 346 io.readResp.datas(0) := Mux( port_0_read_1_reg, read_datas(1) , read_datas(0)) 347 io.readResp.datas(1) := Mux( port_1_read_0_reg, read_datas(0) , read_datas(1)) 348 349 350 val write_data_code = Wire(UInt(dataCodeEntryBits.W)) 351 val write_bank_0 = WireInit(io.write.valid && !io.write.bits.bankIdx) 352 val write_bank_1 = WireInit(io.write.valid && io.write.bits.bankIdx) 353 354 val bank_0_idx = bank_0_idx_vec.last 355 val bank_1_idx = bank_1_idx_vec.last 356 357 val codeArrays = (0 until 2) map { i => 358 val codeArray = Module(new SRAMTemplate( 359 UInt(dataCodeEntryBits.W), 360 set=nSets/2, 361 way=nWays, 362 shouldReset = true, 363 holdRead = true, 364 singlePort = true 365 )) 366 367 if(i == 0) { 368 codeArray.io.r.req.valid := io.read.valid && io.read.bits.last.read_bank_0 369 codeArray.io.r.req.bits.apply(setIdx=bank_0_idx(highestIdxBit,1)) 370 codeArray.io.w.req.valid := write_bank_0 371 codeArray.io.w.req.bits.apply(data=write_data_code, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 372 } 373 else { 374 codeArray.io.r.req.valid := io.read.valid && io.read.bits.last.read_bank_1 375 codeArray.io.r.req.bits.apply(setIdx=bank_1_idx(highestIdxBit,1)) 376 codeArray.io.w.req.valid := write_bank_1 377 codeArray.io.w.req.bits.apply(data=write_data_code, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 378 } 379 380 codeArray 381 } 382 383 io.read.ready := !io.write.valid && 384 dataArrays.map(_.io.read.req.map(_.ready).reduce(_&&_)).reduce(_&&_) && 385 codeArrays.map(_.io.r.req.ready).reduce(_ && _) 386 387 //Parity Decode 388 val read_codes = Wire(Vec(2,Vec(nWays,UInt(dataCodeEntryBits.W) ))) 389 for(((dataArray,codeArray),i) <- dataArrays.zip(codeArrays).zipWithIndex){ 390 read_codes(i) := codeArray.io.r.resp.asTypeOf(Vec(nWays,UInt(dataCodeEntryBits.W))) 391 } 392 393 //Parity Encode 394 val write = io.write.bits 395 val write_data = WireInit(write.data) 396 write_data_code := getECCFromBlock(write_data).asUInt 397 write_data_bits := write_data 398 399 io.readResp.codes(0) := Mux( port_0_read_1_reg, read_codes(1) , read_codes(0)) 400 io.readResp.codes(1) := Mux( port_1_read_0_reg, read_codes(0) , read_codes(1)) 401 402 io.write.ready := true.B 403 404 // deal with customized cache op 405 require(nWays <= 32) 406 io.cacheOp.resp.bits := DontCare 407 io.cacheOp.resp.valid := false.B 408 val cacheOpShouldResp = WireInit(false.B) 409 val dataresp = Wire(Vec(nWays,UInt(blockBits.W) )) 410 dataresp := DontCare 411 when(io.cacheOp.req.valid){ 412 when( 413 CacheInstrucion.isReadData(io.cacheOp.req.bits.opCode) 414 ){ 415 for (i <- 0 until partWayNum) { 416 dataArrays(i).io.read.req.zipWithIndex.map{ case(port,i) => 417 if(i ==0) port.valid := !io.cacheOp.req.bits.bank_num(0) 418 else port.valid := io.cacheOp.req.bits.bank_num(0) 419 port.bits.ridx := io.cacheOp.req.bits.index(highestIdxBit,1) 420 } 421 } 422 cacheOpShouldResp := dataArrays.head.io.read.req.map(_.fire()).reduce(_||_) 423 dataresp :=Mux(io.cacheOp.req.bits.bank_num(0).asBool, read_datas(1), read_datas(0)) 424 } 425 when(CacheInstrucion.isWriteData(io.cacheOp.req.bits.opCode)){ 426 for (i <- 0 until partWayNum) { 427 dataArrays(i).io.write.valid := true.B 428 dataArrays(i).io.write.bits.wdata := io.cacheOp.req.bits.write_data_vec.asTypeOf(write_data.cloneType) 429 dataArrays(i).io.write.bits.wbankidx := io.cacheOp.req.bits.bank_num(0) 430 dataArrays(i).io.write.bits.widx := io.cacheOp.req.bits.index(highestIdxBit,1) 431 dataArrays(i).io.write.bits.wmask := UIntToOH(io.cacheOp.req.bits.wayNum(4, 0)).asTypeOf(Vec(partWayNum, Vec(pWay, Bool())))(i) 432 } 433 cacheOpShouldResp := true.B 434 } 435 } 436 437 io.cacheOp.resp.valid := RegNext(cacheOpShouldResp) 438 val numICacheLineWords = blockBits / 64 439 require(blockBits >= 64 && isPow2(blockBits)) 440 for (wordIndex <- 0 until numICacheLineWords) { 441 io.cacheOp.resp.bits.read_data_vec(wordIndex) := dataresp(io.cacheOp.req.bits.wayNum(4, 0))(64*(wordIndex+1)-1, 64*wordIndex) 442 } 443 444} 445 446 447class ICacheIO(implicit p: Parameters) extends ICacheBundle 448{ 449 val hartId = Input(UInt(8.W)) 450 val prefetch = Flipped(new FtqPrefechBundle) 451 val stop = Input(Bool()) 452 val fetch = new ICacheMainPipeBundle 453 val toIFU = Output(Bool()) 454 val pmp = Vec(PortNumber + 1, new ICachePMPBundle) 455 val itlb = Vec(PortNumber + 1, new TlbRequestIO) 456 val perfInfo = Output(new ICachePerfInfo) 457 val error = new L1CacheErrorInfo 458 /* Cache Instruction */ 459 val csr = new L1CacheToCsrIO 460 /* CSR control signal */ 461 val csr_pf_enable = Input(Bool()) 462 val csr_parity_enable = Input(Bool()) 463} 464 465class ICache()(implicit p: Parameters) extends LazyModule with HasICacheParameters { 466 467 val clientParameters = TLMasterPortParameters.v1( 468 Seq(TLMasterParameters.v1( 469 name = "icache", 470 sourceId = IdRange(0, cacheParams.nMissEntries + cacheParams.nReleaseEntries), 471 supportsProbe = TransferSizes(blockBytes), 472 supportsHint = TransferSizes(blockBytes) 473 )), 474 requestFields = cacheParams.reqFields, 475 echoFields = cacheParams.echoFields 476 ) 477 478 val clientNode = TLClientNode(Seq(clientParameters)) 479 480 lazy val module = new ICacheImp(this) 481} 482 483class ICacheImp(outer: ICache) extends LazyModuleImp(outer) with HasICacheParameters with HasPerfEvents { 484 val io = IO(new ICacheIO) 485 486 println("ICache:") 487 println(" ICacheSets: " + cacheParams.nSets) 488 println(" ICacheWays: " + cacheParams.nWays) 489 println(" ICacheBanks: " + PortNumber) 490 println(" hasPrefetch: " + cacheParams.hasPrefetch) 491 if(cacheParams.hasPrefetch){ 492 println(" nPrefetchEntries: " + cacheParams.nPrefetchEntries) 493 } 494 495 val (bus, edge) = outer.clientNode.out.head 496 497 val metaArray = Module(new ICacheMetaArray) 498 val dataArray = Module(new ICacheDataArray) 499 val mainPipe = Module(new ICacheMainPipe) 500 val missUnit = Module(new ICacheMissUnit(edge)) 501 val releaseUnit = Module(new ReleaseUnit(edge)) 502 val replacePipe = Module(new ICacheReplacePipe) 503 val probeQueue = Module(new ICacheProbeQueue(edge)) 504 val prefetchPipe = Module(new IPrefetchPipe) 505 506 val meta_read_arb = Module(new Arbiter(new ICacheReadBundle, 3)) 507 val data_read_arb = Module(new Arbiter(Vec(partWayNum, new ICacheReadBundle), 2)) 508 val meta_write_arb = Module(new Arbiter(new ICacheMetaWriteBundle(), 2 )) 509 val replace_req_arb = Module(new Arbiter(new ReplacePipeReq, 2)) 510 // val tlb_req_arb = Module(new Arbiter(new TlbReq, 2)) 511 512 meta_read_arb.io.in(ReplacePipeKey) <> replacePipe.io.meta_read 513 meta_read_arb.io.in(MainPipeKey) <> mainPipe.io.metaArray.toIMeta 514 meta_read_arb.io.in(2) <> prefetchPipe.io.toIMeta 515 metaArray.io.read <> meta_read_arb.io.out 516 517 replacePipe.io.meta_response <> metaArray.io.readResp 518 mainPipe.io.metaArray.fromIMeta <> metaArray.io.readResp 519 prefetchPipe.io.fromIMeta <> metaArray.io.readResp 520 521 data_read_arb.io.in(ReplacePipeKey) <> replacePipe.io.data_read 522 data_read_arb.io.in(MainPipeKey) <> mainPipe.io.dataArray.toIData 523 dataArray.io.read <> data_read_arb.io.out 524 replacePipe.io.data_response <> dataArray.io.readResp 525 mainPipe.io.dataArray.fromIData <> dataArray.io.readResp 526 527 mainPipe.io.respStall := io.stop 528 io.perfInfo := mainPipe.io.perfInfo 529 530 meta_write_arb.io.in(ReplacePipeKey) <> replacePipe.io.meta_write 531 meta_write_arb.io.in(MainPipeKey) <> missUnit.io.meta_write 532 533 //metaArray.io.write <> meta_write_arb.io.out 534 //dataArray.io.write <> missUnit.io.data_write 535 536 metaArray.io.write.valid := RegNext(meta_write_arb.io.out.valid,init =false.B) 537 metaArray.io.write.bits := RegNext(meta_write_arb.io.out.bits) 538 meta_write_arb.io.out.ready := true.B 539 540 dataArray.io.write.valid := RegNext(missUnit.io.data_write.valid,init =false.B) 541 dataArray.io.write.bits := RegNext(missUnit.io.data_write.bits) 542 missUnit.io.data_write.ready := true.B 543 544 mainPipe.io.csr_parity_enable := io.csr_parity_enable 545 replacePipe.io.csr_parity_enable := io.csr_parity_enable 546 547 if(cacheParams.hasPrefetch){ 548 prefetchPipe.io.fromFtq <> io.prefetch 549 when(!io.csr_pf_enable){ 550 prefetchPipe.io.fromFtq.req.valid := false.B 551 io.prefetch.req.ready := true.B 552 } 553 } else { 554 prefetchPipe.io.fromFtq <> DontCare 555 } 556 557 io.pmp(0) <> mainPipe.io.pmp(0) 558 io.pmp(1) <> mainPipe.io.pmp(1) 559 io.pmp(2) <> prefetchPipe.io.pmp 560 561 prefetchPipe.io.prefetchEnable := mainPipe.io.prefetchEnable 562 prefetchPipe.io.prefetchDisable := mainPipe.io.prefetchDisable 563 564 //notify IFU that Icache pipeline is available 565 io.toIFU := mainPipe.io.fetch.req.ready 566 567 // tlb_req_arb.io.in(0) <> mainPipe.io.itlb(0).req 568 // tlb_req_arb.io.in(1) <> prefetchPipe.io.iTLBInter.req 569 // io.itlb(0).req <> tlb_req_arb.io.out 570 571 // mainPipe.io.itlb(0).resp <> io.itlb(0).resp 572 // prefetchPipe.io.iTLBInter.resp <> io.itlb(0).resp 573 574 // when(mainPipe.io.itlb(0).req.fire() && prefetchPipe.io.iTLBInter.req.fire()) 575 // { 576 // assert(false.B, "Both mainPipe ITLB and prefetchPipe ITLB fire!") 577 // } 578 579 io.itlb(0) <> mainPipe.io.itlb(0) 580 io.itlb(1) <> mainPipe.io.itlb(1) 581 // io.itlb(2) <> mainPipe.io.itlb(2) 582 // io.itlb(3) <> mainPipe.io.itlb(3) 583 io.itlb(2) <> prefetchPipe.io.iTLBInter 584 585 586 io.fetch.resp <> mainPipe.io.fetch.resp 587 588 for(i <- 0 until PortNumber){ 589 missUnit.io.req(i) <> mainPipe.io.mshr(i).toMSHR 590 mainPipe.io.mshr(i).fromMSHR <> missUnit.io.resp(i) 591 } 592 593 missUnit.io.prefetch_req <> prefetchPipe.io.toMissUnit.enqReq 594 missUnit.io.hartId := io.hartId 595 prefetchPipe.io.fromMSHR <> missUnit.io.prefetch_check 596 597 bus.b.ready := false.B 598 bus.c.valid := false.B 599 bus.c.bits := DontCare 600 bus.e.valid := false.B 601 bus.e.bits := DontCare 602 603 bus.a <> missUnit.io.mem_acquire 604 bus.e <> missUnit.io.mem_finish 605 606 releaseUnit.io.req <> replacePipe.io.release_req 607 replacePipe.io.release_finish := releaseUnit.io.finish 608 bus.c <> releaseUnit.io.mem_release 609 610 // connect bus d 611 missUnit.io.mem_grant.valid := false.B 612 missUnit.io.mem_grant.bits := DontCare 613 614 releaseUnit.io.mem_grant.valid := false.B 615 releaseUnit.io.mem_grant.bits := DontCare 616 617 //Probe through bus b 618 probeQueue.io.mem_probe <> bus.b 619 620 //Parity error port 621 val errors = mainPipe.io.errors ++ Seq(replacePipe.io.error) 622 io.error <> RegNext(Mux1H(errors.map(e => e.valid -> e))) 623 624 625 /** Block set-conflict request */ 626 val probeReqValid = probeQueue.io.pipe_req.valid 627 val probeReqVidx = probeQueue.io.pipe_req.bits.vidx 628 629 val hasVictim = VecInit(missUnit.io.victimInfor.map(_.valid)) 630 val victimSetSeq = VecInit(missUnit.io.victimInfor.map(_.vidx)) 631 632 val probeShouldBlock = VecInit(hasVictim.zip(victimSetSeq).map{case(valid, idx) => valid && probeReqValid && idx === probeReqVidx }).reduce(_||_) 633 634 val releaseReqValid = missUnit.io.release_req.valid 635 val releaseReqVidx = missUnit.io.release_req.bits.vidx 636 637 val hasConflict = VecInit(Seq( 638 replacePipe.io.status.r0_set.valid, 639 replacePipe.io.status.r1_set.valid, 640 replacePipe.io.status.r2_set.valid, 641 replacePipe.io.status.r3_set.valid 642 )) 643 644 val conflictIdx = VecInit(Seq( 645 replacePipe.io.status.r0_set.bits, 646 replacePipe.io.status.r1_set.bits, 647 replacePipe.io.status.r2_set.bits, 648 replacePipe.io.status.r3_set.bits 649 )) 650 651 val releaseShouldBlock = VecInit(hasConflict.zip(conflictIdx).map{case(valid, idx) => valid && releaseReqValid && idx === releaseReqVidx }).reduce(_||_) 652 653 replace_req_arb.io.in(ReplacePipeKey) <> probeQueue.io.pipe_req 654 replace_req_arb.io.in(ReplacePipeKey).valid := probeQueue.io.pipe_req.valid && !probeShouldBlock 655 replace_req_arb.io.in(MainPipeKey) <> missUnit.io.release_req 656 replace_req_arb.io.in(MainPipeKey).valid := missUnit.io.release_req.valid && !releaseShouldBlock 657 replacePipe.io.pipe_req <> replace_req_arb.io.out 658 659 when(releaseShouldBlock){ 660 missUnit.io.release_req.ready := false.B 661 } 662 663 when(probeShouldBlock){ 664 probeQueue.io.pipe_req.ready := false.B 665 } 666 667 668 missUnit.io.release_resp <> replacePipe.io.pipe_resp 669 670 671 mainPipe.io.fetch.req <> io.fetch.req //&& !fetchShouldBlock(i) 672 // in L1ICache, we only expect GrantData and ReleaseAck 673 bus.d.ready := false.B 674 when ( bus.d.bits.opcode === TLMessages.GrantData) { 675 missUnit.io.mem_grant <> bus.d 676 } .elsewhen (bus.d.bits.opcode === TLMessages.ReleaseAck) { 677 releaseUnit.io.mem_grant <> bus.d 678 } .otherwise { 679 assert (!bus.d.fire()) 680 } 681 682 val perfEvents = Seq( 683 ("icache_miss_cnt ", false.B), 684 ("icache_miss_penty", BoolStopWatch(start = false.B, stop = false.B || false.B, startHighPriority = true)), 685 ) 686 generatePerfEvent() 687 688 // Customized csr cache op support 689 val cacheOpDecoder = Module(new CSRCacheOpDecoder("icache", CacheInstrucion.COP_ID_ICACHE)) 690 cacheOpDecoder.io.csr <> io.csr 691 dataArray.io.cacheOp.req := cacheOpDecoder.io.cache.req 692 metaArray.io.cacheOp.req := cacheOpDecoder.io.cache.req 693 cacheOpDecoder.io.cache.resp.valid := 694 dataArray.io.cacheOp.resp.valid || 695 metaArray.io.cacheOp.resp.valid 696 cacheOpDecoder.io.cache.resp.bits := Mux1H(List( 697 dataArray.io.cacheOp.resp.valid -> dataArray.io.cacheOp.resp.bits, 698 metaArray.io.cacheOp.resp.valid -> metaArray.io.cacheOp.resp.bits, 699 )) 700 cacheOpDecoder.io.error := io.error 701 assert(!((dataArray.io.cacheOp.resp.valid +& metaArray.io.cacheOp.resp.valid) > 1.U)) 702 703} 704 705class ICachePartWayReadBundle[T <: Data](gen: T, pWay: Int)(implicit p: Parameters) 706 extends ICacheBundle 707{ 708 val req = Flipped(Vec(PortNumber, Decoupled(new Bundle{ 709 val ridx = UInt((log2Ceil(nSets) - 1).W) 710 }))) 711 val resp = Output(new Bundle{ 712 val rdata = Vec(PortNumber,Vec(pWay, gen)) 713 }) 714} 715 716class ICacheWriteBundle[T <: Data](gen: T, pWay: Int)(implicit p: Parameters) 717 extends ICacheBundle 718{ 719 val wdata = gen 720 val widx = UInt((log2Ceil(nSets) - 1).W) 721 val wbankidx = Bool() 722 val wmask = Vec(pWay, Bool()) 723} 724 725class ICachePartWayArray[T <: Data](gen: T, pWay: Int)(implicit p: Parameters) extends ICacheArray 726{ 727 728 //including part way data 729 val io = IO{new Bundle { 730 val read = new ICachePartWayReadBundle(gen,pWay) 731 val write = Flipped(ValidIO(new ICacheWriteBundle(gen, pWay))) 732 }} 733 734 io.read.req.map(_.ready := !io.write.valid) 735 736 val srams = (0 until PortNumber) map { bank => 737 val sramBank = Module(new SRAMTemplate( 738 gen, 739 set=nSets/2, 740 way=pWay, 741 shouldReset = true, 742 holdRead = true, 743 singlePort = true 744 )) 745 746 sramBank.io.r.req.valid := io.read.req(bank).valid 747 sramBank.io.r.req.bits.apply(setIdx= io.read.req(bank).bits.ridx) 748 749 if(bank == 0) sramBank.io.w.req.valid := io.write.valid && !io.write.bits.wbankidx 750 else sramBank.io.w.req.valid := io.write.valid && io.write.bits.wbankidx 751 sramBank.io.w.req.bits.apply(data=io.write.bits.wdata, setIdx=io.write.bits.widx, waymask=io.write.bits.wmask.asUInt()) 752 753 sramBank 754 } 755 756 io.read.req.map(_.ready := !io.write.valid && srams.map(_.io.r.req.ready).reduce(_&&_)) 757 758 io.read.resp.rdata := VecInit(srams.map(bank => bank.io.r.resp.asTypeOf(Vec(pWay,gen)))) 759 760} 761