1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend.icache 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp, TransferSizes} 23import freechips.rocketchip.tilelink._ 24import freechips.rocketchip.util.BundleFieldBase 25import huancun.{AliasField, DirtyField, PreferCacheField, PrefetchField} 26import xiangshan._ 27import xiangshan.frontend._ 28import xiangshan.cache._ 29import utils._ 30import xiangshan.backend.fu.PMPReqBundle 31import xiangshan.cache.mmu.{BlockTlbRequestIO, TlbReq} 32 33case class ICacheParameters( 34 nSets: Int = 256, 35 nWays: Int = 8, 36 rowBits: Int = 64, 37 nTLBEntries: Int = 32, 38 tagECC: Option[String] = None, 39 dataECC: Option[String] = None, 40 replacer: Option[String] = Some("random"), 41 nMissEntries: Int = 2, 42 nReleaseEntries: Int = 1, 43 nProbeEntries: Int = 2, 44 nPrefetchEntries: Int = 4, 45 hasPrefetch: Boolean = false, 46 nMMIOs: Int = 1, 47 blockBytes: Int = 64 48)extends L1CacheParameters { 49 50 val setBytes = nSets * blockBytes 51 val aliasBitsOpt = if(setBytes > pageSize) Some(log2Ceil(setBytes / pageSize)) else None 52 val reqFields: Seq[BundleFieldBase] = Seq( 53 PrefetchField(), 54 PreferCacheField() 55 ) ++ aliasBitsOpt.map(AliasField) 56 val echoFields: Seq[BundleFieldBase] = Seq(DirtyField()) 57 def tagCode: Code = Code.fromString(tagECC) 58 def dataCode: Code = Code.fromString(dataECC) 59 def replacement = ReplacementPolicy.fromString(replacer,nWays,nSets) 60} 61 62trait HasICacheParameters extends HasL1CacheParameters with HasInstrMMIOConst with HasIFUConst{ 63 val cacheParams = icacheParameters 64 val dataCodeUnit = 16 65 val dataCodeUnitNum = blockBits/dataCodeUnit 66 67 def highestIdxBit = log2Ceil(nSets) - 1 68 def encDataUnitBits = cacheParams.dataCode.width(dataCodeUnit) 69 def dataCodeBits = encDataUnitBits - dataCodeUnit 70 def dataCodeEntryBits = dataCodeBits * dataCodeUnitNum 71 72 val ICacheSets = cacheParams.nSets 73 val ICacheWays = cacheParams.nWays 74 75 val ICacheSameVPAddrLength = 12 76 val ReplaceIdWid = 5 77 78 val ICacheWordOffset = 0 79 val ICacheSetOffset = ICacheWordOffset + log2Up(blockBytes) 80 val ICacheAboveIndexOffset = ICacheSetOffset + log2Up(ICacheSets) 81 val ICacheTagOffset = ICacheAboveIndexOffset min ICacheSameVPAddrLength 82 83 def ReplacePipeKey = 0 84 def MainPipeKey = 1 85 def PortNumber = 2 86 def ProbeKey = 3 87 88 def nPrefetchEntries = cacheParams.nPrefetchEntries 89 90 def generatePipeControl(lastFire: Bool, thisFire: Bool, thisFlush: Bool, lastFlush: Bool): Bool = { 91 val valid = RegInit(false.B) 92 when(thisFlush) {valid := false.B} 93 .elsewhen(lastFire && !lastFlush) {valid := true.B} 94 .elsewhen(thisFire) {valid := false.B} 95 valid 96 } 97 98 def ResultHoldBypass[T<:Data](data: T, valid: Bool): T = { 99 Mux(valid, data, RegEnable(data, valid)) 100 } 101 102 require(isPow2(nSets), s"nSets($nSets) must be pow2") 103 require(isPow2(nWays), s"nWays($nWays) must be pow2") 104} 105 106abstract class ICacheBundle(implicit p: Parameters) extends XSBundle 107 with HasICacheParameters 108 109abstract class ICacheModule(implicit p: Parameters) extends XSModule 110 with HasICacheParameters 111 112abstract class ICacheArray(implicit p: Parameters) extends XSModule 113 with HasICacheParameters 114 115class ICacheMetadata(implicit p: Parameters) extends ICacheBundle { 116 val coh = new ClientMetadata 117 val tag = UInt(tagBits.W) 118} 119 120object ICacheMetadata { 121 def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = { 122 val meta = Wire(new L1Metadata) 123 meta.tag := tag 124 meta.coh := coh 125 meta 126 } 127} 128 129 130class ICacheMetaArray()(implicit p: Parameters) extends ICacheArray 131{ 132 def onReset = ICacheMetadata(0.U, ClientMetadata.onReset) 133 val metaBits = onReset.getWidth 134 val metaEntryBits = cacheParams.tagCode.width(metaBits) 135 136 val io=IO{new Bundle{ 137 val write = Flipped(DecoupledIO(new ICacheMetaWriteBundle)) 138 val read = Flipped(DecoupledIO(new ICacheReadBundle)) 139 val readResp = Output(new ICacheMetaRespBundle) 140 val cacheOp = Flipped(new L1CacheInnerOpIO) // customized cache op port 141 }} 142 143 io.read.ready := !io.write.valid 144 145 val port_0_read_0 = io.read.valid && !io.read.bits.vSetIdx(0)(0) 146 val port_0_read_1 = io.read.valid && io.read.bits.vSetIdx(0)(0) 147 val port_1_read_1 = io.read.valid && io.read.bits.vSetIdx(1)(0) && io.read.bits.isDoubleLine 148 val port_1_read_0 = io.read.valid && !io.read.bits.vSetIdx(1)(0) && io.read.bits.isDoubleLine 149 150 val port_0_read_0_reg = RegEnable(port_0_read_0, io.read.fire()) 151 val port_0_read_1_reg = RegEnable(port_0_read_1, io.read.fire()) 152 val port_1_read_1_reg = RegEnable(port_1_read_1, io.read.fire()) 153 val port_1_read_0_reg = RegEnable(port_1_read_0, io.read.fire()) 154 155 val bank_0_idx = Mux(port_0_read_0, io.read.bits.vSetIdx(0), io.read.bits.vSetIdx(1)) 156 val bank_1_idx = Mux(port_0_read_1, io.read.bits.vSetIdx(0), io.read.bits.vSetIdx(1)) 157 val bank_idx = Seq(bank_0_idx, bank_1_idx) 158 159 val write_bank_0 = io.write.valid && !io.write.bits.bankIdx 160 val write_bank_1 = io.write.valid && io.write.bits.bankIdx 161 162 val write_meta_bits = Wire(UInt(metaEntryBits.W)) 163 164 val tagArrays = (0 until 2) map { bank => 165 val tagArray = Module(new SRAMTemplate( 166 UInt(metaEntryBits.W), 167 set=nSets/2, 168 way=nWays, 169 shouldReset = true, 170 holdRead = true, 171 singlePort = true 172 )) 173 174 //meta connection 175 if(bank == 0) { 176 tagArray.io.r.req.valid := port_0_read_0 || port_1_read_0 177 tagArray.io.r.req.bits.apply(setIdx=bank_0_idx(highestIdxBit,1)) 178 tagArray.io.w.req.valid := write_bank_0 179 tagArray.io.w.req.bits.apply(data=write_meta_bits, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 180 } 181 else { 182 tagArray.io.r.req.valid := port_0_read_1 || port_1_read_1 183 tagArray.io.r.req.bits.apply(setIdx=bank_1_idx(highestIdxBit,1)) 184 tagArray.io.w.req.valid := write_bank_1 185 tagArray.io.w.req.bits.apply(data=write_meta_bits, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 186 } 187 188 tagArray 189 } 190 191 io.read.ready := !io.write.valid && tagArrays.map(_.io.r.req.ready).reduce(_&&_) 192 193 //Parity Decode 194 val read_metas = Wire(Vec(2,Vec(nWays,new ICacheMetadata()))) 195 for((tagArray,i) <- tagArrays.zipWithIndex){ 196 val read_meta_bits = tagArray.io.r.resp.asTypeOf(Vec(nWays,UInt(metaEntryBits.W))) 197 val read_meta_decoded = read_meta_bits.map{ way_bits => cacheParams.tagCode.decode(way_bits)} 198 val read_meta_wrong = read_meta_decoded.map{ way_bits_decoded => way_bits_decoded.error} 199 val read_meta_corrected = VecInit(read_meta_decoded.map{ way_bits_decoded => way_bits_decoded.corrected}) 200 read_metas(i) := read_meta_corrected.asTypeOf(Vec(nWays,new ICacheMetadata())) 201 (0 until nWays).map{ w => io.readResp.errors(i)(w) := RegNext(read_meta_wrong(w)) && RegNext(RegNext(io.read.fire))} 202 } 203 204 //Parity Encode 205 val write = io.write.bits 206 write_meta_bits := cacheParams.tagCode.encode(ICacheMetadata(tag = write.phyTag, coh = write.coh).asUInt) 207 208 val wayNum = OHToUInt(io.write.bits.waymask) 209 val validPtr = Cat(io.write.bits.virIdx, wayNum) 210 211 io.readResp.metaData <> DontCare 212 when(port_0_read_0_reg){ 213 io.readResp.metaData(0) := read_metas(0) 214 }.elsewhen(port_0_read_1_reg){ 215 io.readResp.metaData(0) := read_metas(1) 216 } 217 218 when(port_1_read_0_reg){ 219 io.readResp.metaData(1) := read_metas(0) 220 }.elsewhen(port_1_read_1_reg){ 221 io.readResp.metaData(1) := read_metas(1) 222 } 223 224 225 io.write.ready := true.B 226 // deal with customized cache op 227 require(nWays <= 32) 228 io.cacheOp.resp.bits := DontCare 229 val cacheOpShouldResp = WireInit(false.B) 230 when(io.cacheOp.req.valid){ 231 when( 232 CacheInstrucion.isReadTag(io.cacheOp.req.bits.opCode) || 233 CacheInstrucion.isReadTagECC(io.cacheOp.req.bits.opCode) 234 ){ 235 for (i <- 0 until 2) { 236 tagArrays(i).io.r.req.valid := true.B 237 tagArrays(i).io.r.req.bits.apply(setIdx = io.cacheOp.req.bits.index) 238 } 239 cacheOpShouldResp := true.B 240 } 241 when(CacheInstrucion.isWriteTag(io.cacheOp.req.bits.opCode)){ 242 for (i <- 0 until 2) { 243 tagArrays(i).io.w.req.valid := true.B 244 tagArrays(i).io.w.req.bits.apply( 245 data = io.cacheOp.req.bits.write_tag_low, 246 setIdx = io.cacheOp.req.bits.index, 247 waymask = UIntToOH(io.cacheOp.req.bits.wayNum(4, 0)) 248 ) 249 } 250 cacheOpShouldResp := true.B 251 } 252 // TODO 253 // when(CacheInstrucion.isWriteTagECC(io.cacheOp.req.bits.opCode)){ 254 // for (i <- 0 until readPorts) { 255 // array(i).io.ecc_write.valid := true.B 256 // array(i).io.ecc_write.bits.idx := io.cacheOp.req.bits.index 257 // array(i).io.ecc_write.bits.way_en := UIntToOH(io.cacheOp.req.bits.wayNum(4, 0)) 258 // array(i).io.ecc_write.bits.ecc := io.cacheOp.req.bits.write_tag_ecc 259 // } 260 // cacheOpShouldResp := true.B 261 // } 262 } 263 io.cacheOp.resp.valid := RegNext(io.cacheOp.req.valid && cacheOpShouldResp) 264 io.cacheOp.resp.bits.read_tag_low := Mux(io.cacheOp.resp.valid, 265 tagArrays(0).io.r.resp.asTypeOf(Vec(nWays, UInt(tagBits.W)))(io.cacheOp.req.bits.wayNum), 266 0.U 267 ) 268 io.cacheOp.resp.bits.read_tag_ecc := DontCare // TODO 269 // TODO: deal with duplicated array 270} 271 272 273class ICacheDataArray(implicit p: Parameters) extends ICacheArray 274{ 275 276 def getECCFromEncUnit(encUnit: UInt) = { 277 require(encUnit.getWidth == encDataUnitBits) 278 if (encDataUnitBits == dataCodeUnit) { 279 0.U.asTypeOf(UInt(1.W)) 280 } else { 281 encUnit(encDataUnitBits - 1, dataCodeUnit) 282 } 283 } 284 285 def getECCFromBlock(cacheblock: UInt) = { 286 // require(cacheblock.getWidth == blockBits) 287 VecInit((0 until dataCodeUnitNum).map { w => 288 val unit = cacheblock(dataCodeUnit * (w + 1) - 1, dataCodeUnit * w) 289 getECCFromEncUnit(cacheParams.dataCode.encode(unit)) 290 }) 291 } 292 293 val io=IO{new Bundle{ 294 val write = Flipped(DecoupledIO(new ICacheDataWriteBundle)) 295 val read = Flipped(DecoupledIO(new ICacheReadBundle)) 296 val readResp = Output(new ICacheDataRespBundle) 297 val cacheOp = Flipped(new L1CacheInnerOpIO) // customized cache op port 298 }} 299 300 val port_0_read_0 = io.read.valid && !io.read.bits.vSetIdx(0)(0) 301 val port_0_read_1 = io.read.valid && io.read.bits.vSetIdx(0)(0) 302 val port_1_read_1 = io.read.valid && io.read.bits.vSetIdx(1)(0) && io.read.bits.isDoubleLine 303 val port_1_read_0 = io.read.valid && !io.read.bits.vSetIdx(1)(0) && io.read.bits.isDoubleLine 304 305 val port_0_read_1_reg = RegEnable(port_0_read_1, io.read.fire()) 306 val port_1_read_0_reg = RegEnable(port_1_read_0, io.read.fire()) 307 308 val bank_0_idx = Mux(port_0_read_0, io.read.bits.vSetIdx(0), io.read.bits.vSetIdx(1)) 309 val bank_1_idx = Mux(port_0_read_1, io.read.bits.vSetIdx(0), io.read.bits.vSetIdx(1)) 310 val bank_idx = Seq(bank_0_idx, bank_1_idx) 311 312 val write_bank_0 = WireInit(io.write.valid && !io.write.bits.bankIdx) 313 val write_bank_1 = WireInit(io.write.valid && io.write.bits.bankIdx) 314 315 val write_data_bits = Wire(UInt(blockBits.W)) 316 val write_data_code = Wire(UInt(dataCodeEntryBits.W)) 317 318 val dataArrays = (0 until 2) map { i => 319 val dataArray = Module(new SRAMTemplate( 320 UInt(blockBits.W), 321 set=nSets/2, 322 way=nWays, 323 shouldReset = true, 324 holdRead = true, 325 singlePort = true 326 )) 327 328 if(i == 0) { 329 dataArray.io.r.req.valid := port_0_read_0 || port_1_read_0 330 dataArray.io.r.req.bits.apply(setIdx=bank_0_idx(highestIdxBit,1)) 331 dataArray.io.w.req.valid := write_bank_0 332 dataArray.io.w.req.bits.apply(data=write_data_bits, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 333 } 334 else { 335 dataArray.io.r.req.valid := port_0_read_1 || port_1_read_1 336 dataArray.io.r.req.bits.apply(setIdx=bank_1_idx(highestIdxBit,1)) 337 dataArray.io.w.req.valid := write_bank_1 338 dataArray.io.w.req.bits.apply(data=write_data_bits, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 339 } 340 341 dataArray 342 } 343 344 val codeArrays = (0 until 2) map { i => 345 val codeArray = Module(new SRAMTemplate( 346 UInt(dataCodeEntryBits.W), 347 set=nSets/2, 348 way=nWays, 349 shouldReset = true, 350 holdRead = true, 351 singlePort = true 352 )) 353 354 if(i == 0) { 355 codeArray.io.r.req.valid := port_0_read_0 || port_1_read_0 356 codeArray.io.r.req.bits.apply(setIdx=bank_0_idx(highestIdxBit,1)) 357 codeArray.io.w.req.valid := write_bank_0 358 codeArray.io.w.req.bits.apply(data=write_data_code, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 359 } 360 else { 361 codeArray.io.r.req.valid := port_0_read_1 || port_1_read_1 362 codeArray.io.r.req.bits.apply(setIdx=bank_1_idx(highestIdxBit,1)) 363 codeArray.io.w.req.valid := write_bank_1 364 codeArray.io.w.req.bits.apply(data=write_data_code, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 365 } 366 367 codeArray 368 } 369 370 io.read.ready := !io.write.valid && dataArrays.map(_.io.r.req.ready).reduce(_ && _) && codeArrays.map(_.io.r.req.ready).reduce(_ && _) 371 372 //Parity Decode 373 val read_datas = Wire(Vec(2,Vec(nWays,UInt(blockBits.W) ))) 374 val read_codes = Wire(Vec(2,Vec(nWays,UInt(dataCodeEntryBits.W) ))) 375 for(((dataArray,codeArray),i) <- dataArrays.zip(codeArrays).zipWithIndex){ 376 read_datas(i) := dataArray.io.r.resp.asTypeOf(Vec(nWays,UInt(blockBits.W))) 377 read_codes(i) := codeArray.io.r.resp.asTypeOf(Vec(nWays,UInt(dataCodeEntryBits.W))) 378 } 379 380 381 //Parity Encode 382 val write = io.write.bits 383 val write_data = WireInit(write.data) 384 write_data_code := getECCFromBlock(write_data).asUInt 385 write_data_bits := write_data 386 387 io.readResp.datas(0) := Mux( port_0_read_1_reg, read_datas(1) , read_datas(0)) 388 io.readResp.datas(1) := Mux( port_1_read_0_reg, read_datas(0) , read_datas(1)) 389 io.readResp.codes(0) := Mux( port_0_read_1_reg, read_codes(1) , read_codes(0)) 390 io.readResp.codes(1) := Mux( port_1_read_0_reg, read_codes(0) , read_codes(1)) 391 392 io.write.ready := true.B 393 394 // deal with customized cache op 395 require(nWays <= 32) 396 io.cacheOp.resp.bits := DontCare 397 val cacheOpShouldResp = WireInit(false.B) 398 when(io.cacheOp.req.valid){ 399 when( 400 CacheInstrucion.isReadData(io.cacheOp.req.bits.opCode) || 401 CacheInstrucion.isReadDataECC(io.cacheOp.req.bits.opCode) 402 ){ 403 (0 until 2).map(i => { 404 dataArrays(i).io.r.req.valid := true.B 405 dataArrays(i).io.r.req.bits.apply(setIdx = io.cacheOp.req.bits.index) 406 }) 407 cacheOpShouldResp := true.B 408 } 409 when(CacheInstrucion.isWriteData(io.cacheOp.req.bits.opCode)){ 410 (0 until 2).map(i => { 411 dataArrays(i).io.w.req.valid := io.cacheOp.req.bits.bank_num === i.U 412 dataArrays(i).io.w.req.bits.setIdx := io.cacheOp.req.bits.index 413 dataArrays(i).io.w.req.bits.waymask match { 414 case Some(waymask) => waymask := UIntToOH(io.cacheOp.req.bits.wayNum(4, 0)) 415 case None => 416 } 417 }) 418 write_data := io.cacheOp.req.bits.write_data_vec.asTypeOf(write_data.cloneType) 419 cacheOpShouldResp := true.B 420 } 421 } 422 io.cacheOp.resp.valid := RegNext(io.cacheOp.req.valid && cacheOpShouldResp) 423 val dataresp = Mux(io.cacheOp.req.bits.bank_num(0).asBool, 424 read_datas(1), 425 read_datas(0) 426 ) 427 428 val numICacheLineWords = blockBits / 64 429 require(blockBits >= 64 && isPow2(blockBits)) 430 for (wordIndex <- 0 until numICacheLineWords) { 431 io.cacheOp.resp.bits.read_data_vec(wordIndex) := dataresp(io.cacheOp.req.bits.wayNum(4, 0))(64*(wordIndex+1)-1, 64*wordIndex) 432 } 433 // io.cacheOp.resp.bits.read_data_ecc := Mux(io.cacheOp.resp.valid, 434 // bank_result(io.cacheOp.req.bits.bank_num).ecc, 435 // 0.U 436 // ) 437} 438 439 440class ICacheIO(implicit p: Parameters) extends ICacheBundle 441{ 442 val hartId = Input(UInt(8.W)) 443 val prefetch = Flipped(new FtqPrefechBundle) 444 val stop = Input(Bool()) 445 val fetch = Vec(PortNumber, new ICacheMainPipeBundle) 446 val pmp = Vec(PortNumber + 1, new ICachePMPBundle) 447 val itlb = Vec(PortNumber * 2 + 1, new BlockTlbRequestIO) 448 val perfInfo = Output(new ICachePerfInfo) 449 val error = new L1CacheErrorInfo 450 /* Cache Instruction */ 451 val csr = new L1CacheToCsrIO 452 /* CSR control signal */ 453 val csr_pf_enable = Input(Bool()) 454 val csr_parity_enable = Input(Bool()) 455} 456 457class ICache()(implicit p: Parameters) extends LazyModule with HasICacheParameters { 458 459 val clientParameters = TLMasterPortParameters.v1( 460 Seq(TLMasterParameters.v1( 461 name = "icache", 462 sourceId = IdRange(0, cacheParams.nMissEntries + cacheParams.nReleaseEntries), 463 supportsProbe = TransferSizes(blockBytes), 464 supportsHint = TransferSizes(blockBytes) 465 )), 466 requestFields = cacheParams.reqFields, 467 echoFields = cacheParams.echoFields 468 ) 469 470 val clientNode = TLClientNode(Seq(clientParameters)) 471 472 lazy val module = new ICacheImp(this) 473} 474 475class ICacheImp(outer: ICache) extends LazyModuleImp(outer) with HasICacheParameters with HasPerfEvents { 476 val io = IO(new ICacheIO) 477 478 println("ICache:") 479 println(" ICacheSets: " + cacheParams.nSets) 480 println(" ICacheWays: " + cacheParams.nWays) 481 println(" ICacheBanks: " + PortNumber) 482 println(" hasPrefetch: " + cacheParams.hasPrefetch) 483 if(cacheParams.hasPrefetch){ 484 println(" nPrefetchEntries: " + cacheParams.nPrefetchEntries) 485 } 486 487 val (bus, edge) = outer.clientNode.out.head 488 489 val metaArray = Module(new ICacheMetaArray) 490 val dataArray = Module(new ICacheDataArray) 491 val mainPipe = Module(new ICacheMainPipe) 492 val missUnit = Module(new ICacheMissUnit(edge)) 493 val releaseUnit = Module(new ReleaseUnit(edge)) 494 val replacePipe = Module(new ICacheReplacePipe) 495 val probeQueue = Module(new ICacheProbeQueue(edge)) 496 val prefetchPipe = Module(new IPrefetchPipe) 497 498 val meta_read_arb = Module(new Arbiter(new ICacheReadBundle, 3)) 499 val data_read_arb = Module(new Arbiter(new ICacheReadBundle, 2)) 500 val meta_write_arb = Module(new Arbiter(new ICacheMetaWriteBundle(), 2 )) 501 val replace_req_arb = Module(new Arbiter(new ReplacePipeReq, 2)) 502 // val tlb_req_arb = Module(new Arbiter(new TlbReq, 2)) 503 504 meta_read_arb.io.in(ReplacePipeKey) <> replacePipe.io.meta_read 505 meta_read_arb.io.in(MainPipeKey) <> mainPipe.io.metaArray.toIMeta 506 meta_read_arb.io.in(2) <> prefetchPipe.io.toIMeta 507 metaArray.io.read <> meta_read_arb.io.out 508 509 replacePipe.io.meta_response <> metaArray.io.readResp 510 mainPipe.io.metaArray.fromIMeta <> metaArray.io.readResp 511 prefetchPipe.io.fromIMeta <> metaArray.io.readResp 512 513 data_read_arb.io.in(ReplacePipeKey) <> replacePipe.io.data_read 514 data_read_arb.io.in(MainPipeKey) <> mainPipe.io.dataArray.toIData 515 dataArray.io.read <> data_read_arb.io.out 516 replacePipe.io.data_response <> dataArray.io.readResp 517 mainPipe.io.dataArray.fromIData <> dataArray.io.readResp 518 519 mainPipe.io.respStall := io.stop 520 io.perfInfo := mainPipe.io.perfInfo 521 522 meta_write_arb.io.in(ReplacePipeKey) <> replacePipe.io.meta_write 523 meta_write_arb.io.in(MainPipeKey) <> missUnit.io.meta_write 524 525 metaArray.io.write <> meta_write_arb.io.out 526 dataArray.io.write <> missUnit.io.data_write 527 528 mainPipe.io.csr_parity_enable := io.csr_parity_enable 529 replacePipe.io.csr_parity_enable := io.csr_parity_enable 530 531 if(cacheParams.hasPrefetch){ 532 prefetchPipe.io.fromFtq <> io.prefetch 533 when(!io.csr_pf_enable){ 534 prefetchPipe.io.fromFtq.req.valid := false.B 535 io.prefetch.req.ready := true.B 536 } 537 } else { 538 prefetchPipe.io.fromFtq <> DontCare 539 } 540 541 io.pmp(0) <> mainPipe.io.pmp(0) 542 io.pmp(1) <> mainPipe.io.pmp(1) 543 io.pmp(2) <> prefetchPipe.io.pmp 544 545 prefetchPipe.io.prefetchEnable := mainPipe.io.prefetchEnable 546 prefetchPipe.io.prefetchDisable := mainPipe.io.prefetchDisable 547 548 549 // tlb_req_arb.io.in(0) <> mainPipe.io.itlb(0).req 550 // tlb_req_arb.io.in(1) <> prefetchPipe.io.iTLBInter.req 551 // io.itlb(0).req <> tlb_req_arb.io.out 552 553 // mainPipe.io.itlb(0).resp <> io.itlb(0).resp 554 // prefetchPipe.io.iTLBInter.resp <> io.itlb(0).resp 555 556 // when(mainPipe.io.itlb(0).req.fire() && prefetchPipe.io.iTLBInter.req.fire()) 557 // { 558 // assert(false.B, "Both mainPipe ITLB and prefetchPipe ITLB fire!") 559 // } 560 561 io.itlb(0) <> mainPipe.io.itlb(0) 562 io.itlb(1) <> mainPipe.io.itlb(1) 563 io.itlb(2) <> mainPipe.io.itlb(2) 564 io.itlb(3) <> mainPipe.io.itlb(3) 565 io.itlb(4) <> prefetchPipe.io.iTLBInter 566 567 for(i <- 0 until PortNumber){ 568 io.fetch(i).resp <> mainPipe.io.fetch(i).resp 569 570 missUnit.io.req(i) <> mainPipe.io.mshr(i).toMSHR 571 mainPipe.io.mshr(i).fromMSHR <> missUnit.io.resp(i) 572 573 } 574 575 missUnit.io.prefetch_req <> prefetchPipe.io.toMissUnit.enqReq 576 missUnit.io.hartId := io.hartId 577 prefetchPipe.io.fromMSHR <> missUnit.io.prefetch_check 578 579 bus.b.ready := false.B 580 bus.c.valid := false.B 581 bus.c.bits := DontCare 582 bus.e.valid := false.B 583 bus.e.bits := DontCare 584 585 bus.a <> missUnit.io.mem_acquire 586 bus.e <> missUnit.io.mem_finish 587 588 releaseUnit.io.req <> replacePipe.io.release_req 589 replacePipe.io.release_finish := releaseUnit.io.finish 590 bus.c <> releaseUnit.io.mem_release 591 592 // connect bus d 593 missUnit.io.mem_grant.valid := false.B 594 missUnit.io.mem_grant.bits := DontCare 595 596 releaseUnit.io.mem_grant.valid := false.B 597 releaseUnit.io.mem_grant.bits := DontCare 598 599 //Probe through bus b 600 probeQueue.io.mem_probe <> bus.b 601 602 //Parity error port 603 val errors = mainPipe.io.errors ++ Seq(replacePipe.io.error) 604 io.error <> RegNext(Mux1H(errors.map(e => e.valid -> e))) 605 606 607 /** Block set-conflict request */ 608 val probeReqValid = probeQueue.io.pipe_req.valid 609 val probeReqVidx = probeQueue.io.pipe_req.bits.vidx 610 611 val hasVictim = VecInit(missUnit.io.victimInfor.map(_.valid)) 612 val victimSetSeq = VecInit(missUnit.io.victimInfor.map(_.vidx)) 613 614 val probeShouldBlock = VecInit(hasVictim.zip(victimSetSeq).map{case(valid, idx) => valid && probeReqValid && idx === probeReqVidx }).reduce(_||_) 615 616 val releaseReqValid = missUnit.io.release_req.valid 617 val releaseReqVidx = missUnit.io.release_req.bits.vidx 618 619 val hasConflict = VecInit(Seq( 620 replacePipe.io.status.r1_set.valid, 621 replacePipe.io.status.r2_set.valid, 622 replacePipe.io.status.r3_set.valid 623 )) 624 625 val conflictIdx = VecInit(Seq( 626 replacePipe.io.status.r1_set.bits, 627 replacePipe.io.status.r2_set.bits, 628 replacePipe.io.status.r3_set.bits 629 )) 630 631 val releaseShouldBlock = VecInit(hasConflict.zip(conflictIdx).map{case(valid, idx) => valid && releaseReqValid && idx === releaseReqVidx }).reduce(_||_) 632 633 replace_req_arb.io.in(ReplacePipeKey) <> probeQueue.io.pipe_req 634 replace_req_arb.io.in(ReplacePipeKey).valid := probeQueue.io.pipe_req.valid && !probeShouldBlock 635 replace_req_arb.io.in(MainPipeKey) <> missUnit.io.release_req 636 replace_req_arb.io.in(MainPipeKey).valid := missUnit.io.release_req.valid && !releaseShouldBlock 637 replacePipe.io.pipe_req <> replace_req_arb.io.out 638 639 when(releaseShouldBlock){ 640 missUnit.io.release_req.ready := false.B 641 } 642 643 when(probeShouldBlock){ 644 probeQueue.io.pipe_req.ready := false.B 645 } 646 647 648 missUnit.io.release_resp <> replacePipe.io.pipe_resp 649 650 651 (0 until PortNumber).map{i => 652 mainPipe.io.fetch(i).req.valid := io.fetch(i).req.valid //&& !fetchShouldBlock(i) 653 io.fetch(i).req.ready := mainPipe.io.fetch(i).req.ready //&& !fetchShouldBlock(i) 654 mainPipe.io.fetch(i).req.bits := io.fetch(i).req.bits 655 } 656 657 // in L1ICache, we only expect GrantData and ReleaseAck 658 bus.d.ready := false.B 659 when ( bus.d.bits.opcode === TLMessages.GrantData) { 660 missUnit.io.mem_grant <> bus.d 661 } .elsewhen (bus.d.bits.opcode === TLMessages.ReleaseAck) { 662 releaseUnit.io.mem_grant <> bus.d 663 } .otherwise { 664 assert (!bus.d.fire()) 665 } 666 667 val perfEvents = Seq( 668 ("icache_miss_cnt ", false.B), 669 ("icache_miss_penty", BoolStopWatch(start = false.B, stop = false.B || false.B, startHighPriority = true)), 670 ) 671 generatePerfEvent() 672 673 // Customized csr cache op support 674 val cacheOpDecoder = Module(new CSRCacheOpDecoder("icache", CacheInstrucion.COP_ID_ICACHE)) 675 cacheOpDecoder.io.csr <> io.csr 676 dataArray.io.cacheOp.req := cacheOpDecoder.io.cache.req 677 metaArray.io.cacheOp.req := cacheOpDecoder.io.cache.req 678 cacheOpDecoder.io.cache.resp.valid := 679 dataArray.io.cacheOp.resp.valid || 680 metaArray.io.cacheOp.resp.valid 681 cacheOpDecoder.io.cache.resp.bits := Mux1H(List( 682 dataArray.io.cacheOp.resp.valid -> dataArray.io.cacheOp.resp.bits, 683 metaArray.io.cacheOp.resp.valid -> metaArray.io.cacheOp.resp.bits, 684 )) 685 cacheOpDecoder.io.error := io.error 686 assert(!((dataArray.io.cacheOp.resp.valid +& metaArray.io.cacheOp.resp.valid) > 1.U)) 687 688} 689