1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend.icache 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util.{DecoupledIO, _} 22import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp, TransferSizes} 23import freechips.rocketchip.tilelink._ 24import freechips.rocketchip.util.BundleFieldBase 25import huancun.{AliasField, DirtyField, PreferCacheField, PrefetchField} 26import xiangshan._ 27import xiangshan.frontend._ 28import xiangshan.cache._ 29import utils._ 30import utility._ 31import xiangshan.backend.fu.PMPReqBundle 32import xiangshan.cache.mmu.{TlbRequestIO, TlbReq} 33 34case class ICacheParameters( 35 nSets: Int = 256, 36 nWays: Int = 8, 37 rowBits: Int = 64, 38 nTLBEntries: Int = 32, 39 tagECC: Option[String] = None, 40 dataECC: Option[String] = None, 41 replacer: Option[String] = Some("random"), 42 nMissEntries: Int = 2, 43 nReleaseEntries: Int = 1, 44 nProbeEntries: Int = 2, 45 nPrefetchEntries: Int = 4, 46 hasPrefetch: Boolean = false, 47 nMMIOs: Int = 1, 48 blockBytes: Int = 64 49)extends L1CacheParameters { 50 51 val setBytes = nSets * blockBytes 52 val aliasBitsOpt = if(setBytes > pageSize) Some(log2Ceil(setBytes / pageSize)) else None 53 val reqFields: Seq[BundleFieldBase] = Seq( 54 PrefetchField(), 55 PreferCacheField() 56 ) ++ aliasBitsOpt.map(AliasField) 57 val echoFields: Seq[BundleFieldBase] = Seq(DirtyField()) 58 def tagCode: Code = Code.fromString(tagECC) 59 def dataCode: Code = Code.fromString(dataECC) 60 def replacement = ReplacementPolicy.fromString(replacer,nWays,nSets) 61} 62 63trait HasICacheParameters extends HasL1CacheParameters with HasInstrMMIOConst with HasIFUConst{ 64 val cacheParams = icacheParameters 65 val dataCodeUnit = 16 66 val dataCodeUnitNum = blockBits/dataCodeUnit 67 68 def highestIdxBit = log2Ceil(nSets) - 1 69 def encDataUnitBits = cacheParams.dataCode.width(dataCodeUnit) 70 def dataCodeBits = encDataUnitBits - dataCodeUnit 71 def dataCodeEntryBits = dataCodeBits * dataCodeUnitNum 72 73 val ICacheSets = cacheParams.nSets 74 val ICacheWays = cacheParams.nWays 75 76 val ICacheSameVPAddrLength = 12 77 val ReplaceIdWid = 5 78 79 val ICacheWordOffset = 0 80 val ICacheSetOffset = ICacheWordOffset + log2Up(blockBytes) 81 val ICacheAboveIndexOffset = ICacheSetOffset + log2Up(ICacheSets) 82 val ICacheTagOffset = ICacheAboveIndexOffset min ICacheSameVPAddrLength 83 84 def PortNumber = 2 85 86 def partWayNum = 4 87 def pWay = nWays/partWayNum 88 89 def nPrefetchEntries = cacheParams.nPrefetchEntries 90 91 def getBits(num: Int) = log2Ceil(num).W 92 93 94 def generatePipeControl(lastFire: Bool, thisFire: Bool, thisFlush: Bool, lastFlush: Bool): Bool = { 95 val valid = RegInit(false.B) 96 when(thisFlush) {valid := false.B} 97 .elsewhen(lastFire && !lastFlush) {valid := true.B} 98 .elsewhen(thisFire) {valid := false.B} 99 valid 100 } 101 102 def ResultHoldBypass[T<:Data](data: T, valid: Bool): T = { 103 Mux(valid, data, RegEnable(data, valid)) 104 } 105 106 require(isPow2(nSets), s"nSets($nSets) must be pow2") 107 require(isPow2(nWays), s"nWays($nWays) must be pow2") 108} 109 110abstract class ICacheBundle(implicit p: Parameters) extends XSBundle 111 with HasICacheParameters 112 113abstract class ICacheModule(implicit p: Parameters) extends XSModule 114 with HasICacheParameters 115 116abstract class ICacheArray(implicit p: Parameters) extends XSModule 117 with HasICacheParameters 118 119class ICacheMetadata(implicit p: Parameters) extends ICacheBundle { 120 val tag = UInt(tagBits.W) 121} 122 123object ICacheMetadata { 124 def apply(tag: Bits)(implicit p: Parameters) = { 125 val meta = Wire(new ICacheMetadata) 126 meta.tag := tag 127 meta 128 } 129} 130 131 132class ICacheMetaArray()(implicit p: Parameters) extends ICacheArray 133{ 134 def onReset = ICacheMetadata(0.U) 135 val metaBits = onReset.getWidth 136 val metaEntryBits = cacheParams.tagCode.width(metaBits) 137 138 val io=IO{new Bundle{ 139 val write = Flipped(DecoupledIO(new ICacheMetaWriteBundle)) 140 val read = Flipped(DecoupledIO(new ICacheReadBundle)) 141 val readResp = Output(new ICacheMetaRespBundle) 142 val cacheOp = Flipped(new L1CacheInnerOpIO) // customized cache op port 143 val fencei = Input(Bool()) 144 }} 145 146 io.read.ready := !io.write.valid 147 148 val port_0_read_0 = io.read.valid && !io.read.bits.vSetIdx(0)(0) 149 val port_0_read_1 = io.read.valid && io.read.bits.vSetIdx(0)(0) 150 val port_1_read_1 = io.read.valid && io.read.bits.vSetIdx(1)(0) && io.read.bits.isDoubleLine 151 val port_1_read_0 = io.read.valid && !io.read.bits.vSetIdx(1)(0) && io.read.bits.isDoubleLine 152 153 val port_0_read_0_reg = RegEnable(next = port_0_read_0, enable = io.read.fire()) 154 val port_0_read_1_reg = RegEnable(next = port_0_read_1, enable = io.read.fire()) 155 val port_1_read_1_reg = RegEnable(next = port_1_read_1, enable = io.read.fire()) 156 val port_1_read_0_reg = RegEnable(next = port_1_read_0, enable = io.read.fire()) 157 158 val bank_0_idx = Mux(port_0_read_0, io.read.bits.vSetIdx(0), io.read.bits.vSetIdx(1)) 159 val bank_1_idx = Mux(port_0_read_1, io.read.bits.vSetIdx(0), io.read.bits.vSetIdx(1)) 160 val bank_idx = Seq(bank_0_idx, bank_1_idx) 161 162 val write_bank_0 = io.write.valid && !io.write.bits.bankIdx 163 val write_bank_1 = io.write.valid && io.write.bits.bankIdx 164 165 val write_meta_bits = Wire(UInt(metaEntryBits.W)) 166 167 val tagArrays = (0 until 2) map { bank => 168 val tagArray = Module(new SRAMTemplate( 169 UInt(metaEntryBits.W), 170 set=nSets/2, 171 way=nWays, 172 shouldReset = true, 173 holdRead = true, 174 singlePort = true 175 )) 176 177 //meta connection 178 if(bank == 0) { 179 tagArray.io.r.req.valid := port_0_read_0 || port_1_read_0 180 tagArray.io.r.req.bits.apply(setIdx=bank_0_idx(highestIdxBit,1)) 181 tagArray.io.w.req.valid := write_bank_0 182 tagArray.io.w.req.bits.apply(data=write_meta_bits, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 183 } 184 else { 185 tagArray.io.r.req.valid := port_0_read_1 || port_1_read_1 186 tagArray.io.r.req.bits.apply(setIdx=bank_1_idx(highestIdxBit,1)) 187 tagArray.io.w.req.valid := write_bank_1 188 tagArray.io.w.req.bits.apply(data=write_meta_bits, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 189 } 190 191 tagArray 192 } 193 194 val read_set_idx_next = RegEnable(next = io.read.bits.vSetIdx, enable = io.read.fire) 195 val valid_array = RegInit(VecInit(Seq.fill(nWays)(0.U(nSets.W)))) 196 val valid_metas = Wire(Vec(PortNumber, Vec(nWays, Bool()))) 197 // valid read 198 (0 until PortNumber).foreach( i => 199 (0 until nWays).foreach( way => 200 valid_metas(i)(way) := valid_array(way)(read_set_idx_next(i)) 201 )) 202 io.readResp.entryValid := valid_metas 203// val readIdxNext = RegEnable(next = io.read.bits.vSetIdx, enable = io.read.fire) 204// val validArray = RegInit(0.U((nSets * nWays).W)) 205// val validMetas = VecInit((0 until 2).map{ bank => 206// val validMeta = Cat((0 until nWays).map{w => validArray( Cat(readIdxNext(bank), w.U(log2Ceil(nWays).W)) )}.reverse).asUInt 207// validMeta 208// }) 209// io.readResp.entryValid := validMetas.asTypeOf(Vec(2, Vec(nWays, Bool()))) 210 211 io.read.ready := !io.write.valid && !io.fencei && tagArrays.map(_.io.r.req.ready).reduce(_&&_) 212 213 //Parity Decode 214 val read_metas = Wire(Vec(2,Vec(nWays,new ICacheMetadata()))) 215 for((tagArray,i) <- tagArrays.zipWithIndex){ 216 val read_meta_bits = tagArray.io.r.resp.asTypeOf(Vec(nWays,UInt(metaEntryBits.W))) 217 val read_meta_decoded = read_meta_bits.map{ way_bits => cacheParams.tagCode.decode(way_bits)} 218 val read_meta_wrong = read_meta_decoded.map{ way_bits_decoded => way_bits_decoded.error} 219 val read_meta_corrected = VecInit(read_meta_decoded.map{ way_bits_decoded => way_bits_decoded.corrected}) 220 read_metas(i) := read_meta_corrected.asTypeOf(Vec(nWays,new ICacheMetadata())) 221 (0 until nWays).map{ w => io.readResp.errors(i)(w) := RegNext(read_meta_wrong(w)) && RegNext(RegNext(io.read.fire))} 222 } 223 224 //Parity Encode 225 val write = io.write.bits 226 write_meta_bits := cacheParams.tagCode.encode(ICacheMetadata(tag = write.phyTag).asUInt) 227 228// val wayNum = OHToUInt(io.write.bits.waymask) 229// val validPtr = Cat(io.write.bits.virIdx, wayNum) 230// when (io.write.valid) { 231// validArray := validArray.bitSet(validPtr, true.B) 232// } 233 // valid write 234 val way_num = OHToUInt(io.write.bits.waymask) 235 when (io.write.valid) { 236 valid_array(way_num) := valid_array(way_num).bitSet(io.write.bits.virIdx, true.B) 237 } 238 239 XSPerfAccumulate("meta_refill_num", io.write.valid) 240 241 io.readResp.metaData <> DontCare 242 when(port_0_read_0_reg){ 243 io.readResp.metaData(0) := read_metas(0) 244 }.elsewhen(port_0_read_1_reg){ 245 io.readResp.metaData(0) := read_metas(1) 246 } 247 248 when(port_1_read_0_reg){ 249 io.readResp.metaData(1) := read_metas(0) 250 }.elsewhen(port_1_read_1_reg){ 251 io.readResp.metaData(1) := read_metas(1) 252 } 253 254 255 io.write.ready := true.B 256 // deal with customized cache op 257 require(nWays <= 32) 258 io.cacheOp.resp.bits := DontCare 259 val cacheOpShouldResp = WireInit(false.B) 260 when(io.cacheOp.req.valid){ 261 when( 262 CacheInstrucion.isReadTag(io.cacheOp.req.bits.opCode) || 263 CacheInstrucion.isReadTagECC(io.cacheOp.req.bits.opCode) 264 ){ 265 for (i <- 0 until 2) { 266 tagArrays(i).io.r.req.valid := true.B 267 tagArrays(i).io.r.req.bits.apply(setIdx = io.cacheOp.req.bits.index) 268 } 269 cacheOpShouldResp := true.B 270 } 271 when(CacheInstrucion.isWriteTag(io.cacheOp.req.bits.opCode)){ 272 for (i <- 0 until 2) { 273 tagArrays(i).io.w.req.valid := true.B 274 tagArrays(i).io.w.req.bits.apply( 275 data = io.cacheOp.req.bits.write_tag_low, 276 setIdx = io.cacheOp.req.bits.index, 277 waymask = UIntToOH(io.cacheOp.req.bits.wayNum(4, 0)) 278 ) 279 } 280 cacheOpShouldResp := true.B 281 } 282 // TODO 283 // when(CacheInstrucion.isWriteTagECC(io.cacheOp.req.bits.opCode)){ 284 // for (i <- 0 until readPorts) { 285 // array(i).io.ecc_write.valid := true.B 286 // array(i).io.ecc_write.bits.idx := io.cacheOp.req.bits.index 287 // array(i).io.ecc_write.bits.way_en := UIntToOH(io.cacheOp.req.bits.wayNum(4, 0)) 288 // array(i).io.ecc_write.bits.ecc := io.cacheOp.req.bits.write_tag_ecc 289 // } 290 // cacheOpShouldResp := true.B 291 // } 292 } 293 io.cacheOp.resp.valid := RegNext(io.cacheOp.req.valid && cacheOpShouldResp) 294 io.cacheOp.resp.bits.read_tag_low := Mux(io.cacheOp.resp.valid, 295 tagArrays(0).io.r.resp.asTypeOf(Vec(nWays, UInt(tagBits.W)))(io.cacheOp.req.bits.wayNum), 296 0.U 297 ) 298 io.cacheOp.resp.bits.read_tag_ecc := DontCare // TODO 299 // TODO: deal with duplicated array 300 301 // fencei logic : reset valid_array 302 when (io.fencei) { 303 (0 until nWays).foreach( way => 304 valid_array(way) := 0.U 305 ) 306 } 307} 308 309 310 311class ICacheDataArray(implicit p: Parameters) extends ICacheArray 312{ 313 314 def getECCFromEncUnit(encUnit: UInt) = { 315 require(encUnit.getWidth == encDataUnitBits) 316 if (encDataUnitBits == dataCodeUnit) { 317 0.U.asTypeOf(UInt(1.W)) 318 } else { 319 encUnit(encDataUnitBits - 1, dataCodeUnit) 320 } 321 } 322 323 def getECCFromBlock(cacheblock: UInt) = { 324 // require(cacheblock.getWidth == blockBits) 325 VecInit((0 until dataCodeUnitNum).map { w => 326 val unit = cacheblock(dataCodeUnit * (w + 1) - 1, dataCodeUnit * w) 327 getECCFromEncUnit(cacheParams.dataCode.encode(unit)) 328 }) 329 } 330 331 val io=IO{new Bundle{ 332 val write = Flipped(DecoupledIO(new ICacheDataWriteBundle)) 333 val read = Flipped(DecoupledIO(Vec(partWayNum, new ICacheReadBundle))) 334 val readResp = Output(new ICacheDataRespBundle) 335 val cacheOp = Flipped(new L1CacheInnerOpIO) // customized cache op port 336 }} 337 338 val write_data_bits = Wire(UInt(blockBits.W)) 339 340 val port_0_read_0_reg = RegEnable(next = io.read.valid && io.read.bits.head.port_0_read_0, enable = io.read.fire()) 341 val port_0_read_1_reg = RegEnable(next = io.read.valid && io.read.bits.head.port_0_read_1, enable = io.read.fire()) 342 val port_1_read_1_reg = RegEnable(next = io.read.valid && io.read.bits.head.port_1_read_1, enable = io.read.fire()) 343 val port_1_read_0_reg = RegEnable(next = io.read.valid && io.read.bits.head.port_1_read_0, enable = io.read.fire()) 344 345 val bank_0_idx_vec = io.read.bits.map(copy => Mux(io.read.valid && copy.port_0_read_0, copy.vSetIdx(0), copy.vSetIdx(1))) 346 val bank_1_idx_vec = io.read.bits.map(copy => Mux(io.read.valid && copy.port_0_read_1, copy.vSetIdx(0), copy.vSetIdx(1))) 347 348 val dataArrays = (0 until partWayNum).map{ i => 349 val dataArray = Module(new ICachePartWayArray( 350 UInt(blockBits.W), 351 pWay, 352 )) 353 354 dataArray.io.read.req(0).valid := io.read.bits(i).read_bank_0 && io.read.valid 355 dataArray.io.read.req(0).bits.ridx := bank_0_idx_vec(i)(highestIdxBit,1) 356 dataArray.io.read.req(1).valid := io.read.bits(i).read_bank_1 && io.read.valid 357 dataArray.io.read.req(1).bits.ridx := bank_1_idx_vec(i)(highestIdxBit,1) 358 359 360 dataArray.io.write.valid := io.write.valid 361 dataArray.io.write.bits.wdata := write_data_bits 362 dataArray.io.write.bits.widx := io.write.bits.virIdx(highestIdxBit,1) 363 dataArray.io.write.bits.wbankidx := io.write.bits.bankIdx 364 dataArray.io.write.bits.wmask := io.write.bits.waymask.asTypeOf(Vec(partWayNum, Vec(pWay, Bool())))(i) 365 366 dataArray 367 } 368 369 val read_datas = Wire(Vec(2,Vec(nWays,UInt(blockBits.W) ))) 370 371 (0 until PortNumber).map { port => 372 (0 until nWays).map { w => 373 read_datas(port)(w) := dataArrays(w / pWay).io.read.resp.rdata(port).asTypeOf(Vec(pWay, UInt(blockBits.W)))(w % pWay) 374 } 375 } 376 377 io.readResp.datas(0) := Mux( port_0_read_1_reg, read_datas(1) , read_datas(0)) 378 io.readResp.datas(1) := Mux( port_1_read_0_reg, read_datas(0) , read_datas(1)) 379 380 381 val write_data_code = Wire(UInt(dataCodeEntryBits.W)) 382 val write_bank_0 = WireInit(io.write.valid && !io.write.bits.bankIdx) 383 val write_bank_1 = WireInit(io.write.valid && io.write.bits.bankIdx) 384 385 val bank_0_idx = bank_0_idx_vec.last 386 val bank_1_idx = bank_1_idx_vec.last 387 388 val codeArrays = (0 until 2) map { i => 389 val codeArray = Module(new SRAMTemplate( 390 UInt(dataCodeEntryBits.W), 391 set=nSets/2, 392 way=nWays, 393 shouldReset = true, 394 holdRead = true, 395 singlePort = true 396 )) 397 398 if(i == 0) { 399 codeArray.io.r.req.valid := io.read.valid && io.read.bits.last.read_bank_0 400 codeArray.io.r.req.bits.apply(setIdx=bank_0_idx(highestIdxBit,1)) 401 codeArray.io.w.req.valid := write_bank_0 402 codeArray.io.w.req.bits.apply(data=write_data_code, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 403 } 404 else { 405 codeArray.io.r.req.valid := io.read.valid && io.read.bits.last.read_bank_1 406 codeArray.io.r.req.bits.apply(setIdx=bank_1_idx(highestIdxBit,1)) 407 codeArray.io.w.req.valid := write_bank_1 408 codeArray.io.w.req.bits.apply(data=write_data_code, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 409 } 410 411 codeArray 412 } 413 414 io.read.ready := !io.write.valid && 415 dataArrays.map(_.io.read.req.map(_.ready).reduce(_&&_)).reduce(_&&_) && 416 codeArrays.map(_.io.r.req.ready).reduce(_ && _) 417 418 //Parity Decode 419 val read_codes = Wire(Vec(2,Vec(nWays,UInt(dataCodeEntryBits.W) ))) 420 for(((dataArray,codeArray),i) <- dataArrays.zip(codeArrays).zipWithIndex){ 421 read_codes(i) := codeArray.io.r.resp.asTypeOf(Vec(nWays,UInt(dataCodeEntryBits.W))) 422 } 423 424 //Parity Encode 425 val write = io.write.bits 426 val write_data = WireInit(write.data) 427 write_data_code := getECCFromBlock(write_data).asUInt 428 write_data_bits := write_data 429 430 io.readResp.codes(0) := Mux( port_0_read_1_reg, read_codes(1) , read_codes(0)) 431 io.readResp.codes(1) := Mux( port_1_read_0_reg, read_codes(0) , read_codes(1)) 432 433 io.write.ready := true.B 434 435 // deal with customized cache op 436 require(nWays <= 32) 437 io.cacheOp.resp.bits := DontCare 438 io.cacheOp.resp.valid := false.B 439 val cacheOpShouldResp = WireInit(false.B) 440 val dataresp = Wire(Vec(nWays,UInt(blockBits.W) )) 441 dataresp := DontCare 442 when(io.cacheOp.req.valid){ 443 when( 444 CacheInstrucion.isReadData(io.cacheOp.req.bits.opCode) 445 ){ 446 for (i <- 0 until partWayNum) { 447 dataArrays(i).io.read.req.zipWithIndex.map{ case(port,i) => 448 if(i ==0) port.valid := !io.cacheOp.req.bits.bank_num(0) 449 else port.valid := io.cacheOp.req.bits.bank_num(0) 450 port.bits.ridx := io.cacheOp.req.bits.index(highestIdxBit,1) 451 } 452 } 453 cacheOpShouldResp := dataArrays.head.io.read.req.map(_.fire()).reduce(_||_) 454 dataresp :=Mux(io.cacheOp.req.bits.bank_num(0).asBool, read_datas(1), read_datas(0)) 455 } 456 when(CacheInstrucion.isWriteData(io.cacheOp.req.bits.opCode)){ 457 for (i <- 0 until partWayNum) { 458 dataArrays(i).io.write.valid := true.B 459 dataArrays(i).io.write.bits.wdata := io.cacheOp.req.bits.write_data_vec.asTypeOf(write_data.cloneType) 460 dataArrays(i).io.write.bits.wbankidx := io.cacheOp.req.bits.bank_num(0) 461 dataArrays(i).io.write.bits.widx := io.cacheOp.req.bits.index(highestIdxBit,1) 462 dataArrays(i).io.write.bits.wmask := UIntToOH(io.cacheOp.req.bits.wayNum(4, 0)).asTypeOf(Vec(partWayNum, Vec(pWay, Bool())))(i) 463 } 464 cacheOpShouldResp := true.B 465 } 466 } 467 468 io.cacheOp.resp.valid := RegNext(cacheOpShouldResp) 469 val numICacheLineWords = blockBits / 64 470 require(blockBits >= 64 && isPow2(blockBits)) 471 for (wordIndex <- 0 until numICacheLineWords) { 472 io.cacheOp.resp.bits.read_data_vec(wordIndex) := dataresp(io.cacheOp.req.bits.wayNum(4, 0))(64*(wordIndex+1)-1, 64*wordIndex) 473 } 474 475} 476 477 478class ICacheIO(implicit p: Parameters) extends ICacheBundle 479{ 480 val hartId = Input(UInt(8.W)) 481 val prefetch = Flipped(new FtqPrefechBundle) 482 val stop = Input(Bool()) 483 val fetch = new ICacheMainPipeBundle 484 val toIFU = Output(Bool()) 485 val pmp = Vec(PortNumber + 1, new ICachePMPBundle) 486 val itlb = Vec(PortNumber + 1, new TlbRequestIO) 487 val perfInfo = Output(new ICachePerfInfo) 488 val error = new L1CacheErrorInfo 489 /* Cache Instruction */ 490 val csr = new L1CacheToCsrIO 491 /* CSR control signal */ 492 val csr_pf_enable = Input(Bool()) 493 val csr_parity_enable = Input(Bool()) 494 val fencei = Input(Bool()) 495} 496 497class ICache()(implicit p: Parameters) extends LazyModule with HasICacheParameters { 498 499 val clientParameters = TLMasterPortParameters.v1( 500 Seq(TLMasterParameters.v1( 501 name = "icache", 502 sourceId = IdRange(0, cacheParams.nMissEntries + cacheParams.nReleaseEntries), 503 supportsProbe = TransferSizes(blockBytes), 504 supportsHint = TransferSizes(blockBytes) 505 )), 506 requestFields = cacheParams.reqFields, 507 echoFields = cacheParams.echoFields 508 ) 509 510 val clientNode = TLClientNode(Seq(clientParameters)) 511 512 lazy val module = new ICacheImp(this) 513} 514 515class ICacheImp(outer: ICache) extends LazyModuleImp(outer) with HasICacheParameters with HasPerfEvents { 516 val io = IO(new ICacheIO) 517 518 println("ICache:") 519 println(" ICacheSets: " + cacheParams.nSets) 520 println(" ICacheWays: " + cacheParams.nWays) 521 println(" ICacheBanks: " + PortNumber) 522 println(" hasPrefetch: " + cacheParams.hasPrefetch) 523 if(cacheParams.hasPrefetch){ 524 println(" nPrefetchEntries: " + cacheParams.nPrefetchEntries) 525 } 526 527 val (bus, edge) = outer.clientNode.out.head 528 529 val metaArray = Module(new ICacheMetaArray) 530 val dataArray = Module(new ICacheDataArray) 531 val mainPipe = Module(new ICacheMainPipe) 532 val missUnit = Module(new ICacheMissUnit(edge)) 533 val prefetchPipe = Module(new IPrefetchPipe) 534 535 val meta_read_arb = Module(new Arbiter(new ICacheReadBundle, 2)) 536 val data_read_arb = Module(new Arbiter(Vec(partWayNum, new ICacheReadBundle), 1)) 537 val meta_write_arb = Module(new Arbiter(new ICacheMetaWriteBundle(), 1)) 538 539 meta_read_arb.io.in(0) <> mainPipe.io.metaArray.toIMeta 540 meta_read_arb.io.in(1) <> prefetchPipe.io.toIMeta 541 metaArray.io.read <> meta_read_arb.io.out 542 543 mainPipe.io.metaArray.fromIMeta <> metaArray.io.readResp 544 prefetchPipe.io.fromIMeta <> metaArray.io.readResp 545 546 data_read_arb.io.in(0) <> mainPipe.io.dataArray.toIData 547 dataArray.io.read <> data_read_arb.io.out 548 mainPipe.io.dataArray.fromIData <> dataArray.io.readResp 549 550 mainPipe.io.respStall := io.stop 551 io.perfInfo := mainPipe.io.perfInfo 552 553 meta_write_arb.io.in(0) <> missUnit.io.meta_write 554 555 metaArray.io.write.valid := RegNext(meta_write_arb.io.out.valid,init =false.B) 556 metaArray.io.write.bits := RegNext(meta_write_arb.io.out.bits) 557 meta_write_arb.io.out.ready := true.B 558 559 dataArray.io.write.valid := RegNext(missUnit.io.data_write.valid,init =false.B) 560 dataArray.io.write.bits := RegNext(missUnit.io.data_write.bits) 561 missUnit.io.data_write.ready := true.B 562 563 mainPipe.io.csr_parity_enable := io.csr_parity_enable 564 565 if(cacheParams.hasPrefetch){ 566 prefetchPipe.io.fromFtq <> io.prefetch 567 when(!io.csr_pf_enable){ 568 prefetchPipe.io.fromFtq.req.valid := false.B 569 io.prefetch.req.ready := true.B 570 } 571 } else { 572 prefetchPipe.io.fromFtq <> DontCare 573 } 574 575 io.pmp(0) <> mainPipe.io.pmp(0) 576 io.pmp(1) <> mainPipe.io.pmp(1) 577 io.pmp(2) <> prefetchPipe.io.pmp 578 579 prefetchPipe.io.prefetchEnable := mainPipe.io.prefetchEnable 580 prefetchPipe.io.prefetchDisable := mainPipe.io.prefetchDisable 581 582 //notify IFU that Icache pipeline is available 583 io.toIFU := mainPipe.io.fetch.req.ready 584 585 586 io.itlb(0) <> mainPipe.io.itlb(0) 587 io.itlb(1) <> mainPipe.io.itlb(1) 588 io.itlb(2) <> prefetchPipe.io.iTLBInter 589 590 591 io.fetch.resp <> mainPipe.io.fetch.resp 592 593 for(i <- 0 until PortNumber){ 594 missUnit.io.req(i) <> mainPipe.io.mshr(i).toMSHR 595 mainPipe.io.mshr(i).fromMSHR <> missUnit.io.resp(i) 596 } 597 598 missUnit.io.prefetch_req <> prefetchPipe.io.toMissUnit.enqReq 599 missUnit.io.hartId := io.hartId 600 prefetchPipe.io.fromMSHR <> missUnit.io.prefetch_check 601 602 bus.b.ready := false.B 603 bus.c.valid := false.B 604 bus.c.bits := DontCare 605 bus.e.valid := false.B 606 bus.e.bits := DontCare 607 608 bus.a <> missUnit.io.mem_acquire 609 610 // connect bus d 611 missUnit.io.mem_grant.valid := false.B 612 missUnit.io.mem_grant.bits := DontCare 613 614 //Parity error port 615 val errors = mainPipe.io.errors 616 io.error <> RegNext(Mux1H(errors.map(e => e.valid -> e))) 617 618 619 mainPipe.io.fetch.req <> io.fetch.req 620 bus.d.ready := false.B 621 missUnit.io.mem_grant <> bus.d 622 623 val perfEvents = Seq( 624 ("icache_miss_cnt ", false.B), 625 ("icache_miss_penty", BoolStopWatch(start = false.B, stop = false.B || false.B, startHighPriority = true)), 626 ) 627 generatePerfEvent() 628 629 // Customized csr cache op support 630 val cacheOpDecoder = Module(new CSRCacheOpDecoder("icache", CacheInstrucion.COP_ID_ICACHE)) 631 cacheOpDecoder.io.csr <> io.csr 632 dataArray.io.cacheOp.req := cacheOpDecoder.io.cache.req 633 metaArray.io.cacheOp.req := cacheOpDecoder.io.cache.req 634 cacheOpDecoder.io.cache.resp.valid := 635 dataArray.io.cacheOp.resp.valid || 636 metaArray.io.cacheOp.resp.valid 637 cacheOpDecoder.io.cache.resp.bits := Mux1H(List( 638 dataArray.io.cacheOp.resp.valid -> dataArray.io.cacheOp.resp.bits, 639 metaArray.io.cacheOp.resp.valid -> metaArray.io.cacheOp.resp.bits, 640 )) 641 cacheOpDecoder.io.error := io.error 642 assert(!((dataArray.io.cacheOp.resp.valid +& metaArray.io.cacheOp.resp.valid) > 1.U)) 643 644 // fencei 645 metaArray.io.fencei := io.fencei 646 missUnit.io.fencei := io.fencei 647} 648 649class ICachePartWayReadBundle[T <: Data](gen: T, pWay: Int)(implicit p: Parameters) 650 extends ICacheBundle 651{ 652 val req = Flipped(Vec(PortNumber, Decoupled(new Bundle{ 653 val ridx = UInt((log2Ceil(nSets) - 1).W) 654 }))) 655 val resp = Output(new Bundle{ 656 val rdata = Vec(PortNumber,Vec(pWay, gen)) 657 }) 658} 659 660class ICacheWriteBundle[T <: Data](gen: T, pWay: Int)(implicit p: Parameters) 661 extends ICacheBundle 662{ 663 val wdata = gen 664 val widx = UInt((log2Ceil(nSets) - 1).W) 665 val wbankidx = Bool() 666 val wmask = Vec(pWay, Bool()) 667} 668 669class ICachePartWayArray[T <: Data](gen: T, pWay: Int)(implicit p: Parameters) extends ICacheArray 670{ 671 672 //including part way data 673 val io = IO{new Bundle { 674 val read = new ICachePartWayReadBundle(gen,pWay) 675 val write = Flipped(ValidIO(new ICacheWriteBundle(gen, pWay))) 676 }} 677 678 io.read.req.map(_.ready := !io.write.valid) 679 680 val srams = (0 until PortNumber) map { bank => 681 val sramBank = Module(new SRAMTemplate( 682 gen, 683 set=nSets/2, 684 way=pWay, 685 shouldReset = true, 686 holdRead = true, 687 singlePort = true 688 )) 689 690 sramBank.io.r.req.valid := io.read.req(bank).valid 691 sramBank.io.r.req.bits.apply(setIdx= io.read.req(bank).bits.ridx) 692 693 if(bank == 0) sramBank.io.w.req.valid := io.write.valid && !io.write.bits.wbankidx 694 else sramBank.io.w.req.valid := io.write.valid && io.write.bits.wbankidx 695 sramBank.io.w.req.bits.apply(data=io.write.bits.wdata, setIdx=io.write.bits.widx, waymask=io.write.bits.wmask.asUInt()) 696 697 sramBank 698 } 699 700 io.read.req.map(_.ready := !io.write.valid && srams.map(_.io.r.req.ready).reduce(_&&_)) 701 702 io.read.resp.rdata := VecInit(srams.map(bank => bank.io.r.resp.asTypeOf(Vec(pWay,gen)))) 703 704} 705