1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend.icache 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp, TransferSizes} 23import freechips.rocketchip.tilelink._ 24import freechips.rocketchip.util.BundleFieldBase 25import huancun.{AliasField, DirtyField, PreferCacheField, PrefetchField} 26import xiangshan._ 27import xiangshan.frontend._ 28import xiangshan.cache._ 29import utils._ 30import xiangshan.backend.fu.PMPReqBundle 31import xiangshan.cache.mmu.{BlockTlbRequestIO, TlbReq} 32 33case class ICacheParameters( 34 nSets: Int = 256, 35 nWays: Int = 8, 36 rowBits: Int = 64, 37 nTLBEntries: Int = 32, 38 tagECC: Option[String] = None, 39 dataECC: Option[String] = None, 40 replacer: Option[String] = Some("random"), 41 nMissEntries: Int = 2, 42 nReleaseEntries: Int = 1, 43 nProbeEntries: Int = 2, 44 nPrefetchEntries: Int = 4, 45 hasPrefetch: Boolean = false, 46 nMMIOs: Int = 1, 47 blockBytes: Int = 64 48)extends L1CacheParameters { 49 50 val setBytes = nSets * blockBytes 51 val aliasBitsOpt = if(setBytes > pageSize) Some(log2Ceil(setBytes / pageSize)) else None 52 val reqFields: Seq[BundleFieldBase] = Seq( 53 PrefetchField(), 54 PreferCacheField() 55 ) ++ aliasBitsOpt.map(AliasField) 56 val echoFields: Seq[BundleFieldBase] = Seq(DirtyField()) 57 def tagCode: Code = Code.fromString(tagECC) 58 def dataCode: Code = Code.fromString(dataECC) 59 def replacement = ReplacementPolicy.fromString(replacer,nWays,nSets) 60} 61 62trait HasICacheParameters extends HasL1CacheParameters with HasInstrMMIOConst with HasIFUConst{ 63 val cacheParams = icacheParameters 64 val dataCodeUnit = 16 65 val dataCodeUnitNum = blockBits/dataCodeUnit 66 67 def highestIdxBit = log2Ceil(nSets) - 1 68 def encDataUnitBits = cacheParams.dataCode.width(dataCodeUnit) 69 def dataCodeBits = encDataUnitBits - dataCodeUnit 70 def dataCodeEntryBits = dataCodeBits * dataCodeUnitNum 71 72 val ICacheSets = cacheParams.nSets 73 val ICacheWays = cacheParams.nWays 74 75 val ICacheSameVPAddrLength = 12 76 val ReplaceIdWid = 5 77 78 val ICacheWordOffset = 0 79 val ICacheSetOffset = ICacheWordOffset + log2Up(blockBytes) 80 val ICacheAboveIndexOffset = ICacheSetOffset + log2Up(ICacheSets) 81 val ICacheTagOffset = ICacheAboveIndexOffset min ICacheSameVPAddrLength 82 83 def ReplacePipeKey = 0 84 def MainPipeKey = 1 85 def PortNumber = 2 86 def ProbeKey = 3 87 88 def nPrefetchEntries = cacheParams.nPrefetchEntries 89 90 def generatePipeControl(lastFire: Bool, thisFire: Bool, thisFlush: Bool, lastFlush: Bool): Bool = { 91 val valid = RegInit(false.B) 92 when(thisFlush) {valid := false.B} 93 .elsewhen(lastFire && !lastFlush) {valid := true.B} 94 .elsewhen(thisFire) {valid := false.B} 95 valid 96 } 97 98 def ResultHoldBypass[T<:Data](data: T, valid: Bool): T = { 99 Mux(valid, data, RegEnable(data, valid)) 100 } 101 102 require(isPow2(nSets), s"nSets($nSets) must be pow2") 103 require(isPow2(nWays), s"nWays($nWays) must be pow2") 104} 105 106abstract class ICacheBundle(implicit p: Parameters) extends XSBundle 107 with HasICacheParameters 108 109abstract class ICacheModule(implicit p: Parameters) extends XSModule 110 with HasICacheParameters 111 112abstract class ICacheArray(implicit p: Parameters) extends XSModule 113 with HasICacheParameters 114 115class ICacheMetadata(implicit p: Parameters) extends ICacheBundle { 116 val coh = new ClientMetadata 117 val tag = UInt(tagBits.W) 118} 119 120object ICacheMetadata { 121 def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = { 122 val meta = Wire(new L1Metadata) 123 meta.tag := tag 124 meta.coh := coh 125 meta 126 } 127} 128 129 130class ICacheMetaArray()(implicit p: Parameters) extends ICacheArray 131{ 132 def onReset = ICacheMetadata(0.U, ClientMetadata.onReset) 133 val metaBits = onReset.getWidth 134 val metaEntryBits = cacheParams.tagCode.width(metaBits) 135 136 val io=IO{new Bundle{ 137 val write = Flipped(DecoupledIO(new ICacheMetaWriteBundle)) 138 val read = Flipped(DecoupledIO(new ICacheReadBundle)) 139 val readResp = Output(new ICacheMetaRespBundle) 140 val cacheOp = Flipped(new L1CacheInnerOpIO) // customized cache op port 141 }} 142 143 io.read.ready := !io.write.valid 144 145 val port_0_read_0 = io.read.valid && !io.read.bits.vSetIdx(0)(0) 146 val port_0_read_1 = io.read.valid && io.read.bits.vSetIdx(0)(0) 147 val port_1_read_1 = io.read.valid && io.read.bits.vSetIdx(1)(0) && io.read.bits.isDoubleLine 148 val port_1_read_0 = io.read.valid && !io.read.bits.vSetIdx(1)(0) && io.read.bits.isDoubleLine 149 150 val port_0_read_0_reg = RegEnable(next = port_0_read_0, enable = io.read.fire()) 151 val port_0_read_1_reg = RegEnable(next = port_0_read_1, enable = io.read.fire()) 152 val port_1_read_1_reg = RegEnable(next = port_1_read_1, enable = io.read.fire()) 153 val port_1_read_0_reg = RegEnable(next = port_1_read_0, enable = io.read.fire()) 154 155 val bank_0_idx = Mux(port_0_read_0, io.read.bits.vSetIdx(0), io.read.bits.vSetIdx(1)) 156 val bank_1_idx = Mux(port_0_read_1, io.read.bits.vSetIdx(0), io.read.bits.vSetIdx(1)) 157 val bank_idx = Seq(bank_0_idx, bank_1_idx) 158 159 val write_bank_0 = io.write.valid && !io.write.bits.bankIdx 160 val write_bank_1 = io.write.valid && io.write.bits.bankIdx 161 162 val write_meta_bits = Wire(UInt(metaEntryBits.W)) 163 164 val tagArrays = (0 until 2) map { bank => 165 val tagArray = Module(new SRAMTemplate( 166 UInt(metaEntryBits.W), 167 set=nSets/2, 168 way=nWays, 169 shouldReset = true, 170 holdRead = true, 171 singlePort = true 172 )) 173 174 //meta connection 175 if(bank == 0) { 176 tagArray.io.r.req.valid := port_0_read_0 || port_1_read_0 177 tagArray.io.r.req.bits.apply(setIdx=bank_0_idx(highestIdxBit,1)) 178 tagArray.io.w.req.valid := write_bank_0 179 tagArray.io.w.req.bits.apply(data=write_meta_bits, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 180 } 181 else { 182 tagArray.io.r.req.valid := port_0_read_1 || port_1_read_1 183 tagArray.io.r.req.bits.apply(setIdx=bank_1_idx(highestIdxBit,1)) 184 tagArray.io.w.req.valid := write_bank_1 185 tagArray.io.w.req.bits.apply(data=write_meta_bits, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 186 } 187 188 tagArray 189 } 190 191 //Parity Decode 192 val read_metas = Wire(Vec(2,Vec(nWays,new ICacheMetadata()))) 193 for((tagArray,i) <- tagArrays.zipWithIndex){ 194 val read_meta_bits = tagArray.io.r.resp.asTypeOf(Vec(nWays,UInt(metaEntryBits.W))) 195 val read_meta_decoded = read_meta_bits.map{ way_bits => cacheParams.tagCode.decode(way_bits)} 196 val read_meta_wrong = read_meta_decoded.map{ way_bits_decoded => way_bits_decoded.error} 197 val read_meta_corrected = VecInit(read_meta_decoded.map{ way_bits_decoded => way_bits_decoded.corrected}) 198 read_metas(i) := read_meta_corrected.asTypeOf(Vec(nWays,new ICacheMetadata())) 199 (0 until nWays).map{ w => io.readResp.errors(i)(w) := RegNext(read_meta_wrong(w)) && RegNext(RegNext(io.read.fire))} 200 } 201 202 //Parity Encode 203 val write = io.write.bits 204 write_meta_bits := cacheParams.tagCode.encode(ICacheMetadata(tag = write.phyTag, coh = write.coh).asUInt) 205 206 val wayNum = OHToUInt(io.write.bits.waymask) 207 val validPtr = Cat(io.write.bits.virIdx, wayNum) 208 209 io.readResp.metaData <> DontCare 210 when(port_0_read_0_reg){ 211 io.readResp.metaData(0) := read_metas(0) 212 }.elsewhen(port_0_read_1_reg){ 213 io.readResp.metaData(0) := read_metas(1) 214 } 215 216 when(port_1_read_0_reg){ 217 io.readResp.metaData(1) := read_metas(0) 218 }.elsewhen(port_1_read_1_reg){ 219 io.readResp.metaData(1) := read_metas(1) 220 } 221 222 223 io.write.ready := true.B 224 // deal with customized cache op 225 require(nWays <= 32) 226 io.cacheOp.resp.bits := DontCare 227 val cacheOpShouldResp = WireInit(false.B) 228 when(io.cacheOp.req.valid){ 229 when( 230 CacheInstrucion.isReadTag(io.cacheOp.req.bits.opCode) || 231 CacheInstrucion.isReadTagECC(io.cacheOp.req.bits.opCode) 232 ){ 233 for (i <- 0 until 2) { 234 tagArrays(i).io.r.req.valid := true.B 235 tagArrays(i).io.r.req.bits.apply(setIdx = io.cacheOp.req.bits.index) 236 } 237 cacheOpShouldResp := true.B 238 } 239 when(CacheInstrucion.isWriteTag(io.cacheOp.req.bits.opCode)){ 240 for (i <- 0 until 2) { 241 tagArrays(i).io.w.req.valid := true.B 242 tagArrays(i).io.w.req.bits.apply( 243 data = io.cacheOp.req.bits.write_tag_low, 244 setIdx = io.cacheOp.req.bits.index, 245 waymask = UIntToOH(io.cacheOp.req.bits.wayNum(4, 0)) 246 ) 247 } 248 cacheOpShouldResp := true.B 249 } 250 // TODO 251 // when(CacheInstrucion.isWriteTagECC(io.cacheOp.req.bits.opCode)){ 252 // for (i <- 0 until readPorts) { 253 // array(i).io.ecc_write.valid := true.B 254 // array(i).io.ecc_write.bits.idx := io.cacheOp.req.bits.index 255 // array(i).io.ecc_write.bits.way_en := UIntToOH(io.cacheOp.req.bits.wayNum(4, 0)) 256 // array(i).io.ecc_write.bits.ecc := io.cacheOp.req.bits.write_tag_ecc 257 // } 258 // cacheOpShouldResp := true.B 259 // } 260 } 261 io.cacheOp.resp.valid := RegNext(io.cacheOp.req.valid && cacheOpShouldResp) 262 io.cacheOp.resp.bits.read_tag_low := Mux(io.cacheOp.resp.valid, 263 tagArrays(0).io.r.resp.asTypeOf(Vec(nWays, UInt(tagBits.W)))(io.cacheOp.req.bits.wayNum), 264 0.U 265 ) 266 io.cacheOp.resp.bits.read_tag_ecc := DontCare // TODO 267 // TODO: deal with duplicated array 268} 269 270 271class ICacheDataArray(implicit p: Parameters) extends ICacheArray 272{ 273 274 def getECCFromEncUnit(encUnit: UInt) = { 275 require(encUnit.getWidth == encDataUnitBits) 276 encUnit(encDataUnitBits - 1, dataCodeUnit) 277 } 278 279 def getECCFromBlock(cacheblock: UInt) = { 280 // require(cacheblock.getWidth == blockBits) 281 VecInit((0 until dataCodeUnitNum).map { w => 282 val unit = cacheblock(dataCodeUnit * (w + 1) - 1, dataCodeUnit * w) 283 getECCFromEncUnit(cacheParams.dataCode.encode(unit)) 284 }) 285 } 286 287 val io=IO{new Bundle{ 288 val write = Flipped(DecoupledIO(new ICacheDataWriteBundle)) 289 val read = Flipped(DecoupledIO(new ICacheReadBundle)) 290 val readResp = Output(new ICacheDataRespBundle) 291 val cacheOp = Flipped(new L1CacheInnerOpIO) // customized cache op port 292 }} 293 294 io.read.ready := !io.write.valid 295 296 val port_0_read_0 = io.read.valid && !io.read.bits.vSetIdx(0)(0) 297 val port_0_read_1 = io.read.valid && io.read.bits.vSetIdx(0)(0) 298 val port_1_read_1 = io.read.valid && io.read.bits.vSetIdx(1)(0) && io.read.bits.isDoubleLine 299 val port_1_read_0 = io.read.valid && !io.read.bits.vSetIdx(1)(0) && io.read.bits.isDoubleLine 300 301 val port_0_read_1_reg = RegEnable(next = port_0_read_1, enable = io.read.fire()) 302 val port_1_read_0_reg = RegEnable(next = port_1_read_0, enable = io.read.fire()) 303 304 val bank_0_idx = Mux(port_0_read_0, io.read.bits.vSetIdx(0), io.read.bits.vSetIdx(1)) 305 val bank_1_idx = Mux(port_0_read_1, io.read.bits.vSetIdx(0), io.read.bits.vSetIdx(1)) 306 val bank_idx = Seq(bank_0_idx, bank_1_idx) 307 308 val write_bank_0 = WireInit(io.write.valid && !io.write.bits.bankIdx) 309 val write_bank_1 = WireInit(io.write.valid && io.write.bits.bankIdx) 310 311 val write_data_bits = Wire(UInt(blockBits.W)) 312 val write_data_code = Wire(UInt(dataCodeEntryBits.W)) 313 314 val dataArrays = (0 until 2) map { i => 315 val dataArray = Module(new SRAMTemplate( 316 UInt(blockBits.W), 317 set=nSets/2, 318 way=nWays, 319 shouldReset = true, 320 holdRead = true, 321 singlePort = true 322 )) 323 324 if(i == 0) { 325 dataArray.io.r.req.valid := port_0_read_0 || port_1_read_0 326 dataArray.io.r.req.bits.apply(setIdx=bank_0_idx(highestIdxBit,1)) 327 dataArray.io.w.req.valid := write_bank_0 328 dataArray.io.w.req.bits.apply(data=write_data_bits, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 329 } 330 else { 331 dataArray.io.r.req.valid := port_0_read_1 || port_1_read_1 332 dataArray.io.r.req.bits.apply(setIdx=bank_1_idx(highestIdxBit,1)) 333 dataArray.io.w.req.valid := write_bank_1 334 dataArray.io.w.req.bits.apply(data=write_data_bits, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 335 } 336 337 dataArray 338 } 339 340 val codeArrays = (0 until 2) map { i => 341 val codeArray = Module(new SRAMTemplate( 342 UInt(dataCodeEntryBits.W), 343 set=nSets/2, 344 way=nWays, 345 shouldReset = true, 346 holdRead = true, 347 singlePort = true 348 )) 349 350 if(i == 0) { 351 codeArray.io.r.req.valid := port_0_read_0 || port_1_read_0 352 codeArray.io.r.req.bits.apply(setIdx=bank_0_idx(highestIdxBit,1)) 353 codeArray.io.w.req.valid := write_bank_0 354 codeArray.io.w.req.bits.apply(data=write_data_code, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 355 } 356 else { 357 codeArray.io.r.req.valid := port_0_read_1 || port_1_read_1 358 codeArray.io.r.req.bits.apply(setIdx=bank_1_idx(highestIdxBit,1)) 359 codeArray.io.w.req.valid := write_bank_1 360 codeArray.io.w.req.bits.apply(data=write_data_code, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 361 } 362 363 codeArray 364 } 365 366 //Parity Decode 367 val read_datas = Wire(Vec(2,Vec(nWays,UInt(blockBits.W) ))) 368 val read_codes = Wire(Vec(2,Vec(nWays,UInt(dataCodeEntryBits.W) ))) 369 for(((dataArray,codeArray),i) <- dataArrays.zip(codeArrays).zipWithIndex){ 370 read_datas(i) := dataArray.io.r.resp.asTypeOf(Vec(nWays,UInt(blockBits.W))) 371 read_codes(i) := codeArray.io.r.resp.asTypeOf(Vec(nWays,UInt(dataCodeEntryBits.W))) 372 } 373 374 375 //Parity Encode 376 val write = io.write.bits 377 val write_data = WireInit(write.data) 378 write_data_code := getECCFromBlock(write_data).asUInt 379 write_data_bits := write_data 380 381 io.readResp.datas(0) := Mux( port_0_read_1_reg, read_datas(1) , read_datas(0)) 382 io.readResp.datas(1) := Mux( port_1_read_0_reg, read_datas(0) , read_datas(1)) 383 io.readResp.codes(0) := Mux( port_0_read_1_reg, read_codes(1) , read_codes(0)) 384 io.readResp.codes(1) := Mux( port_1_read_0_reg, read_codes(0) , read_codes(1)) 385 386 io.write.ready := true.B 387 388 // deal with customized cache op 389 require(nWays <= 32) 390 io.cacheOp.resp.bits := DontCare 391 val cacheOpShouldResp = WireInit(false.B) 392 when(io.cacheOp.req.valid){ 393 when( 394 CacheInstrucion.isReadData(io.cacheOp.req.bits.opCode) || 395 CacheInstrucion.isReadDataECC(io.cacheOp.req.bits.opCode) 396 ){ 397 (0 until 2).map(i => { 398 dataArrays(i).io.r.req.valid := true.B 399 dataArrays(i).io.r.req.bits.apply(setIdx = io.cacheOp.req.bits.index) 400 }) 401 cacheOpShouldResp := true.B 402 } 403 when(CacheInstrucion.isWriteData(io.cacheOp.req.bits.opCode)){ 404 (0 until 2).map(i => { 405 dataArrays(i).io.w.req.valid := io.cacheOp.req.bits.bank_num === i.U 406 dataArrays(i).io.w.req.bits.setIdx := io.cacheOp.req.bits.index 407 dataArrays(i).io.w.req.bits.waymask match { 408 case Some(waymask) => waymask := UIntToOH(io.cacheOp.req.bits.wayNum(4, 0)) 409 case None => 410 } 411 }) 412 write_data := io.cacheOp.req.bits.write_data_vec.asTypeOf(write_data.cloneType) 413 cacheOpShouldResp := true.B 414 } 415 } 416 io.cacheOp.resp.valid := RegNext(io.cacheOp.req.valid && cacheOpShouldResp) 417 val dataresp = Mux(io.cacheOp.req.bits.bank_num(0).asBool, 418 read_datas(1), 419 read_datas(0) 420 ) 421 422 val numICacheLineWords = blockBits / 64 423 require(blockBits >= 64 && isPow2(blockBits)) 424 for (wordIndex <- 0 until numICacheLineWords) { 425 io.cacheOp.resp.bits.read_data_vec(wordIndex) := dataresp(io.cacheOp.req.bits.wayNum(4, 0))(64*(wordIndex+1)-1, 64*wordIndex) 426 } 427 // io.cacheOp.resp.bits.read_data_ecc := Mux(io.cacheOp.resp.valid, 428 // bank_result(io.cacheOp.req.bits.bank_num).ecc, 429 // 0.U 430 // ) 431} 432 433 434class ICacheIO(implicit p: Parameters) extends ICacheBundle 435{ 436 val hartId = Input(UInt(8.W)) 437 val prefetch = Flipped(new FtqPrefechBundle) 438 val stop = Input(Bool()) 439 val fetch = Vec(PortNumber, new ICacheMainPipeBundle) 440 val pmp = Vec(PortNumber + 1, new ICachePMPBundle) 441 val itlb = Vec(PortNumber * 2 + 1, new BlockTlbRequestIO) 442 val perfInfo = Output(new ICachePerfInfo) 443 val error = new L1CacheErrorInfo 444 /* Cache Instruction */ 445 val csr = new L1CacheToCsrIO 446 /* CSR control signal */ 447 val csr_pf_enable = Input(Bool()) 448 val csr_parity_enable = Input(Bool()) 449} 450 451class ICache()(implicit p: Parameters) extends LazyModule with HasICacheParameters { 452 453 val clientParameters = TLMasterPortParameters.v1( 454 Seq(TLMasterParameters.v1( 455 name = "icache", 456 sourceId = IdRange(0, cacheParams.nMissEntries + cacheParams.nReleaseEntries), 457 supportsProbe = TransferSizes(blockBytes), 458 supportsHint = TransferSizes(blockBytes) 459 )), 460 requestFields = cacheParams.reqFields, 461 echoFields = cacheParams.echoFields 462 ) 463 464 val clientNode = TLClientNode(Seq(clientParameters)) 465 466 lazy val module = new ICacheImp(this) 467} 468 469class ICacheImp(outer: ICache) extends LazyModuleImp(outer) with HasICacheParameters with HasPerfEvents { 470 val io = IO(new ICacheIO) 471 472 println("ICache:") 473 println(" ICacheSets: " + cacheParams.nSets) 474 println(" ICacheWays: " + cacheParams.nWays) 475 println(" ICacheBanks: " + PortNumber) 476 println(" hasPrefetch: " + cacheParams.hasPrefetch) 477 if(cacheParams.hasPrefetch){ 478 println(" nPrefetchEntries: " + cacheParams.nPrefetchEntries) 479 } 480 481 val (bus, edge) = outer.clientNode.out.head 482 483 val metaArray = Module(new ICacheMetaArray) 484 val dataArray = Module(new ICacheDataArray) 485 val mainPipe = Module(new ICacheMainPipe) 486 val missUnit = Module(new ICacheMissUnit(edge)) 487 val releaseUnit = Module(new ReleaseUnit(edge)) 488 val replacePipe = Module(new ICacheReplacePipe) 489 val probeQueue = Module(new ICacheProbeQueue(edge)) 490 val prefetchPipe = Module(new IPrefetchPipe) 491 492 val meta_read_arb = Module(new Arbiter(new ICacheReadBundle, 3)) 493 val data_read_arb = Module(new Arbiter(new ICacheReadBundle, 2)) 494 val meta_write_arb = Module(new Arbiter(new ICacheMetaWriteBundle(), 2 )) 495 val replace_req_arb = Module(new Arbiter(new ReplacePipeReq, 2)) 496 // val tlb_req_arb = Module(new Arbiter(new TlbReq, 2)) 497 498 meta_read_arb.io.in(ReplacePipeKey) <> replacePipe.io.meta_read 499 meta_read_arb.io.in(MainPipeKey) <> mainPipe.io.metaArray.toIMeta 500 meta_read_arb.io.in(2) <> prefetchPipe.io.toIMeta 501 metaArray.io.read <> meta_read_arb.io.out 502 503 replacePipe.io.meta_response <> metaArray.io.readResp 504 mainPipe.io.metaArray.fromIMeta <> metaArray.io.readResp 505 prefetchPipe.io.fromIMeta <> metaArray.io.readResp 506 507 data_read_arb.io.in(ReplacePipeKey) <> replacePipe.io.data_read 508 data_read_arb.io.in(MainPipeKey) <> mainPipe.io.dataArray.toIData 509 dataArray.io.read <> data_read_arb.io.out 510 replacePipe.io.data_response <> dataArray.io.readResp 511 mainPipe.io.dataArray.fromIData <> dataArray.io.readResp 512 513 mainPipe.io.respStall := io.stop 514 io.perfInfo := mainPipe.io.perfInfo 515 516 meta_write_arb.io.in(ReplacePipeKey) <> replacePipe.io.meta_write 517 meta_write_arb.io.in(MainPipeKey) <> missUnit.io.meta_write 518 519 metaArray.io.write <> meta_write_arb.io.out 520 dataArray.io.write <> missUnit.io.data_write 521 522 mainPipe.io.csr_parity_enable := io.csr_parity_enable 523 replacePipe.io.csr_parity_enable := io.csr_parity_enable 524 525 if(cacheParams.hasPrefetch){ 526 prefetchPipe.io.fromFtq <> io.prefetch 527 when(!io.csr_pf_enable){ 528 prefetchPipe.io.fromFtq.req.valid := false.B 529 io.prefetch.req.ready := true.B 530 } 531 } else { 532 prefetchPipe.io.fromFtq <> DontCare 533 } 534 535 io.pmp(0) <> mainPipe.io.pmp(0) 536 io.pmp(1) <> mainPipe.io.pmp(1) 537 io.pmp(2) <> prefetchPipe.io.pmp 538 539 prefetchPipe.io.prefetchEnable := mainPipe.io.prefetchEnable 540 prefetchPipe.io.prefetchDisable := mainPipe.io.prefetchDisable 541 542 543 // tlb_req_arb.io.in(0) <> mainPipe.io.itlb(0).req 544 // tlb_req_arb.io.in(1) <> prefetchPipe.io.iTLBInter.req 545 // io.itlb(0).req <> tlb_req_arb.io.out 546 547 // mainPipe.io.itlb(0).resp <> io.itlb(0).resp 548 // prefetchPipe.io.iTLBInter.resp <> io.itlb(0).resp 549 550 // when(mainPipe.io.itlb(0).req.fire() && prefetchPipe.io.iTLBInter.req.fire()) 551 // { 552 // assert(false.B, "Both mainPipe ITLB and prefetchPipe ITLB fire!") 553 // } 554 555 io.itlb(0) <> mainPipe.io.itlb(0) 556 io.itlb(1) <> mainPipe.io.itlb(1) 557 io.itlb(2) <> mainPipe.io.itlb(2) 558 io.itlb(3) <> mainPipe.io.itlb(3) 559 io.itlb(4) <> prefetchPipe.io.iTLBInter 560 561 for(i <- 0 until PortNumber){ 562 io.fetch(i).resp <> mainPipe.io.fetch(i).resp 563 564 missUnit.io.req(i) <> mainPipe.io.mshr(i).toMSHR 565 mainPipe.io.mshr(i).fromMSHR <> missUnit.io.resp(i) 566 567 } 568 569 missUnit.io.prefetch_req <> prefetchPipe.io.toMissUnit.enqReq 570 missUnit.io.hartId := io.hartId 571 prefetchPipe.io.fromMSHR <> missUnit.io.prefetch_check 572 573 bus.b.ready := false.B 574 bus.c.valid := false.B 575 bus.c.bits := DontCare 576 bus.e.valid := false.B 577 bus.e.bits := DontCare 578 579 bus.a <> missUnit.io.mem_acquire 580 bus.e <> missUnit.io.mem_finish 581 582 releaseUnit.io.req <> replacePipe.io.release_req 583 replacePipe.io.release_finish := releaseUnit.io.finish 584 bus.c <> releaseUnit.io.mem_release 585 586 // connect bus d 587 missUnit.io.mem_grant.valid := false.B 588 missUnit.io.mem_grant.bits := DontCare 589 590 releaseUnit.io.mem_grant.valid := false.B 591 releaseUnit.io.mem_grant.bits := DontCare 592 593 //Probe through bus b 594 probeQueue.io.mem_probe <> bus.b 595 596 //Parity error port 597 val errors = mainPipe.io.errors ++ Seq(replacePipe.io.error) 598 io.error <> RegNext(Mux1H(errors.map(e => e.valid -> e))) 599 600 601 /** Block set-conflict request */ 602 val probeReqValid = probeQueue.io.pipe_req.valid 603 val probeReqVidx = probeQueue.io.pipe_req.bits.vidx 604 605 val hasVictim = VecInit(missUnit.io.victimInfor.map(_.valid)) 606 val victimSetSeq = VecInit(missUnit.io.victimInfor.map(_.vidx)) 607 608 val probeShouldBlock = VecInit(hasVictim.zip(victimSetSeq).map{case(valid, idx) => valid && probeReqValid && idx === probeReqVidx }).reduce(_||_) 609 610 val releaseReqValid = missUnit.io.release_req.valid 611 val releaseReqVidx = missUnit.io.release_req.bits.vidx 612 613 val hasConflict = VecInit(Seq( 614 replacePipe.io.status.r1_set.valid, 615 replacePipe.io.status.r2_set.valid, 616 replacePipe.io.status.r3_set.valid 617 )) 618 619 val conflictIdx = VecInit(Seq( 620 replacePipe.io.status.r1_set.bits, 621 replacePipe.io.status.r2_set.bits, 622 replacePipe.io.status.r3_set.bits 623 )) 624 625 val releaseShouldBlock = VecInit(hasConflict.zip(conflictIdx).map{case(valid, idx) => valid && releaseReqValid && idx === releaseReqVidx }).reduce(_||_) 626 627 replace_req_arb.io.in(ReplacePipeKey) <> probeQueue.io.pipe_req 628 replace_req_arb.io.in(ReplacePipeKey).valid := probeQueue.io.pipe_req.valid && !probeShouldBlock 629 replace_req_arb.io.in(MainPipeKey) <> missUnit.io.release_req 630 replace_req_arb.io.in(MainPipeKey).valid := missUnit.io.release_req.valid && !releaseShouldBlock 631 replacePipe.io.pipe_req <> replace_req_arb.io.out 632 633 when(releaseShouldBlock){ 634 missUnit.io.release_req.ready := false.B 635 } 636 637 when(probeShouldBlock){ 638 probeQueue.io.pipe_req.ready := false.B 639 } 640 641 642 missUnit.io.release_resp <> replacePipe.io.pipe_resp 643 644 645 (0 until PortNumber).map{i => 646 mainPipe.io.fetch(i).req.valid := io.fetch(i).req.valid //&& !fetchShouldBlock(i) 647 io.fetch(i).req.ready := mainPipe.io.fetch(i).req.ready //&& !fetchShouldBlock(i) 648 mainPipe.io.fetch(i).req.bits := io.fetch(i).req.bits 649 } 650 651 // in L1ICache, we only expect GrantData and ReleaseAck 652 bus.d.ready := false.B 653 when ( bus.d.bits.opcode === TLMessages.GrantData) { 654 missUnit.io.mem_grant <> bus.d 655 } .elsewhen (bus.d.bits.opcode === TLMessages.ReleaseAck) { 656 releaseUnit.io.mem_grant <> bus.d 657 } .otherwise { 658 assert (!bus.d.fire()) 659 } 660 661 val perfEvents = Seq( 662 ("icache_miss_cnt ", false.B), 663 ("icache_miss_penty", BoolStopWatch(start = false.B, stop = false.B || false.B, startHighPriority = true)), 664 ) 665 generatePerfEvent() 666 667 // Customized csr cache op support 668 val cacheOpDecoder = Module(new CSRCacheOpDecoder("icache", CacheInstrucion.COP_ID_ICACHE)) 669 cacheOpDecoder.io.csr <> io.csr 670 dataArray.io.cacheOp.req := cacheOpDecoder.io.cache.req 671 metaArray.io.cacheOp.req := cacheOpDecoder.io.cache.req 672 cacheOpDecoder.io.cache.resp.valid := 673 dataArray.io.cacheOp.resp.valid || 674 metaArray.io.cacheOp.resp.valid 675 cacheOpDecoder.io.cache.resp.bits := Mux1H(List( 676 dataArray.io.cacheOp.resp.valid -> dataArray.io.cacheOp.resp.bits, 677 metaArray.io.cacheOp.resp.valid -> metaArray.io.cacheOp.resp.bits, 678 )) 679 cacheOpDecoder.io.error := io.error 680 assert(!((dataArray.io.cacheOp.resp.valid +& metaArray.io.cacheOp.resp.valid) > 1.U)) 681 682}