xref: /XiangShan/src/main/scala/xiangshan/frontend/icache/FIFO.scala (revision e1d5ffc2d93873b72146e78c8f6a904926de8590) 
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
4* Copyright (c) 2020-2021 Peng Cheng Laboratory
5*
6* XiangShan is licensed under Mulan PSL v2.
7* You can use this software according to the terms and conditions of the Mulan PSL v2.
8* You may obtain a copy of Mulan PSL v2 at:
9*          http://license.coscl.org.cn/MulanPSL2
10*
11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
14*
15* See the Mulan PSL v2 for more details.
16***************************************************************************************/
17
18package  xiangshan.frontend.icache
19
20import chisel3._
21import chisel3.util._
22import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp}
23import freechips.rocketchip.tilelink._
24import freechips.rocketchip.util.BundleFieldBase
25import huancun.{AliasField, PrefetchField}
26import org.chipsalliance.cde.config.Parameters
27import utility._
28import utils._
29import xiangshan._
30import xiangshan.cache._
31import xiangshan.cache.mmu.TlbRequestIO
32import xiangshan.frontend._
33
34
35class FIFOReg[T <: Data](
36  val gen:            T,
37  val entries:        Int,
38  val pipe:           Boolean = false,
39  val hasFlush:       Boolean = false
40) extends Module() {
41  require(entries > 0, "Queue must have non-negative number of entries")
42
43  val io = IO(new Bundle {
44    val enq     = Flipped(DecoupledIO(gen))
45    val deq     = DecoupledIO(gen)
46    val flush   = if (hasFlush) Some(Input(Bool())) else None
47  })
48  val flush = io.flush.getOrElse(false.B)
49
50  class FIFOPtr() extends CircularQueuePtr[FIFOPtr](entries)
51
52  object FIFOPtr {
53    def apply(f: Bool, v: UInt): FIFOPtr = {
54      val ptr = Wire(new FIFOPtr)
55      ptr.flag := f
56      ptr.value := v
57      ptr
58    }
59  }
60
61  val regFiles = RegInit(VecInit(Seq.fill(entries)(0.U.asTypeOf(gen.cloneType))))
62  val enq_ptr  = RegInit(FIFOPtr(false.B, 0.U))
63  val deq_ptr  = RegInit(FIFOPtr(false.B, 0.U))
64
65  val empty = enq_ptr === deq_ptr
66  val full  = (enq_ptr.value === deq_ptr.value) && (enq_ptr.flag ^ deq_ptr.flag)
67
68  when(io.enq.fire) {
69    enq_ptr := enq_ptr + 1.U
70  }
71  when(io.deq.fire) {
72    deq_ptr := deq_ptr + 1.U
73  }
74  when(flush) {
75    enq_ptr.value := 0.U
76    enq_ptr.flag  := false.B
77    deq_ptr.value := 0.U
78    deq_ptr.flag  := false.B
79  }
80
81  when(io.enq.fire) {
82    regFiles(enq_ptr.value) := io.enq.bits
83  }
84  io.deq.bits := regFiles(deq_ptr.value)
85
86  io.deq.valid := !empty
87  io.enq.ready := !full
88  if (pipe) {
89    when(io.deq.ready) { io.enq.ready := true.B }
90  }
91}