xref: /XiangShan/src/main/scala/xiangshan/frontend/WrBypass.scala (revision b30646200e30d530074276ea626ab5a43d2ca760) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16package xiangshan.frontend
17
18import chipsalliance.rocketchip.config.Parameters
19import chisel3._
20import chisel3.util._
21import xiangshan._
22import utils._
23import utility._
24import chisel3.experimental.chiselName
25import xiangshan.cache.mmu.CAMTemplate
26
27class WrBypass[T <: Data](gen: T, val numEntries: Int, val idxWidth: Int,
28  val numWays: Int = 1, val tagWidth: Int = 0)(implicit p: Parameters) extends XSModule {
29  require(numEntries >= 0)
30  require(idxWidth > 0)
31  require(numWays >= 1)
32  require(tagWidth >= 0)
33  def hasTag = tagWidth > 0
34  def multipleWays = numWays > 1
35  val io = IO(new Bundle {
36    val wen = Input(Bool())
37    val write_idx = Input(UInt(idxWidth.W))
38    val write_tag = if (hasTag) Some(Input(UInt(tagWidth.W))) else None
39    val write_data = Input(Vec(numWays, gen))
40    val write_way_mask = if (multipleWays) Some(Input(Vec(numWays, Bool()))) else None
41
42    val hit = Output(Bool())
43    val hit_data = Vec(numWays, Valid(gen))
44  })
45
46  class Idx_Tag extends Bundle {
47    val idx = UInt(idxWidth.W)
48    val tag = if (hasTag) Some(UInt(tagWidth.W)) else None
49    def apply(idx: UInt, tag: UInt) = {
50      this.idx := idx
51      this.tag.map(_ := tag)
52    }
53  }
54  val idx_tag_cam = Module(new CAMTemplate(new Idx_Tag, numEntries, 1))
55  val data_mem = Mem(numEntries, Vec(numWays, gen))
56
57  val valids = RegInit(0.U.asTypeOf(Vec(numEntries, Vec(numWays, Bool()))))
58  val ever_written = RegInit(0.U.asTypeOf(Vec(numEntries, Bool())))
59
60
61  idx_tag_cam.io.r.req(0)(io.write_idx, io.write_tag.getOrElse(0.U))
62  val hits_oh = idx_tag_cam.io.r.resp(0).zip(ever_written).map {case (h, ew) => h && ew}
63  val hit_idx = OHToUInt(hits_oh)
64  val hit = hits_oh.reduce(_||_)
65
66  io.hit := hit
67  for (i <- 0 until numWays) {
68    io.hit_data(i).valid := Mux1H(hits_oh, valids)(i)
69    io.hit_data(i).bits  := data_mem.read(hit_idx)(i)
70  }
71
72  // Replacer
73  // Because data_mem can only write to one index
74  // Implementing a per-way replacer is meaningless
75  // So here use one replacer for all ways
76  val replacer = ReplacementPolicy.fromString("plru", numEntries) // numEntries in total
77  val replacer_touch_ways = Wire(Vec(1, Valid(UInt(log2Ceil(numEntries).W)))) // One index at a time
78  val enq_idx = replacer.way
79  val full_mask = Fill(numWays, 1.U(1.W)).asTypeOf(Vec(numWays, Bool()))
80  val update_way_mask = io.write_way_mask.getOrElse(full_mask)
81
82  // write data on every request
83  when (io.wen) {
84    val data_write_idx = Mux(hit, hit_idx, enq_idx)
85    data_mem.write(data_write_idx, io.write_data, update_way_mask)
86  }
87  replacer_touch_ways(0).valid := io.wen
88  replacer_touch_ways(0).bits := Mux(hit, hit_idx, enq_idx)
89  replacer.access(replacer_touch_ways)
90
91  // update valids
92  for (i <- 0 until numWays) {
93    when (io.wen) {
94      when (hit) {
95        when (update_way_mask(i)) {
96          valids(hit_idx)(i) := true.B
97        }
98      }.otherwise {
99        ever_written(enq_idx) := true.B
100        valids(enq_idx)(i) := false.B
101        when (update_way_mask(i)) {
102          valids(enq_idx)(i) := true.B
103        }
104      }
105    }
106  }
107
108  val enq_en = io.wen && !hit
109  idx_tag_cam.io.w.valid := enq_en
110  idx_tag_cam.io.w.bits.index := enq_idx
111  idx_tag_cam.io.w.bits.data(io.write_idx, io.write_tag.getOrElse(0.U))
112
113  XSPerfAccumulate("wrbypass_hit",  io.wen &&  hit)
114  XSPerfAccumulate("wrbypass_miss", io.wen && !hit)
115
116  XSDebug(io.wen && hit,  p"wrbypass hit entry #${hit_idx}, idx ${io.write_idx}" +
117    p"tag ${io.write_tag.getOrElse(0.U)}data ${io.write_data}\n")
118  XSDebug(io.wen && !hit, p"wrbypass enq entry #${enq_idx}, idx ${io.write_idx}" +
119    p"tag ${io.write_tag.getOrElse(0.U)}data ${io.write_data}\n")
120}
121