1package xiangshan.frontend 2 3import chisel3._ 4import chisel3.util._ 5import device.RAMHelper 6import xiangshan._ 7import utils._ 8 9trait HasIFUConst { this: XSModule => 10 val resetVector = 0x80000000L//TODO: set reset vec 11 val groupAlign = log2Up(FetchWidth * 4 * 2) 12 def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W)) 13 // each 1 bit in mask stands for 2 Bytes 14 def mask(pc: UInt): UInt = (Fill(PredictWidth * 2, 1.U(1.W)) >> pc(groupAlign - 1, 1))(PredictWidth - 1, 0) 15 def snpc(pc: UInt): UInt = pc + (PopCount(mask(pc)) << 1) 16 17 val IFUDebug = true 18} 19 20class IFUIO extends XSBundle 21{ 22 val fetchPacket = DecoupledIO(new FetchPacket) 23 val redirect = Flipped(ValidIO(new Redirect)) 24 val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 25 val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 26 val icacheReq = DecoupledIO(new FakeIcacheReq) 27 val icacheResp = Flipped(DecoupledIO(new FakeIcacheResp)) 28 val icacheFlush = Output(UInt(2.W)) 29} 30 31 32class IFU extends XSModule with HasIFUConst 33{ 34 val io = IO(new IFUIO) 35 val bpu = BPU(EnableBPU) 36 val pd = Module(new PreDecode) 37 38 val if2_redirect, if3_redirect, if4_redirect = WireInit(false.B) 39 val if1_flush, if2_flush, if3_flush, if4_flush = WireInit(false.B) 40 41 if4_flush := io.redirect.valid 42 if3_flush := if4_flush || if4_redirect 43 if2_flush := if3_flush || if3_redirect 44 if1_flush := if2_flush || if2_redirect 45 46 //********************** IF1 ****************************// 47 val if1_valid = !reset.asBool 48 val if1_npc = WireInit(0.U(VAddrBits.W)) 49 val if2_ready = WireInit(false.B) 50 val if1_fire = if1_valid && (if2_ready || if1_flush) && io.icacheReq.ready 51 52 // val extHist = VecInit(Fill(ExtHistoryLength, RegInit(0.U(1.W)))) 53 val extHist = RegInit(VecInit(Seq.fill(ExtHistoryLength)(0.U(1.W)))) 54 val headPtr = RegInit(0.U(log2Up(ExtHistoryLength).W)) 55 val shiftPtr = WireInit(false.B) 56 val newPtr = Wire(UInt(log2Up(ExtHistoryLength).W)) 57 val ptr = Mux(shiftPtr, newPtr, headPtr) 58 when (shiftPtr) { headPtr := newPtr } 59 val hist = Wire(Vec(HistoryLength, UInt(1.W))) 60 for (i <- 0 until HistoryLength) { 61 hist(i) := extHist(ptr + i.U) 62 } 63 64 newPtr := headPtr 65 shiftPtr := false.B 66 67 //********************** IF2 ****************************// 68 val if2_valid = RegEnable(next = if1_valid, init = false.B, enable = if1_fire) 69 val if3_ready = WireInit(false.B) 70 val if2_fire = if2_valid && if3_ready && !if2_flush 71 val if2_pc = RegEnable(next = if1_npc, init = resetVector.U, enable = if1_fire) 72 val if2_snpc = snpc(if2_pc) 73 val if2_histPtr = RegEnable(ptr, if1_fire) 74 if2_ready := if2_fire || !if2_valid || if2_flush 75 when (if2_flush) { if2_valid := if1_fire } 76 .elsewhen (if1_fire) { if2_valid := if1_valid } 77 .elsewhen (if2_fire) { if2_valid := false.B } 78 79 when (RegNext(reset.asBool) && !reset.asBool) { 80 if1_npc := resetVector.U(VAddrBits.W) 81 }.elsewhen (if2_fire) { 82 if1_npc := if2_snpc 83 }.otherwise { 84 if1_npc := RegNext(if1_npc) 85 } 86 87 val if2_bp = bpu.io.out(0).bits 88 if2_redirect := if2_fire && bpu.io.out(0).valid && if2_bp.redirect// && !if2_bp.saveHalfRVI 89 when (if2_redirect) { 90 if1_npc := if2_bp.target 91 } 92 93 when (if2_fire && (if2_bp.takenOnBr || if2_bp.hasNotTakenBrs)) { 94 shiftPtr := true.B 95 newPtr := headPtr - 1.U 96 hist(0) := if2_bp.takenOnBr.asUInt 97 extHist(newPtr) := if2_bp.takenOnBr.asUInt 98 } 99 100 // repair histptr when if4 finds a not taken branch which is 101 // not recorded in uBTB or BTB 102 val if4_shiftWithoutRedirect = WireInit(false.B) 103 104 //********************** IF3 ****************************// 105 val if3_valid = RegEnable(next = if2_valid, init = false.B, enable = if2_fire) 106 val if4_ready = WireInit(false.B) 107 val if3_fire = if3_valid && if4_ready && io.icacheResp.valid && !if3_flush 108 val if3_pc = RegEnable(if2_pc, if2_fire) 109 val if3_histPtr = RegEnable(if2_histPtr - if4_shiftWithoutRedirect.asUInt, if2_fire) 110 if3_ready := if3_fire || !if3_valid || if3_flush 111 when (if3_flush) { if3_valid := false.B } 112 .elsewhen (if2_fire) { if3_valid := if2_valid } 113 .elsewhen (if3_fire) { if3_valid := false.B } 114 115 val if3_bp = bpu.io.out(1).bits 116 117 class PrevHalfInstr extends Bundle { 118 val valid = Bool() 119 val taken = Bool() 120 val fetchpc = UInt(VAddrBits.W) // only for debug 121 val idx = UInt(VAddrBits.W) // only for debug 122 val pc = UInt(VAddrBits.W) 123 val target = UInt(VAddrBits.W) 124 val instr = UInt(16.W) 125 val takenOnBr = Bool() 126 } 127 128 val if3_prevHalfInstr = RegInit(0.U.asTypeOf(new PrevHalfInstr)) 129 val if4_prevHalfInstr = Wire(new PrevHalfInstr) 130 when (if4_prevHalfInstr.valid) { 131 if3_prevHalfInstr := if4_prevHalfInstr 132 } 133 val prevHalfInstr = Mux(if4_prevHalfInstr.valid, if4_prevHalfInstr, if3_prevHalfInstr) 134 135 val if3_hasPrevHalfInstr = prevHalfInstr.valid && (prevHalfInstr.pc + 2.U) === if3_pc 136 if3_redirect := if3_fire && bpu.io.out(1).valid && (if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.redirect/* && !if3_bp.saveHalfRVI*/ ) 137 when (if3_redirect) { 138 if1_npc := Mux(if3_hasPrevHalfInstr && prevHalfInstr.taken, prevHalfInstr.target, if3_bp.target) 139 } 140 141 when (if3_fire && if3_redirect) { 142 shiftPtr := true.B 143 newPtr := Mux(if3_hasPrevHalfInstr && prevHalfInstr.takenOnBr || if3_bp.takenOnBr || if3_bp.hasNotTakenBrs, if3_histPtr - 1.U, if3_histPtr) 144 hist(0) := Mux(if3_hasPrevHalfInstr && prevHalfInstr.takenOnBr || if3_bp.takenOnBr || if3_bp.hasNotTakenBrs, 145 (if3_hasPrevHalfInstr && prevHalfInstr.takenOnBr || if3_bp.takenOnBr).asUInt, 146 extHist(if3_histPtr)) 147 extHist(newPtr) := Mux(if3_hasPrevHalfInstr && prevHalfInstr.takenOnBr || if3_bp.takenOnBr || if3_bp.hasNotTakenBrs, 148 (if3_hasPrevHalfInstr && prevHalfInstr.takenOnBr || if3_bp.takenOnBr).asUInt, 149 extHist(if3_histPtr)) 150 } 151 152 153 154 // val prev_half_valid = RegInit(false.B) 155 // val prev_half_redirect = RegInit(false.B) 156 // val prev_half_fetchpc = Reg(UInt(VAddrBits.W)) 157 // val prev_half_idx = Reg(UInt(log2Up(PredictWidth).W)) 158 // val prev_half_tgt = Reg(UInt(VAddrBits.W)) 159 // val prev_half_taken = RegInit(false.B) 160 // val prev_half_instr = Reg(UInt(16.W)) 161 // when (if3_flush) { 162 // prev_half_valid := false.B 163 // prev_half_redirect := false.B 164 // }.elsewhen (if3_fire && if3_bp.saveHalfRVI) { 165 // prev_half_valid := true.B 166 // prev_half_redirect := if3_bp.redirect && bpu.io.out(1).valid 167 // prev_half_fetchpc := if3_pc 168 // val idx = Mux(if3_bp.redirect && bpu.io.out(1).valid, if3_bp.jmpIdx, PopCount(mask(if3_pc)) - 1.U) 169 // prev_half_idx := idx 170 // prev_half_tgt := if3_bp.target 171 // prev_half_taken := if3_bp.taken 172 // prev_half_instr := pd.io.out.instrs(idx)(15, 0) 173 // }.elsewhen (if3_fire) { 174 // prev_half_valid := false.B 175 // prev_half_redirect := false.B 176 // } 177 178 // when (bpu.io.out(1).valid && if3_fire) { 179 // when (prev_half_valid && prev_half_taken) { 180 // if3_redirect := true.B 181 // if1_npc := prev_half_tgt 182 // shiftPtr := true.B 183 // newPtr := if3_histPtr - 1.U 184 // hist(0) := 1.U 185 // extHist(newPtr) := 1.U 186 // }.elsewhen (if3_bp.redirect && !if3_bp.saveHalfRVI) { 187 // if3_redirect := true.B 188 // if1_npc := if3_bp.target 189 // shiftPtr := true.B 190 // newPtr := Mux(if3_bp.taken || if3_bp.hasNotTakenBrs, if3_histPtr - 1.U, if3_histPtr) 191 // hist(0) := Mux(if3_bp.taken || if3_bp.hasNotTakenBrs, if3_bp.taken.asUInt, extHist(if3_histPtr)) 192 // extHist(newPtr) := Mux(if3_bp.taken || if3_bp.hasNotTakenBrs, if3_bp.taken.asUInt, extHist(if3_histPtr)) 193 // }.elsewhen (if3_bp.saveHalfRVI) { 194 // if3_redirect := true.B 195 // if1_npc := snpc(if3_pc) 196 // shiftPtr := true.B 197 // newPtr := Mux(if3_bp.hasNotTakenBrs, if3_histPtr - 1.U, if3_histPtr) 198 // hist(0) := Mux(if3_bp.hasNotTakenBrs, 0.U, extHist(if3_histPtr)) 199 // extHist(newPtr) := Mux(if3_bp.hasNotTakenBrs, 0.U, extHist(if3_histPtr)) 200 // }.otherwise { 201 // if3_redirect := false.B 202 // } 203 // }.otherwise { 204 // if3_redirect := false.B 205 // } 206 207 208 //********************** IF4 ****************************// 209 val if4_pd = RegEnable(pd.io.out, if3_fire) 210 val if4_valid = RegInit(false.B) 211 val if4_fire = if4_valid && io.fetchPacket.ready 212 val if4_pc = RegEnable(if3_pc, if3_fire) 213 val if4_histPtr = RegEnable(if3_histPtr - if4_shiftWithoutRedirect.asUInt, if3_fire) 214 if4_ready := (if4_fire || !if4_valid || if4_flush) && GTimer() > 500.U 215 when (if4_flush) { if4_valid := false.B } 216 .elsewhen (if3_fire) { if4_valid := if3_valid } 217 .elsewhen(if4_fire) { if4_valid := false.B } 218 219 val if4_bp = Wire(new BranchPrediction) 220 if4_bp := bpu.io.out(2).bits 221 222 val if4_cfi_jal = if4_pd.instrs(if4_bp.jmpIdx) 223 val if4_cfi_jal_tgt = if4_pd.pc(if4_bp.jmpIdx) + Mux(if4_pd.pd(if4_bp.jmpIdx).isRVC, 224 SignExt(Cat(if4_cfi_jal(12), if4_cfi_jal(8), if4_cfi_jal(10, 9), if4_cfi_jal(6), if4_cfi_jal(7), if4_cfi_jal(2), if4_cfi_jal(11), if4_cfi_jal(5, 3), 0.U(1.W)), XLEN), 225 SignExt(Cat(if4_cfi_jal(31), if4_cfi_jal(19, 12), if4_cfi_jal(20), if4_cfi_jal(30, 21), 0.U(1.W)), XLEN)) 226 if4_bp.target := Mux(if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken, if4_cfi_jal_tgt, bpu.io.out(2).bits.target) 227 if4_bp.redirect := bpu.io.out(2).bits.redirect || if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken && if4_cfi_jal_tgt =/= bpu.io.out(2).bits.target 228 229 if4_prevHalfInstr := 0.U.asTypeOf(new PrevHalfInstr) 230 when (bpu.io.out(2).valid && if4_fire && if4_bp.saveHalfRVI) { 231 if4_prevHalfInstr.valid := true.B 232 if4_prevHalfInstr.taken := if4_bp.taken 233 if4_prevHalfInstr.takenOnBr := if4_bp.takenOnBr 234 if4_prevHalfInstr.fetchpc := if4_pc 235 if4_prevHalfInstr.idx := PopCount(mask(if4_pc)) - 1.U 236 if4_prevHalfInstr.pc := if4_pd.pc(if4_prevHalfInstr.idx) 237 if4_prevHalfInstr.target := if4_bp.target 238 if4_prevHalfInstr.instr := if4_pd.instrs(if4_prevHalfInstr.idx)(15, 0) 239 } 240 241 when (bpu.io.out(2).valid && if4_fire && if4_bp.redirect) { 242 if4_redirect := true.B 243 shiftPtr := true.B 244 newPtr := Mux(if4_bp.takenOnBr || if4_bp.hasNotTakenBrs, if4_histPtr - 1.U, if4_histPtr) 245 hist(0) := Mux(if4_bp.takenOnBr || if4_bp.hasNotTakenBrs, if4_bp.takenOnBr.asUInt, extHist(if4_histPtr)) 246 extHist(newPtr) := Mux(if4_bp.takenOnBr || if4_bp.hasNotTakenBrs, if4_bp.takenOnBr.asUInt, extHist(if4_histPtr)) 247 when (if4_bp.saveHalfRVI) { 248 if1_npc := snpc(if4_pc) 249 }.otherwise { 250 if1_npc := if4_bp.target 251 } 252 }.elsewhen (bpu.io.out(2).valid && if4_fire/* && !if4_bp.redirect*/) { 253 when (if4_bp.saveHalfRVI && if4_bp.takenOnBr) { 254 if4_redirect := true.B 255 if1_npc := snpc(if4_pc) 256 shiftPtr := true.B 257 newPtr := if4_histPtr - 1.U 258 hist(0) := 1.U 259 extHist(newPtr) := 1.U 260 }.elsewhen (if4_bp.saveHalfRVI && if4_bp.taken) { 261 if4_redirect := true.B 262 if1_npc := snpc(if4_pc) 263 shiftPtr := true.B 264 newPtr := if4_histPtr 265 hist(0) := extHist(if4_histPtr) 266 extHist(newPtr) := extHist(if4_histPtr) 267 }.otherwise { 268 if4_redirect := false.B 269 when (if4_bp.takenOnBr || if4_bp.hasNotTakenBrs) { 270 shiftPtr := true.B 271 if4_shiftWithoutRedirect := true.B 272 newPtr := if4_histPtr - 1.U 273 hist(0) := if4_bp.takenOnBr.asUInt 274 extHist(newPtr) := if4_bp.takenOnBr.asUInt 275 } 276 } 277 }.otherwise { 278 if4_redirect := false.B 279 } 280 281 282 283 // when (bpu.io.out(2).valid && if4_fire && if4_bp.redirect) { 284 // when (!if4_bp.saveHalfRVI) { 285 // if4_redirect := true.B 286 // // if1_npc := if4_bp.target 287 // if1_npc := Mux(if4_bp.taken, if4_bp.target, snpc(if4_pc)) 288 289 // shiftPtr := true.B 290 // newPtr := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_histPtr - 1.U, if4_histPtr) 291 // hist(0) := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_bp.taken.asUInt, extHist(if4_histPtr)) 292 // extHist(newPtr) := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_bp.taken.asUInt, extHist(if4_histPtr)) 293 294 // }.otherwise { 295 // if4_redirect := true.B 296 // if1_npc := snpc(if4_pc) 297 298 // prev_half_valid := true.B 299 // prev_half_redirect := true.B 300 // prev_half_fetchpc := if4_pc 301 // val idx = PopCount(mask(if4_pc)) - 1.U 302 // prev_half_idx := idx 303 // prev_half_tgt := if4_bp.target 304 // prev_half_taken := if4_bp.taken 305 // prev_half_instr := if4_pd.instrs(idx)(15, 0) 306 307 // shiftPtr := true.B 308 // newPtr := Mux(if4_bp.hasNotTakenBrs, if4_histPtr - 1.U, if4_histPtr) 309 // hist(0) := Mux(if4_bp.hasNotTakenBrs, 0.U, extHist(if4_histPtr)) 310 // extHist(newPtr) := Mux(if4_bp.hasNotTakenBrs, 0.U, extHist(if4_histPtr)) 311 // } 312 // }.otherwise { 313 // if4_redirect := false.B 314 // } 315 316 when (io.outOfOrderBrInfo.valid && io.outOfOrderBrInfo.bits.isMisPred) { 317 val b = io.outOfOrderBrInfo.bits 318 val oldPtr = b.brInfo.histPtr 319 shiftPtr := true.B 320 when (!b.pd.isBr && !b.brInfo.sawNotTakenBranch) { 321 // If mispredicted cfi is not a branch, 322 // and there wasn't any not taken branch before it, 323 // we should only recover the pointer to an unshifted state 324 newPtr := oldPtr 325 }.otherwise { 326 newPtr := oldPtr - 1.U 327 hist(0) := Mux(b.pd.isBr, b.taken, 0.U) 328 extHist(newPtr) := Mux(b.pd.isBr, b.taken, 0.U) 329 } 330 } 331 332 when (io.redirect.valid) { 333 if1_npc := io.redirect.bits.target 334 } 335 336 io.icacheReq.valid := if1_valid && if2_ready 337 io.icacheReq.bits.addr := if1_npc 338 io.icacheResp.ready := if3_ready 339 io.icacheFlush := Cat(if3_flush, if2_flush) 340 341 val inOrderBrHist = Wire(Vec(HistoryLength, UInt(1.W))) 342 (0 until HistoryLength).foreach(i => inOrderBrHist(i) := extHist(i.U + io.inOrderBrInfo.bits.brInfo.histPtr)) 343 bpu.io.inOrderBrInfo.valid := io.inOrderBrInfo.valid 344 bpu.io.inOrderBrInfo.bits := BranchUpdateInfoWithHist(io.inOrderBrInfo.bits, inOrderBrHist.asUInt) 345 bpu.io.outOfOrderBrInfo.valid := io.outOfOrderBrInfo.valid 346 bpu.io.outOfOrderBrInfo.bits := BranchUpdateInfoWithHist(io.outOfOrderBrInfo.bits, inOrderBrHist.asUInt) // Dont care about hist 347 348 // bpu.io.flush := Cat(if4_flush, if3_flush, if2_flush) 349 bpu.io.flush := VecInit(if2_flush, if3_flush, if4_flush) 350 bpu.io.in.valid := if1_fire 351 bpu.io.in.bits.pc := if1_npc 352 bpu.io.in.bits.hist := hist.asUInt 353 bpu.io.in.bits.inMask := mask(if1_npc) 354 bpu.io.out(0).ready := if2_fire 355 bpu.io.out(1).ready := if3_fire 356 bpu.io.out(2).ready := if4_fire 357 bpu.io.predecode.valid := if4_valid 358 bpu.io.predecode.bits.mask := if4_pd.mask 359 bpu.io.predecode.bits.pd := if4_pd.pd 360 bpu.io.predecode.bits.isFetchpcEqualFirstpc := if4_pc === if4_pd.pc(0) 361 bpu.io.branchInfo.ready := if4_fire 362 363 pd.io.in := io.icacheResp.bits 364 pd.io.prev.valid := if3_hasPrevHalfInstr 365 pd.io.prev.bits := prevHalfInstr.instr 366 367 io.fetchPacket.valid := if4_valid && !io.redirect.valid 368 io.fetchPacket.bits.instrs := if4_pd.instrs 369 io.fetchPacket.bits.mask := if4_pd.mask & (Fill(PredictWidth, !if4_bp.taken) | (Fill(PredictWidth, 1.U(1.W)) >> (~if4_bp.jmpIdx))) 370 io.fetchPacket.bits.pc := if4_pd.pc 371 (0 until PredictWidth).foreach(i => io.fetchPacket.bits.pnpc(i) := if4_pd.pc(i) + Mux(if4_pd.pd(i).isRVC, 2.U, 4.U)) 372 when (if4_bp.taken) { 373 io.fetchPacket.bits.pnpc(if4_bp.jmpIdx) := if4_bp.target 374 } 375 io.fetchPacket.bits.brInfo := bpu.io.branchInfo.bits 376 (0 until PredictWidth).foreach(i => io.fetchPacket.bits.brInfo(i).histPtr := if4_histPtr) 377 io.fetchPacket.bits.pd := if4_pd.pd 378 379 // debug info 380 if (IFUDebug) { 381 XSDebug(RegNext(reset.asBool) && !reset.asBool, "Reseting...\n") 382 XSDebug(io.icacheFlush(0).asBool, "Flush icache stage2...\n") 383 XSDebug(io.icacheFlush(1).asBool, "Flush icache stage3...\n") 384 XSDebug(io.redirect.valid, "Redirect from backend! isExcp=%d isMisPred=%d isReplay=%d pc=%x\n", 385 io.redirect.bits.isException, io.redirect.bits.isMisPred, io.redirect.bits.isReplay, io.redirect.bits.pc) 386 XSDebug(io.redirect.valid, p"Redirect from backend! target=${Hexadecimal(io.redirect.bits.target)} brTag=${io.redirect.bits.brTag}\n") 387 388 XSDebug("[IF1] v=%d fire=%d flush=%d pc=%x ptr=%d mask=%b\n", if1_valid, if1_fire, if1_flush, if1_npc, ptr, mask(if1_npc)) 389 XSDebug("[IF2] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d snpc=%x\n", if2_valid, if2_ready, if2_fire, if2_redirect, if2_flush, if2_pc, if2_histPtr, if2_snpc) 390 XSDebug("[IF3] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d\n", if3_valid, if3_ready, if3_fire, if3_redirect, if3_flush, if3_pc, if3_histPtr) 391 XSDebug("[IF4] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d\n", if4_valid, if4_ready, if4_fire, if4_redirect, if4_flush, if4_pc, if4_histPtr) 392 393 XSDebug("[IF1][icacheReq] v=%d r=%d addr=%x\n", io.icacheReq.valid, io.icacheReq.ready, io.icacheReq.bits.addr) 394 XSDebug("[IF1][ghr] headPtr=%d shiftPtr=%d newPtr=%d ptr=%d\n", headPtr, shiftPtr, newPtr, ptr) 395 XSDebug("[IF1][ghr] hist=%b\n", hist.asUInt) 396 XSDebug("[IF1][ghr] extHist=%b\n\n", extHist.asUInt) 397 398 XSDebug("[IF2][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n\n", if2_bp.redirect, if2_bp.taken, if2_bp.jmpIdx, if2_bp.hasNotTakenBrs, if2_bp.target, if2_bp.saveHalfRVI) 399 400 XSDebug("[IF3][icacheResp] v=%d r=%d pc=%x mask=%b\n", io.icacheResp.valid, io.icacheResp.ready, io.icacheResp.bits.pc, io.icacheResp.bits.mask) 401 XSDebug("[IF3][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if3_bp.redirect, if3_bp.taken, if3_bp.jmpIdx, if3_bp.hasNotTakenBrs, if3_bp.target, if3_bp.saveHalfRVI) 402 // XSDebug("[IF3][prevHalfInstr] v=%d redirect=%d fetchpc=%x idx=%d tgt=%x taken=%d instr=%x\n\n", 403 // prev_half_valid, prev_half_redirect, prev_half_fetchpc, prev_half_idx, prev_half_tgt, prev_half_taken, prev_half_instr) 404 XSDebug("[IF3][ prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x\n", 405 prevHalfInstr.valid, prevHalfInstr.taken, prevHalfInstr.fetchpc, prevHalfInstr.idx, prevHalfInstr.pc, prevHalfInstr.target, prevHalfInstr.instr) 406 XSDebug("[IF3][if3_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x\n\n", 407 if3_prevHalfInstr.valid, if3_prevHalfInstr.taken, if3_prevHalfInstr.fetchpc, if3_prevHalfInstr.idx, if3_prevHalfInstr.pc, if3_prevHalfInstr.target, if3_prevHalfInstr.instr) 408 409 410 XSDebug("[IF4][predecode] mask=%b\n", if4_pd.mask) 411 XSDebug("[IF4][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if4_bp.redirect, if4_bp.taken, if4_bp.jmpIdx, if4_bp.hasNotTakenBrs, if4_bp.target, if4_bp.saveHalfRVI) 412 XSDebug(if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken, "[IF4] cfi is jal! instr=%x target=%x\n", if4_cfi_jal, if4_cfi_jal_tgt) 413 XSDebug("[IF4][if4_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x\n", 414 if4_prevHalfInstr.valid, if4_prevHalfInstr.taken, if4_prevHalfInstr.fetchpc, if4_prevHalfInstr.idx, if4_prevHalfInstr.pc, if4_prevHalfInstr.target, if4_prevHalfInstr.instr) 415 XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] v=%d r=%d mask=%b\n", io.fetchPacket.valid, io.fetchPacket.ready, io.fetchPacket.bits.mask) 416 for (i <- 0 until PredictWidth) { 417 XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] %b %x pc=%x pnpc=%x pd: rvc=%d brType=%b call=%d ret=%d\n", 418 io.fetchPacket.bits.mask(i), 419 io.fetchPacket.bits.instrs(i), 420 io.fetchPacket.bits.pc(i), 421 io.fetchPacket.bits.pnpc(i), 422 io.fetchPacket.bits.pd(i).isRVC, 423 io.fetchPacket.bits.pd(i).brType, 424 io.fetchPacket.bits.pd(i).isCall, 425 io.fetchPacket.bits.pd(i).isRet 426 ) 427 } 428 } 429}