1package xiangshan.frontend 2 3import chisel3._ 4import chisel3.util._ 5import device.RAMHelper 6import xiangshan._ 7import utils._ 8 9trait HasIFUConst { this: XSModule => 10 val resetVector = 0x80000000L//TODO: set reset vec 11 val groupAlign = log2Up(FetchWidth * 4 * 2) 12 def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W)) 13 // each 1 bit in mask stands for 2 Bytes 14 def mask(pc: UInt): UInt = (Fill(PredictWidth * 2, 1.U(1.W)) >> pc(groupAlign - 1, 1))(PredictWidth - 1, 0) 15 def snpc(pc: UInt): UInt = pc + (PopCount(mask(pc)) << 1) 16} 17 18class IFUIO extends XSBundle 19{ 20 val fetchPacket = DecoupledIO(new FetchPacket) 21 val redirect = Flipped(ValidIO(new Redirect)) 22 val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 23 val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 24 val icacheReq = DecoupledIO(new FakeIcacheReq) 25 val icacheResp = Flipped(DecoupledIO(new FakeIcacheResp)) 26 val icacheFlush = Output(UInt(2.W)) 27} 28 29 30class IFU extends XSModule with HasIFUConst 31{ 32 val io = IO(new IFUIO) 33 val bpu = if (EnableBPD) Module(new BPU) else Module(new FakeBPU) 34 val pd = Module(new PreDecode) 35 36 val if2_redirect, if3_redirect, if4_redirect = WireInit(false.B) 37 val if1_flush, if2_flush, if3_flush, if4_flush = WireInit(false.B) 38 39 if4_flush := io.redirect.valid 40 if3_flush := if4_flush || if4_redirect 41 if2_flush := if3_flush || if3_redirect 42 if1_flush := if2_flush || if2_redirect 43 44 //********************** IF1 ****************************// 45 val if1_valid = !reset.asBool 46 val if1_npc = WireInit(0.U(VAddrBits.W)) 47 val if2_ready = WireInit(false.B) 48 val if1_fire = if1_valid && (if2_ready || if1_flush) && io.icacheReq.ready 49 50 val extHist = RegInit(Vec(ExtHistoryLength, 0.U(1.W))) 51 val headPtr = RegInit(0.U(log2Up(ExtHistoryLength).W)) 52 val shiftPtr = WireInit(false.B) 53 val newPtr = Wire(UInt(log2Up(ExtHistoryLength).W)) 54 val ptr = Mux(shiftPtr, newPtr, headPtr) 55 when (shiftPtr) { headPtr := newPtr } 56 val hist = Wire(Vec(HistoryLength, UInt(1.W))) 57 for (i <- 0 until HistoryLength) { 58 hist(i) := extHist(ptr + i.U) 59 } 60 61 newPtr := headPtr 62 shiftPtr := false.B 63 64 //********************** IF2 ****************************// 65 val if2_valid = RegEnable(next = if1_valid, init = false.B, enable = if1_fire) 66 val if3_ready = WireInit(false.B) 67 val if2_fire = if2_valid && if3_ready 68 val if2_pc = RegEnable(next = if1_npc, init = resetVector.U, enable = if1_fire) 69 val if2_snpc = snpc(if2_pc) 70 val if2_histPtr = RegEnable(ptr, if1_fire) 71 if2_ready := if2_fire || !if2_valid 72 when (if2_flush) { if2_valid := if1_fire } 73 74 when (RegNext(reset.asBool) && !reset.asBool) { 75 if1_npc := resetVector.U(VAddrBits.W) 76 }.elsewhen (if2_fire) { 77 if1_npc := if2_snpc 78 }.otherwise { 79 if1_npc := RegNext(if1_npc) 80 } 81 82 val if2_bp = bpu.io.out(0).bits 83 if2_redirect := if2_fire && bpu.io.out(0).valid && if2_bp.redirect && !if2_bp.saveHalfRVI 84 when (if2_redirect) { 85 if1_npc := if2_bp.target 86 } 87 88 when (if2_fire && (if2_bp.taken || if2_bp.hasNotTakenBrs)) { 89 shiftPtr := true.B 90 newPtr := headPtr - 1.U 91 hist(0) := if2_bp.taken.asUInt 92 extHist(newPtr) := if2_bp.taken.asUInt 93 } 94 95 //********************** IF3 ****************************// 96 val if3_valid = RegEnable(next = if2_valid, init = false.B, enable = if2_fire) 97 val if4_ready = WireInit(false.B) 98 val if3_fire = if3_valid && if4_ready && io.icacheResp.valid 99 val if3_pc = RegEnable(if2_pc, if2_fire) 100 val if3_histPtr = RegEnable(if2_histPtr, if2_fire) 101 if3_ready := if3_fire || !if3_valid 102 when (if3_flush) { if3_valid := false.B } 103 104 val if3_bp = bpu.io.out(1).bits 105 val prev_half_valid = RegInit(false.B) 106 val prev_half_redirect = RegInit(false.B) 107 val prev_half_fetchpc = Reg(UInt(VAddrBits.W)) 108 val prev_half_idx = Reg(UInt(log2Up(PredictWidth).W)) 109 val prev_half_tgt = Reg(UInt(VAddrBits.W)) 110 val prev_half_taken = RegInit(false.B) 111 val prev_half_instr = Reg(UInt(16.W)) 112 when (if3_flush) { 113 prev_half_valid := false.B 114 prev_half_redirect := false.B 115 }.elsewhen (if3_fire && if3_bp.saveHalfRVI) { 116 prev_half_valid := true.B 117 prev_half_redirect := if3_bp.redirect && bpu.io.out(1).valid 118 prev_half_fetchpc := if3_pc 119 val idx = Mux(if3_bp.redirect && bpu.io.out(1).valid, if3_bp.jmpIdx, PopCount(mask(if3_pc)) - 1.U) 120 prev_half_idx := idx 121 prev_half_tgt := if3_bp.target 122 prev_half_taken := if3_bp.taken 123 prev_half_instr := pd.io.out.instrs(idx)(15, 0) 124 }.elsewhen (if3_fire) { 125 prev_half_valid := false.B 126 prev_half_redirect := false.B 127 } 128 129 // if3_redirect := if3_fire && (prev_half_valid && prev_half_taken || bpu.io.out(1).valid && if3_bp.redirect && !if3_bp.saveHalfRVI) 130 // when (if3_redirect) { 131 // if1_npc := Mux(prev_half_valid && prev_half_redirect, prev_half_tgt, if3_bp.target) 132 // } 133 134 when (bpu.io.out(1).valid && if3_fire) { 135 when (prev_half_valid && prev_half_taken) { 136 if3_redirect := true.B 137 if1_npc := prev_half_tgt 138 shiftPtr := true.B 139 newPtr := if3_histPtr - 1.U 140 hist(0) := 1.U 141 extHist(newPtr) := 1.U 142 }.elsewhen (if3_bp.redirect && !if3_bp.saveHalfRVI) { 143 if3_redirect := true.B 144 if1_npc := if3_bp.target 145 shiftPtr := true.B 146 newPtr := Mux(if3_bp.taken || if3_bp.hasNotTakenBrs, if3_histPtr - 1.U, if3_histPtr) 147 hist(0) := Mux(if3_bp.taken || if3_bp.hasNotTakenBrs, if3_bp.taken.asUInt, extHist(if3_histPtr)) 148 extHist(newPtr) := Mux(if3_bp.taken || if3_bp.hasNotTakenBrs, if3_bp.taken.asUInt, extHist(newPtr)) 149 }.elsewhen (if3_bp.saveHalfRVI) { 150 if3_redirect := true.B 151 if1_npc := snpc(if3_pc) 152 shiftPtr := true.B 153 newPtr := Mux(if3_bp.hasNotTakenBrs, if3_histPtr - 1.U, if3_histPtr) 154 hist(0) := Mux(if3_bp.hasNotTakenBrs, 0.U, extHist(if3_histPtr)) 155 extHist(newPtr) := Mux(if3_bp.hasNotTakenBrs, 0.U, extHist(newPtr)) 156 }.otherwise { 157 if3_redirect := false.B 158 } 159 }.otherwise { 160 if3_redirect := false.B 161 } 162 163 164 //********************** IF4 ****************************// 165 val if4_pd = RegEnable(pd.io.out, if3_fire) 166 // val if4_icacheResp = RegEnable(io.icacheResp.bits, if3_fire) 167 val if4_valid = RegEnable(next = if3_valid, init = false.B, enable = if3_fire) 168 val if4_fire = if4_valid && io.fetchPacket.ready 169 val if4_pc = RegEnable(if3_pc, if3_fire) 170 val if4_histPtr = RegEnable(if3_histPtr, if3_fire) 171 if4_ready := if4_fire || !if4_valid 172 when (if4_flush) { if4_valid := false.B } 173 174 val if4_bp = bpu.io.out(2).bits 175 176 when (bpu.io.out(2).valid && if4_fire && if4_pd.redirect) { 177 when (!if4_bp.saveHalfRVI) { 178 if4_redirect := true.B 179 if1_npc := if4_bp.target 180 181 shiftPtr := true.B 182 newPtr := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_histPtr - 1.U, if4_histPtr) 183 hist(0) := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_bp.taken.asUInt, extHist(if4_histPtr)) 184 extHist(newPtr) := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_bp.taken.asUInt, extHist(newPtr)) 185 186 }.otherwise { 187 if4_redirect := true.B 188 if1_npc := snpc(if4_pc) 189 190 prev_half_valid := true.B 191 prev_half_redirect := true.B 192 prev_half_fetchpc := if4_pc 193 val idx = PopCount(mask(if4_pc)) - 1.U 194 prev_half_idx := idx 195 prev_half_tgt := if4_bp.target 196 prev_half_taken := if4_bp.taken 197 prev_half_instr := if4_pd.io.out.instrs(idx)(15, 0) 198 199 shiftPtr := true.B 200 newPtr := Mux(if4_bp.hasNotTakenBrs, if4_histPtr - 1.U, if4_histPtr) 201 hist(0) := Mux(if4_bp.hasNotTakenBrs, 0.U, extHist(if4_histPtr)) 202 extHist(newPtr) := Mux(if4_np.hasNotTakenBrs, 0.U, extHist(newPtr)) 203 } 204 }.otherwise { 205 if4_redirect := false.B 206 } 207 208 when (io.outOfOrderBrInfo.valid) { 209 shiftPtr := true.B 210 newPtr := io.outOfOrderBrInfo.bits.brInfo.histPtr - 1.U 211 hist(0) := io.outOfOrderBrInfo.bits.taken 212 extHist(newPtr) := io.outOfOrderBrInfo.bits.taken 213 } 214 215 when (io.redirect.valid) { 216 if1_npc := io.redirect.bits.target 217 } 218 219 io.icacheReq.valid := if1_valid && if2_ready 220 io.icacheReq.bits.addr := if1_npc 221 io.icacheResp.ready := if3_valid && if4_ready 222 io.icacheFlush := Cat(if3_flush, if2_flush) 223 224 bpu.io.inOrderBrInfo <> io.inOrderBrInfo 225 bpu.io.flush := Cat(if4_flush, if3_flush, if2_flush) 226 bpu.io.in.valid := if1_fire 227 bpu.io.in.bits.pc := if1_npc 228 bpu.io.in.bits.hist := hist.asUInt 229 bpu.io.in.bits.inMask := mask(if1_npc) 230 bpu.io.out(0).ready := if2_fire 231 bpu.io.out(1).ready := if3_fire 232 bpu.io.out(2).ready := if4_fire 233 bpu.io.predecode.valid := if4_valid 234 bpu.io.predecode.bits.mask := if4_pd.mask 235 bpu.io.predecode.bits.pd := if4_pd.pd 236 bpu.io.branchInfo.ready := if4_fire 237 238 pd.io.in := io.icacheResp.bits 239 pd.io.prev.valid := prev_half_valid 240 pd.io.prev.bits := prev_half_instr 241 242 io.fetchPacket.valid := if4_valid && !io.redirect.valid 243 io.fetchPacket.bits.instrs := if4_pd.instrs 244 io.fetchPacket.bits.mask := if4_pd.mask & (Fill(PredictWidth, !if4_bp.taken) | (Fill(PredictWidth, 1.U(1.W)) >> (~if4_bp.jmpIdx))) 245 io.fetchPacket.bits.pc := if4_pd.pc 246 (0 until PredictWidth).foreach(i => io.fetchPacket.bits.pnpc(i) := if4_pd.pc(i) + Mux(if4_pd.pd(i).isRVC, 2.U, 4.U)) 247 when (if4_bp.taken) { 248 io.fetchPacket.bits.pnpc(if4_bp.jmpIdx) := if4_bp.target 249 } 250 io.fetchPacket.bits.brInfo := bpu.io.branchInfo.bits 251 (0 until PredictWidth).foreach(i => io.fetchPacket.bits.brInfo(i).histPtr := if4_histPtr) 252 io.fetchPacket.bits.pd := if4_pd.pd 253 254 // debug info 255 XSDebug(RegNext(reset.asBool) && !reset.asBool, "Reseting...\n") 256 XSDebug(io.icacheFlush(0).asBool, "Flush icache stage2...\n") 257 XSDebug(io.icacheFlush(1).asBool, "Flush icache stage3...\n") 258 XSDebug(io.redirect.valid, "Rediret from backend! isExcp=%d isMisPred=%d isReplay=%d pc=%x\n", 259 io.redirect.bits.isException, io.redirect.bits.isMisPred, io.redirect.bits.isReplay, io.redirect.bits.pc) 260 XSDebug(io.redirect.valid, p"Rediret from backend! target=${Hexadecimal(io.redirect.bits.target)} brTag=${io.redirect.bits.brTag}\n") 261 262 XSDebug("[IF1] v=%d fire=%d flush=%d pc=%x ptr=%d mask=%b\n", if1_valid, if1_fire, if1_flush, if1_npc, ptr, mask(if1_npc)) 263 XSDebug("[IF2] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d snpc=%x\n", if2_valid, if2_ready, if2_fire, if2_redirect, if2_flush, if2_pc, if2_histPtr, if2_snpc) 264 XSDebug("[IF3] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d\n", if3_valid, if3_ready, if3_fire, if3_redirect, if3_flush, if3_pc, if3_histPtr) 265 XSDebug("[IF4] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d\n", if4_valid, if4_ready, if4_fire, if4_redirect, if4_flush, if4_pc, if4_histPtr) 266 267 XSDebug("[IF1][icacheReq] v=%d r=%d addr=%x\n", io.icacheReq.valid, io.icacheReq.ready) 268 XSDebug("[IF1][ghr] headPtr=%d shiftPtr=%d newPtr=%d ptr=%d\n", headPtr, shiftPtr, newPtr, ptr) 269 XSDebug("[IF1][ghr] hist=%b\n", hist.asUInt) 270 XSDebug("[IF1][ghr] extHist=%b\n\n", extHist.asUInt) 271 272 XSDebug("[IF2][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n\n", if2_bp.redirect, if2_bp.taken, if2_bp.jmpIdx, if2_bp.hasNotTakenBrs, if2_bp.target, if2_bp.saveHalfRVI) 273 274 XSDebug("[IF3][icacheResp] v=%d r=%d pc=%x mask=%b\n", io.icacheResp.valid, io.icacheResp.ready, io.icacheResp.bits.pc, io.icacheResp.bits.mask) 275 XSDebug("[IF3][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if3_bp.redirect, if3_bp.taken, if3_bp.jmpIdx, if3_bp.hasNotTakenBrs, if3_bp.target, if3_bp.saveHalfRVI) 276 XSDebug("[IF3][prevHalfInstr] v=%d redirect=%d fetchpc=%x idx=%d tgt=%x taken=%d instr=%x\n\n", 277 prev_half_valid, prev_half_redirect, prev_half_fetchpc, prev_half_idx, prev_half_tgt, prev_half_taken, prev_half_instr) 278 279 XSDebug("[IF4][predecode] mask=%b\n", if4_pd.mask) 280 XSDebug("[IF4][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if4_bp.redirect, if4_bp.taken, if4_bp.jmpIdx, if4_bp.hasNotTakenBrs, if4_bp.target, if4_bp.saveHalfRVI) 281 XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] v=%d r=%d mask=%b\n", io.fetchPacket.valid, io.fetchPacket.ready, io.fetchPacket.bits.mask) 282 for (i <- 0 until PredictWidth) { 283 XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] %b %x pc=%x pnpc=%x pd: rvc=%d brType=%b call=%d ret=%d\n", 284 io.fetchPacket.bits.mask(i), 285 io.fetchPacket.bits.instrs(i), 286 io.fetchPacket.bits.pc(i), 287 io.fetchPacket.bits.pnpc(i), 288 io.fetchPacket.bits.pd(i).isRVC, 289 io.fetchPacket.bits.pd(i).brType, 290 io.fetchPacket.bits.pd(i).isCall, 291 io.fetchPacket.bits.pd(i).isRet 292 ) 293 } 294}