1package xiangshan.frontend 2 3import chisel3._ 4import chisel3.util._ 5import device.RAMHelper 6import xiangshan._ 7import xiangshan.utils._ 8 9trait HasIFUConst { this: XSModule => 10 val resetVector = 0x80000000L//TODO: set reset vec 11 12 val groupAlign = log2Up(FetchWidth * 4) 13 def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W)) 14 15} 16 17class IFUIO extends XSBundle 18{ 19 val fetchPacket = DecoupledIO(new FetchPacket) 20 val redirectInfo = Input(new RedirectInfo) 21 val icacheReq = DecoupledIO(new FakeIcacheReq) 22 val icacheResp = Flipped(DecoupledIO(new FakeIcacheResp)) 23} 24 25class FakeBPU extends XSModule{ 26 val io = IO(new Bundle() { 27 val in = new Bundle { val pc = Flipped(Valid(UInt(VAddrBits.W))) } 28 val btbOut = ValidIO(new BranchPrediction) 29 val tageOut = ValidIO(new BranchPrediction) 30 val predecode = Flipped(ValidIO(new Predecode)) 31 }) 32 33 io.btbOut.valid := false.B 34 io.btbOut.bits <> DontCare 35 io.tageOut.valid := false.B 36 io.tageOut.bits <> DontCare 37} 38 39 40 41class IFU extends XSModule with HasIFUConst 42{ 43 val io = IO(new IFUIO) 44 //val bpu = Module(new BPU) 45 val bpu = Module(new FakeBPU) 46 47 //------------------------- 48 // IF1 PC update 49 //------------------------- 50 //local 51 val if1_npc = WireInit(0.U(VAddrBits.W)) 52 val if1_valid = !reset.asBool //TODO:this is ugly 53 val if1_pc = RegInit(resetVector.U(VAddrBits.W)) 54 //next 55 val if2_ready = WireInit(false.B) 56 val if2_snpc = Cat(if1_pc(VAddrBits-1, groupAlign) + 1.U, 0.U(groupAlign.W)) 57 val if1_ready = if2_ready 58 59 //pipe fire 60 val if1_fire = if1_valid && if1_ready 61 val if1_pcUpdate = io.redirectInfo.flush() || if1_fire 62 63 when(RegNext(reset.asBool) && !reset.asBool){ 64 XSDebug("RESET....\n") 65 if1_npc := resetVector.U(VAddrBits.W) 66 } .otherwise{ 67 if1_npc := if2_snpc 68 } 69 70 when(if1_pcUpdate) 71 { 72 if1_pc := if1_npc 73 } 74 75 bpu.io.in.pc.valid := if1_valid 76 bpu.io.in.pc.bits := if1_npc 77 78 XSDebug("[IF1]if1_valid:%d || if1_npc:0x%x || if1_pcUpdate:%d if1_pc:0x%x || if2_ready:%d",if1_valid,if1_npc,if1_pcUpdate,if1_pc,if2_ready) 79 XSDebug(false,if1_fire,"------IF1->fire!!!") 80 XSDebug(false,true.B,"\n") 81 82 //------------------------- 83 // IF2 btb resonse 84 // icache visit 85 //------------------------- 86 //local 87 val if2_valid = RegEnable(next=if1_valid,init=false.B,enable=if1_fire) 88 val if2_pc = if1_pc 89 val if2_btb_taken = bpu.io.btbOut.valid 90 val if2_btb_insMask = bpu.io.btbOut.bits.instrValid 91 val if2_btb_target = bpu.io.btbOut.bits.target 92 93 //next 94 val if3_ready = WireInit(false.B) 95 96 //pipe fire 97 val if2_fire = if2_valid && if3_ready && io.icacheReq.fire() 98 if2_ready := (if2_fire) || !if2_valid 99 100 io.icacheReq.valid := if2_valid 101 io.icacheReq.bits.addr := groupPC(if2_pc) 102 io.icacheReq.bits.flush := io.redirectInfo.flush() 103 104 when(if2_valid && if2_btb_taken) 105 { 106 if1_npc := if2_btb_target 107 } 108 109 XSDebug("[IF2]if2_valid:%d || if2_pc:0x%x || if3_ready:%d ",if2_valid,if2_pc,if3_ready) 110 //XSDebug("[IF2-BPU-out]if2_btbTaken:%d || if2_btb_insMask:%b || if2_btb_target:0x%x \n",if2_btb_taken,if2_btb_insMask.asUInt,if2_btb_target) 111 XSDebug(false,if2_fire,"------IF2->fire!!!") 112 XSDebug(false,true.B,"\n") 113 XSDebug("[IF2-Icache-Req] icache_in_valid:%d icache_in_ready:%d\n",io.icacheReq.valid,io.icacheReq.ready) 114 115 //------------------------- 116 // IF3 icache hit check 117 //------------------------- 118 //local 119 val if3_valid = RegEnable(next=if2_valid,init=false.B,enable=if2_fire) 120 val if3_pc = RegEnable(if2_pc,if2_fire) 121 val if3_btb_target = RegEnable(if2_btb_target,if2_fire) 122 val if3_btb_taken = RegEnable(if2_btb_taken,if2_fire) 123 124 //next 125 val if4_ready = WireInit(false.B) 126 127 //pipe fire 128 val if3_fire = if3_valid && if4_ready 129 if3_ready := if3_fire || !if3_valid 130 131 132 XSDebug("[IF3]if3_valid:%d || if3_pc:0x%x || if4_ready:%d ",if3_valid,if3_pc,if4_ready) 133 XSDebug(false,if3_fire,"------IF3->fire!!!") 134 XSDebug(false,true.B,"\n") 135 136 //------------------------- 137 // IF4 icache resonse 138 // RAS result 139 // taget generate 140 //------------------------- 141 val if4_valid = RegEnable(next=if3_valid,init=false.B,enable=if3_fire) 142 val if4_pc = RegEnable(if3_pc,if3_fire) 143 val if4_btb_target = RegEnable(if3_btb_target,if3_fire) 144 val if4_btb_taken = RegEnable(if3_btb_taken,if3_fire) 145 val if4_tage_target = bpu.io.tageOut.bits.target 146 val if4_tage_taken = bpu.io.tageOut.valid 147 val if4_tage_insMask = bpu.io.tageOut.bits.instrValid 148 XSDebug("[IF4]if4_valid:%d || if4_pc:0x%x \n",if4_valid,if4_pc) 149 //XSDebug("[IF4-TAGE-out]if4_tage_taken:%d || if4_btb_insMask:%b || if4_tage_target:0x%x \n",if4_tage_taken,if4_tage_insMask.asUInt,if4_tage_target) 150 XSDebug("[IF4-ICACHE-RESP]icacheResp.valid:%d icacheResp.ready:%d\n",io.icacheResp.valid,io.icacheResp.ready) 151 152 when(if4_valid && io.icacheResp.fire() && if4_tage_taken) 153 { 154 if1_npc := if4_tage_target 155 } 156 157 158 //redirect: miss predict 159 when(io.redirectInfo.flush()){ 160 if1_npc := io.redirectInfo.redirect.target 161 if3_valid := false.B 162 if4_valid := false.B 163 } 164 XSDebug(io.redirectInfo.flush(),"[IFU-REDIRECT] target:0x%x \n",io.redirectInfo.redirect.target.asUInt) 165 166 //Output -> iBuffer 167 io.fetchPacket <> DontCare 168 if4_ready := io.fetchPacket.ready && (io.icacheResp.valid || !if4_valid) 169 io.fetchPacket.valid := if4_valid && !io.redirectInfo.flush() 170 io.fetchPacket.bits.instrs := io.icacheResp.bits.icacheOut 171 io.fetchPacket.bits.mask := Fill(FetchWidth*2, 1.U(1.W)) << if4_pc(2+log2Up(FetchWidth)-1, 1) 172 io.fetchPacket.bits.pc := if4_pc 173 174 //to BPU 175 bpu.io.predecode.valid := io.icacheResp.fire() && if4_valid 176 bpu.io.predecode.bits <> io.icacheResp.bits.predecode 177 bpu.io.predecode.bits.mask := Fill(FetchWidth, 1.U(1.W)) << if4_pc(2+log2Up(FetchWidth)-1, 2) //TODO: consider RVC 178 179 io.icacheResp.ready := io.fetchPacket.ready 180 181} 182 183