1package xiangshan.frontend 2 3import chisel3._ 4import chisel3.util._ 5import chisel3.util.experimental.BoringUtils 6import device.RAMHelper 7import xiangshan._ 8import utils._ 9import xiangshan.cache._ 10import chisel3.ExcitingUtils._ 11 12trait HasIFUConst { this: XSModule => 13 val resetVector = 0x80000000L//TODO: set reset vec 14 val groupAlign = log2Up(FetchWidth * 4 * 2) 15 def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W)) 16 // each 1 bit in mask stands for 2 Bytes 17 def mask(pc: UInt): UInt = (Fill(PredictWidth * 2, 1.U(1.W)) >> pc(groupAlign - 1, 1))(PredictWidth - 1, 0) 18 def snpc(pc: UInt): UInt = pc + (PopCount(mask(pc)) << 1) 19 20 val IFUDebug = true 21} 22 23class GlobalHistoryInfo() extends XSBundle { 24 val sawNTBr = Bool() 25 val takenOnBr = Bool() 26 val saveHalfRVI = Bool() 27 def shifted = takenOnBr || sawNTBr 28 def newPtr(ptr: UInt) = Mux(shifted, ptr - 1.U, ptr) 29 implicit val name = "IFU" 30 def debug = XSDebug("[GHInfo] sawNTBr=%d, takenOnBr=%d, saveHalfRVI=%d\n", sawNTBr, takenOnBr, saveHalfRVI) 31 // override def toString(): String = "histPtr=%d, sawNTBr=%d, takenOnBr=%d, saveHalfRVI=%d".format(histPtr, sawNTBr, takenOnBr, saveHalfRVI) 32} 33 34class IFUIO extends XSBundle 35{ 36 val fetchPacket = DecoupledIO(new FetchPacket) 37 val redirect = Flipped(ValidIO(new Redirect)) 38 val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 39 val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 40 val icacheReq = DecoupledIO(new ICacheReq) 41 val icacheResp = Flipped(DecoupledIO(new ICacheResp)) 42 val icacheFlush = Output(UInt(2.W)) 43 val loopBufPar = Flipped(new LoopBufferParameters) 44} 45 46class IFU extends XSModule with HasIFUConst 47{ 48 val io = IO(new IFUIO) 49 val bpu = BPU(EnableBPU) 50 val pd = Module(new PreDecode) 51 52 val if2_redirect, if3_redirect, if4_redirect = WireInit(false.B) 53 val if1_flush, if2_flush, if3_flush, if4_flush = WireInit(false.B) 54 55 val icacheResp = WireInit(Mux(io.loopBufPar.inLoop, io.loopBufPar.LBResp, io.icacheResp.bits)) 56 57 if4_flush := io.redirect.valid || io.loopBufPar.LBredirect.valid 58 if3_flush := if4_flush || if4_redirect 59 if2_flush := if3_flush || if3_redirect 60 if1_flush := if2_flush || if2_redirect 61 62 //********************** IF1 ****************************// 63 val if1_valid = !reset.asBool && GTimer() > 500.U 64 val if1_npc = WireInit(0.U(VAddrBits.W)) 65 val if2_ready = WireInit(false.B) 66 val if1_fire = if1_valid && (if2_ready || if1_flush) && (io.loopBufPar.inLoop || io.icacheReq.ready) 67 68 69 val if1_histPtr, if2_histPtr, if3_histPtr, if4_histPtr = Wire(UInt(log2Up(ExtHistoryLength).W)) 70 val if2_newPtr, if3_newPtr, if4_newPtr = Wire(UInt(log2Up(ExtHistoryLength).W)) 71 72 val extHist = RegInit(VecInit(Seq.fill(ExtHistoryLength)(0.U(1.W)))) 73 val shiftPtr = WireInit(false.B) 74 val newPtr = Wire(UInt(log2Up(ExtHistoryLength).W)) 75 val ptr = Mux(shiftPtr, newPtr, if1_histPtr) 76 val hist = Wire(Vec(HistoryLength, UInt(1.W))) 77 for (i <- 0 until HistoryLength) { 78 hist(i) := extHist(ptr + i.U) 79 } 80 81 shiftPtr := false.B 82 newPtr := if1_histPtr 83 84 85 86 val if1_GHInfo = Wire(new GlobalHistoryInfo()) 87 if1_GHInfo := 0.U.asTypeOf(new GlobalHistoryInfo) 88 89 //********************** IF2 ****************************// 90 val if2_valid = RegEnable(next = if1_valid, init = false.B, enable = if1_fire) 91 val if3_ready = WireInit(false.B) 92 val if2_fire = if2_valid && if3_ready && !if2_flush 93 val if2_pc = RegEnable(next = if1_npc, init = resetVector.U, enable = if1_fire) 94 val if2_snpc = snpc(if2_pc) 95 val if2_GHInfo = RegEnable(if1_GHInfo, if1_fire) 96 val if2_predHistPtr = RegEnable(ptr, enable=if1_fire) 97 if2_ready := if2_fire || !if2_valid || if2_flush 98 when (if2_flush) { if2_valid := if1_fire } 99 .elsewhen (if1_fire) { if2_valid := if1_valid } 100 .elsewhen (if2_fire) { if2_valid := false.B } 101 102 when (RegNext(reset.asBool) && !reset.asBool) { 103 if1_npc := resetVector.U(VAddrBits.W) 104 }.elsewhen (if2_fire) { 105 if1_npc := if2_snpc 106 }.otherwise { 107 if1_npc := RegNext(if1_npc) 108 } 109 110 val if2_bp = bpu.io.out(0).bits 111 // if taken, bp_redirect should be true 112 // when taken on half RVI, we suppress this redirect signal 113 if2_redirect := if2_fire && bpu.io.out(0).valid && if2_bp.redirect && !if2_bp.saveHalfRVI 114 when (if2_redirect) { 115 if1_npc := if2_bp.target 116 } 117 118 val if2_realGHInfo = Wire(new GlobalHistoryInfo()) 119 if2_realGHInfo.sawNTBr := if2_bp.hasNotTakenBrs 120 if2_realGHInfo.takenOnBr := if2_bp.takenOnBr 121 if2_realGHInfo.saveHalfRVI := if2_bp.saveHalfRVI 122 123 when (if2_fire && if2_realGHInfo.shifted) { 124 shiftPtr := true.B 125 newPtr := if2_newPtr 126 } 127 when (if2_realGHInfo.shifted && if2_newPtr >= ptr) { 128 hist(if2_newPtr-ptr) := if2_realGHInfo.takenOnBr.asUInt 129 } 130 131 132 133 //********************** IF3 ****************************// 134 val if3_valid = RegEnable(next = if2_valid, init = false.B, enable = if2_fire) 135 val if4_ready = WireInit(false.B) 136 val if3_fire = if3_valid && if4_ready && (io.loopBufPar.inLoop || io.icacheResp.valid) && !if3_flush 137 val if3_pc = RegEnable(if2_pc, if2_fire) 138 val if3_GHInfo = RegEnable(if2_realGHInfo, if2_fire) 139 val if3_predHistPtr = RegEnable(if2_predHistPtr, enable=if2_fire) 140 if3_ready := if3_fire || !if3_valid || if3_flush 141 when (if3_flush) { if3_valid := false.B } 142 .elsewhen (if2_fire) { if3_valid := if2_valid } 143 .elsewhen (if3_fire) { if3_valid := false.B } 144 145 val if3_bp = bpu.io.out(1).bits 146 147 val if3_realGHInfo = Wire(new GlobalHistoryInfo()) 148 if3_realGHInfo.sawNTBr := if3_bp.hasNotTakenBrs 149 if3_realGHInfo.takenOnBr := if3_bp.takenOnBr 150 if3_realGHInfo.saveHalfRVI := if3_bp.saveHalfRVI 151 152 class PrevHalfInstr extends Bundle { 153 val valid = Bool() 154 val taken = Bool() 155 val ghInfo = new GlobalHistoryInfo() 156 val fetchpc = UInt(VAddrBits.W) // only for debug 157 val idx = UInt(VAddrBits.W) // only for debug 158 val pc = UInt(VAddrBits.W) 159 val target = UInt(VAddrBits.W) 160 val instr = UInt(16.W) 161 val ipf = Bool() 162 val newPtr = UInt(log2Up(ExtHistoryLength).W) 163 } 164 165 val if3_prevHalfInstr = RegInit(0.U.asTypeOf(new PrevHalfInstr)) 166 val if4_prevHalfInstr = Wire(new PrevHalfInstr) 167 // 32-bit instr crosses 2 pages, and the higher 16-bit triggers page fault 168 val crossPageIPF = WireInit(false.B) 169 when (if4_prevHalfInstr.valid) { 170 if3_prevHalfInstr := if4_prevHalfInstr 171 } 172 val prevHalfInstr = Mux(if4_prevHalfInstr.valid, if4_prevHalfInstr, if3_prevHalfInstr) 173 174 // the previous half of RVI instruction waits until it meets its last half 175 val if3_hasPrevHalfInstr = prevHalfInstr.valid && (prevHalfInstr.pc + 2.U) === if3_pc 176 // set to invalid once consumed or redirect from backend 177 val prevHalfConsumed = if3_hasPrevHalfInstr && if3_fire || if4_flush 178 when (prevHalfConsumed) { 179 if3_prevHalfInstr.valid := false.B 180 } 181 182 // when bp signal a redirect, we distinguish between taken and not taken 183 // if taken and saveHalfRVI is true, we do not redirect to the target 184 if3_redirect := if3_fire && bpu.io.out(1).valid && (if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.redirect && (if3_bp.taken && !if3_bp.saveHalfRVI || !if3_bp.taken) ) 185 186 when (if3_redirect) { 187 when (!(if3_hasPrevHalfInstr && prevHalfInstr.taken)) { 188 if1_npc := if3_bp.target 189 when (if3_realGHInfo.shifted){ 190 shiftPtr := true.B 191 newPtr := if3_newPtr 192 } 193 } 194 } 195 196 // when it does not redirect, we still need to modify hist(wire) 197 when(if3_realGHInfo.shifted && if3_newPtr >= ptr) { 198 hist(if3_newPtr-ptr) := if3_realGHInfo.takenOnBr 199 } 200 when (if3_hasPrevHalfInstr && prevHalfInstr.ghInfo.shifted && prevHalfInstr.newPtr >= ptr) { 201 hist(prevHalfInstr.newPtr-ptr) := prevHalfInstr.ghInfo.takenOnBr 202 } 203 204 //********************** IF4 ****************************// 205 val if4_pd = RegEnable(pd.io.out, if3_fire) 206 val if4_ipf = RegEnable(icacheResp.ipf || if3_hasPrevHalfInstr && prevHalfInstr.ipf, if3_fire) 207 val if4_crossPageIPF = RegEnable(crossPageIPF, if3_fire) 208 val if4_valid = RegInit(false.B) 209 val if4_fire = if4_valid && io.fetchPacket.ready 210 val if4_pc = RegEnable(if3_pc, if3_fire) 211 212 val if4_GHInfo = RegEnable(if3_realGHInfo, if3_fire) 213 val if4_predHistPtr = RegEnable(if3_predHistPtr, enable=if3_fire) 214 if4_ready := (if4_fire || !if4_valid || if4_flush) && GTimer() > 500.U 215 when (if4_flush) { if4_valid := false.B } 216 .elsewhen (if3_fire) { if4_valid := if3_valid } 217 .elsewhen(if4_fire) { if4_valid := false.B } 218 219 val if4_bp = Wire(new BranchPrediction) 220 if4_bp := bpu.io.out(2).bits 221 222 val if4_realGHInfo = Wire(new GlobalHistoryInfo()) 223 if4_realGHInfo.sawNTBr := if4_bp.hasNotTakenBrs 224 if4_realGHInfo.takenOnBr := if4_bp.takenOnBr 225 if4_realGHInfo.saveHalfRVI := if4_bp.saveHalfRVI 226 227 228 val if4_cfi_jal = if4_pd.instrs(if4_bp.jmpIdx) 229 val if4_cfi_jal_tgt = if4_pd.pc(if4_bp.jmpIdx) + Mux(if4_pd.pd(if4_bp.jmpIdx).isRVC, 230 SignExt(Cat(if4_cfi_jal(12), if4_cfi_jal(8), if4_cfi_jal(10, 9), if4_cfi_jal(6), if4_cfi_jal(7), if4_cfi_jal(2), if4_cfi_jal(11), if4_cfi_jal(5, 3), 0.U(1.W)), XLEN), 231 SignExt(Cat(if4_cfi_jal(31), if4_cfi_jal(19, 12), if4_cfi_jal(20), if4_cfi_jal(30, 21), 0.U(1.W)), XLEN)) 232 if4_bp.target := Mux(if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken, if4_cfi_jal_tgt, bpu.io.out(2).bits.target) 233 if4_bp.redirect := bpu.io.out(2).bits.redirect || if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken && if4_cfi_jal_tgt =/= bpu.io.out(2).bits.target 234 235 if4_prevHalfInstr := 0.U.asTypeOf(new PrevHalfInstr) 236 when (bpu.io.out(2).valid && if4_fire && if4_bp.saveHalfRVI) { 237 if4_prevHalfInstr.valid := true.B 238 if4_prevHalfInstr.taken := if4_bp.taken 239 if4_prevHalfInstr.ghInfo := if4_realGHInfo 240 // Make sure shifted can work 241 if4_prevHalfInstr.ghInfo.saveHalfRVI := false.B 242 if4_prevHalfInstr.newPtr := if4_newPtr 243 if4_prevHalfInstr.fetchpc := if4_pc 244 if4_prevHalfInstr.idx := PopCount(mask(if4_pc)) - 1.U 245 if4_prevHalfInstr.pc := if4_pd.pc(if4_prevHalfInstr.idx) 246 if4_prevHalfInstr.target := if4_bp.target 247 if4_prevHalfInstr.instr := if4_pd.instrs(if4_prevHalfInstr.idx)(15, 0) 248 if4_prevHalfInstr.ipf := if4_ipf 249 } 250 251 // Redirect and npc logic for if4 252 when (bpu.io.out(2).valid && if4_fire && if4_bp.redirect) { 253 if4_redirect := true.B 254 when (if4_bp.saveHalfRVI) { 255 if1_npc := snpc(if4_pc) 256 }.otherwise { 257 if1_npc := if4_bp.target 258 } 259 } 260 // }.elsewhen (bpu.io.out(2).valid && if4_fire/* && !if4_bp.redirect*/) { 261 // // We redirect the pipeline to the next fetch packet, 262 // // which contains the last half of the RVI instruction 263 // when (if4_bp.saveHalfRVI && if4_bp.taken) { 264 // if4_redirect := true.B 265 // if1_npc := snpc(if4_pc) 266 // } 267 // } 268 269 // This should cover the if4 redirect to snpc when saveHalfRVI 270 when (if3_redirect) { 271 when (if3_hasPrevHalfInstr && prevHalfInstr.taken) { 272 if1_npc := prevHalfInstr.target 273 } 274 } 275 276 // history logic for if4 277 when (bpu.io.out(2).valid && if4_fire && if4_bp.redirect) { 278 shiftPtr := true.B 279 newPtr := if4_newPtr 280 // }.elsewhen (bpu.io.out(2).valid && if4_fire/* && !if4_bp.redirect*/) { 281 // // only if we hasn't seen not taken branches and 282 // // see a not taken branch in if4 should we tell 283 // // if3 and if4 to update histptr 284 // // We do not shift global history pointer unless we have the full 285 // // RVI instruction 286 // when (if4_newSawNTBrs && !if4_bp.takenOnBr) { 287 // shiftPtr := true.B 288 // // newPtr := if4_realGHInfo.newPtr 289 // } 290 } 291 292 when (if4_realGHInfo.shifted && if4_newPtr >= ptr) { 293 hist(if4_newPtr-ptr) := if4_realGHInfo.takenOnBr 294 } 295 296 when (if3_redirect) { 297 // when redirect and if3_hasPrevHalfInstr, this prevHalfInstr should only be taken 298 when (if3_hasPrevHalfInstr && prevHalfInstr.ghInfo.shifted) { 299 shiftPtr := true.B 300 newPtr := prevHalfInstr.newPtr 301 extHist(prevHalfInstr.newPtr) := prevHalfInstr.ghInfo.takenOnBr 302 } 303 } 304 305 // modify GHR at the end of a prediction lifetime 306 when (if4_fire && if4_realGHInfo.shifted) { 307 extHist(if4_newPtr) := if4_realGHInfo.takenOnBr 308 } 309 310 // This is a histPtr which is only modified when a prediction 311 // is sent, so that it can get the final prediction info 312 val finalPredHistPtr = RegInit(0.U(log2Up(ExtHistoryLength).W)) 313 if4_histPtr := finalPredHistPtr 314 if4_newPtr := if3_histPtr 315 when (if4_fire && if4_realGHInfo.shifted) { 316 finalPredHistPtr := if4_newPtr 317 } 318 319 if3_histPtr := Mux(if4_realGHInfo.shifted && if4_valid && !if4_flush, if4_histPtr - 1.U, if4_histPtr) 320 if3_newPtr := if2_histPtr 321 322 if2_histPtr := Mux(if3_realGHInfo.shifted && if3_valid && !if3_flush, if3_histPtr - 1.U, if3_histPtr) 323 if2_newPtr := if1_histPtr 324 325 if1_histPtr := Mux(if2_realGHInfo.shifted && if2_valid && !if2_flush, if2_histPtr - 1.U, if2_histPtr) 326 327 328 329 330 when (io.outOfOrderBrInfo.valid && io.outOfOrderBrInfo.bits.isMisPred) { 331 val b = io.outOfOrderBrInfo.bits 332 val oldPtr = b.brInfo.histPtr 333 shiftPtr := true.B 334 when (!b.pd.isBr && !b.brInfo.sawNotTakenBranch) { 335 // If mispredicted cfi is not a branch, 336 // and there wasn't any not taken branch before it, 337 // we should only recover the pointer to an unshifted state 338 newPtr := oldPtr 339 finalPredHistPtr := oldPtr 340 }.otherwise { 341 newPtr := oldPtr - 1.U 342 finalPredHistPtr := oldPtr - 1.U 343 hist(0) := Mux(b.pd.isBr, b.taken, 0.U) 344 extHist(newPtr) := Mux(b.pd.isBr, b.taken, 0.U) 345 } 346 } 347 348 when (io.loopBufPar.LBredirect.valid) { 349 if1_npc := io.loopBufPar.LBredirect.bits 350 } 351 352 when (io.redirect.valid) { 353 if1_npc := io.redirect.bits.target 354 } 355 356 when(io.loopBufPar.inLoop) { 357 io.icacheReq.valid := if2_flush 358 }.otherwise { 359 io.icacheReq.valid := if1_valid && if2_ready 360 // io.icacheResp.ready := if3_ready 361 //io.icacheResp.ready := if3_valid 362 } 363 io.icacheResp.ready := if4_ready 364 io.icacheReq.bits.addr := if1_npc 365 366 // when(if4_bp.taken) { 367 // when(if4_bp.saveHalfRVI) { 368 // io.loopBufPar.LBReq := snpc(if4_pc) 369 // }.otherwise { 370 // io.loopBufPar.LBReq := if4_bp.target 371 // } 372 // }.otherwise { 373 // io.loopBufPar.LBReq := snpc(if4_pc) 374 // XSDebug(p"snpc(if4_pc)=${Hexadecimal(snpc(if4_pc))}\n") 375 // } 376 io.loopBufPar.LBReq := if3_pc 377 io.loopBufPar.tgtpc := if4_bp.target 378 379 io.icacheReq.bits.mask := mask(if1_npc) 380 381 io.icacheFlush := Cat(if3_flush, if2_flush) 382 383 val inOrderBrHist = Wire(Vec(HistoryLength, UInt(1.W))) 384 (0 until HistoryLength).foreach(i => inOrderBrHist(i) := extHist(i.U + io.inOrderBrInfo.bits.brInfo.predHistPtr)) 385 bpu.io.inOrderBrInfo.valid := io.inOrderBrInfo.valid 386 bpu.io.inOrderBrInfo.bits := BranchUpdateInfoWithHist(io.inOrderBrInfo.bits, inOrderBrHist.asUInt) 387 bpu.io.outOfOrderBrInfo.valid := io.outOfOrderBrInfo.valid 388 bpu.io.outOfOrderBrInfo.bits := BranchUpdateInfoWithHist(io.outOfOrderBrInfo.bits, inOrderBrHist.asUInt) // Dont care about hist 389 390 // bpu.io.flush := Cat(if4_flush, if3_flush, if2_flush) 391 bpu.io.flush := VecInit(if2_flush, if3_flush, if4_flush) 392 bpu.io.cacheValid := (io.loopBufPar.inLoop || io.icacheResp.valid) 393 bpu.io.in.valid := if1_fire 394 bpu.io.in.bits.pc := if1_npc 395 bpu.io.in.bits.hist := hist.asUInt 396 bpu.io.in.bits.histPtr := ptr 397 bpu.io.in.bits.inMask := mask(if1_npc) 398 bpu.io.out(0).ready := if2_fire 399 bpu.io.out(1).ready := if3_fire 400 bpu.io.out(2).ready := if4_fire 401 bpu.io.predecode.valid := if4_valid 402 bpu.io.predecode.bits.mask := if4_pd.mask 403 bpu.io.predecode.bits.pd := if4_pd.pd 404 bpu.io.predecode.bits.isFetchpcEqualFirstpc := if4_pc === if4_pd.pc(0) 405 bpu.io.branchInfo.ready := if4_fire 406 407 when(io.loopBufPar.inLoop) { 408 pd.io.in := io.loopBufPar.LBResp 409 pd.io.in.mask := io.loopBufPar.LBResp.mask & mask(io.loopBufPar.LBResp.pc) 410 XSDebug("Fetch from LB\n") 411 XSDebug(p"pc=${Hexadecimal(io.loopBufPar.LBResp.pc)}\n") 412 XSDebug(p"data=${Hexadecimal(io.loopBufPar.LBResp.data)}\n") 413 XSDebug(p"mask=${Hexadecimal(io.loopBufPar.LBResp.mask)}\n") 414 }.otherwise { 415 pd.io.in := icacheResp 416 } 417 pd.io.prev.valid := if3_hasPrevHalfInstr 418 pd.io.prev.bits := prevHalfInstr.instr 419 // if a fetch packet triggers page fault, set the pf instruction to nop 420 when (!if3_hasPrevHalfInstr && icacheResp.ipf) { 421 val instrs = Wire(Vec(FetchWidth, UInt(32.W))) 422 (0 until FetchWidth).foreach(i => instrs(i) := ZeroExt("b0010011".U, 32)) // nop 423 pd.io.in.data := instrs.asUInt 424 }.elsewhen (if3_hasPrevHalfInstr && (prevHalfInstr.ipf || icacheResp.ipf)) { 425 pd.io.prev.bits := ZeroExt("b0010011".U, 16) 426 val instrs = Wire(Vec(FetchWidth, UInt(32.W))) 427 (0 until FetchWidth).foreach(i => instrs(i) := Cat(ZeroExt("b0010011".U, 16), Fill(16, 0.U(1.W)))) 428 pd.io.in.data := instrs.asUInt 429 430 when (icacheResp.ipf && !prevHalfInstr.ipf) { crossPageIPF := true.B } // higher 16 bits page fault 431 } 432 433 //Performance Counter 434 if (!env.FPGAPlatform ) { 435 ExcitingUtils.addSource(io.fetchPacket.fire && !io.loopBufPar.inLoop, "CntFetchFromICache", Perf) 436 ExcitingUtils.addSource(io.fetchPacket.fire && io.loopBufPar.inLoop, "CntFetchFromLoopBuffer", Perf) 437 } 438 439 io.fetchPacket.valid := if4_valid && !io.redirect.valid 440 io.fetchPacket.bits.instrs := if4_pd.instrs 441 io.fetchPacket.bits.mask := if4_pd.mask & (Fill(PredictWidth, !if4_bp.taken) | (Fill(PredictWidth, 1.U(1.W)) >> (~if4_bp.jmpIdx))) 442 io.fetchPacket.bits.pc := if4_pd.pc 443 (0 until PredictWidth).foreach(i => io.fetchPacket.bits.pnpc(i) := if4_pd.pc(i) + Mux(if4_pd.pd(i).isRVC, 2.U, 4.U)) 444 when (if4_bp.taken) { 445 io.fetchPacket.bits.pnpc(if4_bp.jmpIdx) := if4_bp.target 446 } 447 io.fetchPacket.bits.brInfo := bpu.io.branchInfo.bits 448 (0 until PredictWidth).foreach(i => io.fetchPacket.bits.brInfo(i).histPtr := finalPredHistPtr) 449 (0 until PredictWidth).foreach(i => io.fetchPacket.bits.brInfo(i).predHistPtr := if4_predHistPtr) 450 io.fetchPacket.bits.pd := if4_pd.pd 451 io.fetchPacket.bits.ipf := if4_ipf 452 io.fetchPacket.bits.crossPageIPFFix := if4_crossPageIPF 453 454 // predTaken Vec 455 io.fetchPacket.bits.predTaken := if4_bp.taken 456 457 // debug info 458 if (IFUDebug) { 459 XSDebug(RegNext(reset.asBool) && !reset.asBool, "Reseting...\n") 460 XSDebug(io.icacheFlush(0).asBool, "Flush icache stage2...\n") 461 XSDebug(io.icacheFlush(1).asBool, "Flush icache stage3...\n") 462 XSDebug(io.redirect.valid, "Redirect from backend! isExcp=%d isFpp:%d isMisPred=%d isReplay=%d pc=%x\n", 463 io.redirect.bits.isException, io.redirect.bits.isFlushPipe, io.redirect.bits.isMisPred, io.redirect.bits.isReplay, io.redirect.bits.pc) 464 XSDebug(io.redirect.valid, p"Redirect from backend! target=${Hexadecimal(io.redirect.bits.target)} brTag=${io.redirect.bits.brTag}\n") 465 466 XSDebug("[IF1] v=%d fire=%d flush=%d pc=%x ptr=%d mask=%b\n", if1_valid, if1_fire, if1_flush, if1_npc, ptr, mask(if1_npc)) 467 XSDebug("[IF2] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d snpc=%x\n", if2_valid, if2_ready, if2_fire, if2_redirect, if2_flush, if2_pc, if2_histPtr, if2_snpc) 468 XSDebug("[IF3] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d crossPageIPF=%d sawNTBrs=%d\n", if3_valid, if3_ready, if3_fire, if3_redirect, if3_flush, if3_pc, if3_histPtr, crossPageIPF, if3_realGHInfo.sawNTBr) 469 XSDebug("[IF4] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d crossPageIPF=%d sawNTBrs=%d\n", if4_valid, if4_ready, if4_fire, if4_redirect, if4_flush, if4_pc, if4_histPtr, if4_crossPageIPF, if4_realGHInfo.sawNTBr) 470 XSDebug("[IF1][icacheReq] v=%d r=%d addr=%x\n", io.icacheReq.valid, io.icacheReq.ready, io.icacheReq.bits.addr) 471 XSDebug("[IF1][ghr] headPtr=%d shiftPtr=%d newPtr=%d ptr=%d\n", if1_histPtr, shiftPtr, newPtr, ptr) 472 XSDebug("[IF1][ghr] hist=%b\n", hist.asUInt) 473 XSDebug("[IF1][ghr] extHist=%b\n\n", extHist.asUInt) 474 475 XSDebug("[IF2][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n\n", if2_bp.redirect, if2_bp.taken, if2_bp.jmpIdx, if2_bp.hasNotTakenBrs, if2_bp.target, if2_bp.saveHalfRVI) 476 // XSDebug("[IF2][GHInfo]: %s\n", if2_realGHInfo) 477 if2_realGHInfo.debug 478 479 XSDebug("[IF3][icacheResp] v=%d r=%d pc=%x mask=%b\n", io.icacheResp.valid, io.icacheResp.ready, io.icacheResp.bits.pc, io.icacheResp.bits.mask) 480 XSDebug("[IF3][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if3_bp.redirect, if3_bp.taken, if3_bp.jmpIdx, if3_bp.hasNotTakenBrs, if3_bp.target, if3_bp.saveHalfRVI) 481 // XSDebug("[IF3][prevHalfInstr] v=%d redirect=%d fetchpc=%x idx=%d tgt=%x taken=%d instr=%x\n\n", 482 // prev_half_valid, prev_half_redirect, prev_half_fetchpc, prev_half_idx, prev_half_tgt, prev_half_taken, prev_half_instr) 483 XSDebug("[IF3][ prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x ipf=%d\n", 484 prevHalfInstr.valid, prevHalfInstr.taken, prevHalfInstr.fetchpc, prevHalfInstr.idx, prevHalfInstr.pc, prevHalfInstr.target, prevHalfInstr.instr, prevHalfInstr.ipf) 485 XSDebug("[IF3][if3_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x ipf=%d\n\n", 486 if3_prevHalfInstr.valid, if3_prevHalfInstr.taken, if3_prevHalfInstr.fetchpc, if3_prevHalfInstr.idx, if3_prevHalfInstr.pc, if3_prevHalfInstr.target, if3_prevHalfInstr.instr, if3_prevHalfInstr.ipf) 487 // XSDebug("[IF3][GHInfo]: %s\n", if3_realGHInfo) 488 if3_realGHInfo.debug 489 490 XSDebug("[IF4][predecode] mask=%b\n", if4_pd.mask) 491 XSDebug("[IF4][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if4_bp.redirect, if4_bp.taken, if4_bp.jmpIdx, if4_bp.hasNotTakenBrs, if4_bp.target, if4_bp.saveHalfRVI) 492 XSDebug(if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken, "[IF4] cfi is jal! instr=%x target=%x\n", if4_cfi_jal, if4_cfi_jal_tgt) 493 XSDebug("[IF4][if4_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x ipf=%d\n", 494 if4_prevHalfInstr.valid, if4_prevHalfInstr.taken, if4_prevHalfInstr.fetchpc, if4_prevHalfInstr.idx, if4_prevHalfInstr.pc, if4_prevHalfInstr.target, if4_prevHalfInstr.instr, if4_prevHalfInstr.ipf) 495 // XSDebug("[IF4][GHInfo]: %s\n", if4_realGHInfo) 496 if4_realGHInfo.debug 497 XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] v=%d r=%d mask=%b ipf=%d crossPageIPF=%d\n", 498 io.fetchPacket.valid, io.fetchPacket.ready, io.fetchPacket.bits.mask, io.fetchPacket.bits.ipf, io.fetchPacket.bits.crossPageIPFFix) 499 for (i <- 0 until PredictWidth) { 500 XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] %b %x pc=%x pnpc=%x pd: rvc=%d brType=%b call=%d ret=%d\n", 501 io.fetchPacket.bits.mask(i), 502 io.fetchPacket.bits.instrs(i), 503 io.fetchPacket.bits.pc(i), 504 io.fetchPacket.bits.pnpc(i), 505 io.fetchPacket.bits.pd(i).isRVC, 506 io.fetchPacket.bits.pd(i).brType, 507 io.fetchPacket.bits.pd(i).isCall, 508 io.fetchPacket.bits.pd(i).isRet 509 ) 510 } 511 } 512}