1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import xiangshan.cache._ 24import xiangshan.cache.mmu._ 25import chisel3.experimental.verification 26import utils._ 27import xiangshan.backend.fu.{PMPReqBundle, PMPRespBundle} 28 29trait HasInstrMMIOConst extends HasXSParameter with HasIFUConst{ 30 def mmioBusWidth = 64 31 def mmioBusBytes = mmioBusWidth / 8 32 def maxInstrLen = 32 33} 34 35trait HasIFUConst extends HasXSParameter { 36 def align(pc: UInt, bytes: Int): UInt = Cat(pc(VAddrBits-1, log2Ceil(bytes)), 0.U(log2Ceil(bytes).W)) 37 // def groupAligned(pc: UInt) = align(pc, groupBytes) 38 // def packetAligned(pc: UInt) = align(pc, packetBytes) 39} 40 41class IfuToFtqIO(implicit p:Parameters) extends XSBundle { 42 val pdWb = Valid(new PredecodeWritebackBundle) 43} 44 45class FtqInterface(implicit p: Parameters) extends XSBundle { 46 val fromFtq = Flipped(new FtqToIfuIO) 47 val toFtq = new IfuToFtqIO 48} 49 50class UncacheInterface(implicit p: Parameters) extends XSBundle { 51 val fromUncache = Flipped(DecoupledIO(new InsUncacheResp)) 52 val toUncache = DecoupledIO( new InsUncacheReq ) 53} 54 55class ICacheInterface(implicit p: Parameters) extends XSBundle { 56 val toIMeta = Decoupled(new ICacheReadBundle) 57 val toIData = Decoupled(new ICacheReadBundle) 58 val toMissQueue = Vec(2,Decoupled(new ICacheMissReq)) 59 val fromIMeta = Input(new ICacheMetaRespBundle) 60 val fromIData = Input(new ICacheDataRespBundle) 61 val fromMissQueue = Vec(2,Flipped(Decoupled(new ICacheMissResp))) 62} 63 64class NewIFUIO(implicit p: Parameters) extends XSBundle { 65 val ftqInter = new FtqInterface 66 val icacheInter = new ICacheInterface 67 val toIbuffer = Decoupled(new FetchToIBuffer) 68 val iTLBInter = Vec(2, new BlockTlbRequestIO) 69 val uncacheInter = new UncacheInterface 70 val pmp = Vec(2, new Bundle { 71 val req = Valid(new PMPReqBundle()) 72 val resp = Flipped(new PMPRespBundle()) 73 }) 74} 75 76// record the situation in which fallThruAddr falls into 77// the middle of an RVI inst 78class LastHalfInfo(implicit p: Parameters) extends XSBundle { 79 val valid = Bool() 80 val middlePC = UInt(VAddrBits.W) 81 def matchThisBlock(startAddr: UInt) = valid && middlePC === startAddr 82} 83 84class IfuToPreDecode(implicit p: Parameters) extends XSBundle { 85 val data = if(HasCExtension) Vec(PredictWidth + 1, UInt(16.W)) else Vec(PredictWidth, UInt(32.W)) 86 val startAddr = UInt(VAddrBits.W) 87 val fallThruAddr = UInt(VAddrBits.W) 88 val fallThruError = Bool() 89 val isDoubleLine = Bool() 90 val ftqOffset = Valid(UInt(log2Ceil(PredictWidth).W)) 91 val target = UInt(VAddrBits.W) 92 val pageFault = Vec(2, Bool()) 93 val accessFault = Vec(2, Bool()) 94 val instValid = Bool() 95 val lastHalfMatch = Bool() 96 val oversize = Bool() 97 val mmio = Bool() 98} 99 100class NewIFU(implicit p: Parameters) extends XSModule with HasICacheParameters 101{ 102 println(s"icache ways: ${nWays} sets:${nSets}") 103 val io = IO(new NewIFUIO) 104 val (toFtq, fromFtq) = (io.ftqInter.toFtq, io.ftqInter.fromFtq) 105 val (toMeta, toData, meta_resp, data_resp) = (io.icacheInter.toIMeta, io.icacheInter.toIData, io.icacheInter.fromIMeta, io.icacheInter.fromIData) 106 val (toMissQueue, fromMissQueue) = (io.icacheInter.toMissQueue, io.icacheInter.fromMissQueue) 107 val (toUncache, fromUncache) = (io.uncacheInter.toUncache , io.uncacheInter.fromUncache) 108 val (toITLB, fromITLB) = (VecInit(io.iTLBInter.map(_.req)), VecInit(io.iTLBInter.map(_.resp))) 109 val fromPMP = io.pmp.map(_.resp) 110 111 def isCrossLineReq(start: UInt, end: UInt): Bool = start(blockOffBits) ^ end(blockOffBits) 112 113 def isLastInCacheline(fallThruAddr: UInt): Bool = fallThruAddr(blockOffBits - 1, 1) === 0.U 114 115 def ResultHoldBypass[T<:Data](data: T, valid: Bool): T = { 116 Mux(valid, data, RegEnable(data, valid)) 117 } 118 119 //--------------------------------------------- 120 // Fetch Stage 1 : 121 // * Send req to ICache Meta/Data 122 // * Check whether need 2 line fetch 123 //--------------------------------------------- 124 125 val f0_valid = fromFtq.req.valid 126 val f0_ftq_req = fromFtq.req.bits 127 val f0_situation = VecInit(Seq(isCrossLineReq(f0_ftq_req.startAddr, f0_ftq_req.fallThruAddr), isLastInCacheline(f0_ftq_req.fallThruAddr))) 128 val f0_doubleLine = f0_situation(0) || f0_situation(1) 129 val f0_vSetIdx = VecInit(get_idx((f0_ftq_req.startAddr)), get_idx(f0_ftq_req.fallThruAddr)) 130 val f0_fire = fromFtq.req.fire() 131 132 val f0_flush, f1_flush, f2_flush, f3_flush = WireInit(false.B) 133 val from_bpu_f0_flush, from_bpu_f1_flush, from_bpu_f2_flush, from_bpu_f3_flush = WireInit(false.B) 134 135 from_bpu_f0_flush := fromFtq.flushFromBpu.shouldFlushByStage2(f0_ftq_req.ftqIdx) || 136 fromFtq.flushFromBpu.shouldFlushByStage3(f0_ftq_req.ftqIdx) 137 138 val f3_redirect = WireInit(false.B) 139 f3_flush := fromFtq.redirect.valid 140 f2_flush := f3_flush || f3_redirect 141 f1_flush := f2_flush || from_bpu_f1_flush 142 f0_flush := f1_flush || from_bpu_f0_flush 143 144 val f1_ready, f2_ready, f3_ready = WireInit(false.B) 145 146 //fetch: send addr to Meta/TLB and Data simultaneously 147 val fetch_req = List(toMeta, toData) 148 for(i <- 0 until 2) { 149 fetch_req(i).valid := f0_fire 150 fetch_req(i).bits.isDoubleLine := f0_doubleLine 151 fetch_req(i).bits.vSetIdx := f0_vSetIdx 152 } 153 154 fromFtq.req.ready := fetch_req(0).ready && fetch_req(1).ready && f1_ready && GTimer() > 500.U 155 156 XSPerfAccumulate("ifu_bubble_ftq_not_valid", !f0_valid ) 157 XSPerfAccumulate("ifu_bubble_pipe_stall", f0_valid && fetch_req(0).ready && fetch_req(1).ready && !f1_ready ) 158 XSPerfAccumulate("ifu_bubble_sram_0_busy", f0_valid && !fetch_req(0).ready ) 159 XSPerfAccumulate("ifu_bubble_sram_1_busy", f0_valid && !fetch_req(1).ready ) 160 161 //--------------------------------------------- 162 // Fetch Stage 2 : 163 // * Send req to ITLB and TLB Response (Get Paddr) 164 // * ICache Response (Get Meta and Data) 165 // * Hit Check (Generate hit signal and hit vector) 166 // * Get victim way 167 //--------------------------------------------- 168 169 //TODO: handle fetch exceptions 170 171 val tlbRespAllValid = WireInit(false.B) 172 173 val f1_valid = RegInit(false.B) 174 val f1_ftq_req = RegEnable(next = f0_ftq_req, enable=f0_fire) 175 val f1_situation = RegEnable(next = f0_situation, enable=f0_fire) 176 val f1_doubleLine = RegEnable(next = f0_doubleLine, enable=f0_fire) 177 val f1_vSetIdx = RegEnable(next = f0_vSetIdx, enable=f0_fire) 178 val f1_fire = f1_valid && tlbRespAllValid && f2_ready 179 180 f1_ready := f2_ready && tlbRespAllValid || !f1_valid 181 182 from_bpu_f1_flush := fromFtq.flushFromBpu.shouldFlushByStage3(f1_ftq_req.ftqIdx) 183 184 val preDecoder = Module(new PreDecode) 185 val (preDecoderIn, preDecoderOut) = (preDecoder.io.in, preDecoder.io.out) 186 187 //flush generate and to Ftq 188 val predecodeOutValid = WireInit(false.B) 189 190 when(f1_flush) {f1_valid := false.B} 191 .elsewhen(f0_fire && !f0_flush) {f1_valid := true.B} 192 .elsewhen(f1_fire) {f1_valid := false.B} 193 194 toITLB(0).valid := f1_valid 195 toITLB(0).bits.size := 3.U // TODO: fix the size 196 toITLB(0).bits.vaddr := align(f1_ftq_req.startAddr, blockBytes) 197 toITLB(0).bits.debug.pc := align(f1_ftq_req.startAddr, blockBytes) 198 199 toITLB(1).valid := f1_valid && f1_doubleLine 200 toITLB(1).bits.size := 3.U // TODO: fix the size 201 toITLB(1).bits.vaddr := align(f1_ftq_req.fallThruAddr, blockBytes) 202 toITLB(1).bits.debug.pc := align(f1_ftq_req.fallThruAddr, blockBytes) 203 204 toITLB.map{port => 205 port.bits.cmd := TlbCmd.exec 206 port.bits.robIdx := DontCare 207 port.bits.debug.isFirstIssue := DontCare 208 } 209 210 fromITLB.map(_.ready := true.B) 211 212 val (tlbRespValid, tlbRespPAddr) = (fromITLB.map(_.valid), VecInit(fromITLB.map(_.bits.paddr))) 213 val (tlbRespMiss) = (fromITLB.map(port => port.bits.miss && port.valid)) 214 val (tlbExcpPF, tlbExcpAF) = (fromITLB.map(port => port.bits.excp.pf.instr && port.valid), 215 fromITLB.map(port => (port.bits.excp.af.instr) && port.valid)) //TODO: Temp treat mmio req as access fault 216 217 tlbRespAllValid := tlbRespValid(0) && (tlbRespValid(1) || !f1_doubleLine) 218 219 val f1_pAddrs = tlbRespPAddr 220 val f1_pTags = VecInit(f1_pAddrs.map(get_phy_tag(_))) 221 222 val f1_tags = ResultHoldBypass(data = meta_resp.tags, valid = RegNext(toMeta.fire())) 223 val f1_cacheline_valid = ResultHoldBypass(data = meta_resp.valid, valid = RegNext(toMeta.fire())) 224 val f1_datas = ResultHoldBypass(data = data_resp.datas, valid = RegNext(toData.fire())) 225 226 val bank0_hit_vec = VecInit(f1_tags(0).zipWithIndex.map{ case(way_tag,i) => f1_cacheline_valid(0)(i) && way_tag === f1_pTags(0) }) 227 val bank1_hit_vec = VecInit(f1_tags(1).zipWithIndex.map{ case(way_tag,i) => f1_cacheline_valid(1)(i) && way_tag === f1_pTags(1) }) 228 val (bank0_hit,bank1_hit) = (ParallelOR(bank0_hit_vec) && !tlbExcpPF(0) && !tlbExcpAF(0), ParallelOR(bank1_hit_vec) && !tlbExcpPF(1) && !tlbExcpAF(1)) 229 val f1_hit = (bank0_hit && bank1_hit && f1_valid && f1_doubleLine) || (f1_valid && !f1_doubleLine && bank0_hit) 230 val f1_bank_hit_vec = VecInit(Seq(bank0_hit_vec, bank1_hit_vec)) 231 val f1_bank_hit = VecInit(Seq(bank0_hit, bank1_hit)) 232 233 //MMIO 234 //MMIO only need 1 instruction 235 // val f1_mmio = tlbRespMMIO(0) && f1_valid 236 237 238 val replacers = Seq.fill(2)(ReplacementPolicy.fromString(Some("random"),nWays,nSets/2)) 239 val f1_victim_masks = VecInit(replacers.zipWithIndex.map{case (replacer, i) => UIntToOH(replacer.way(f1_vSetIdx(i)))}) 240 241 val touch_sets = Seq.fill(2)(Wire(Vec(2, UInt(log2Ceil(nSets/2).W)))) 242 val touch_ways = Seq.fill(2)(Wire(Vec(2, Valid(UInt(log2Ceil(nWays).W)))) ) 243 244 ((replacers zip touch_sets) zip touch_ways).map{case ((r, s),w) => r.access(s,w)} 245 246 val f1_hit_data = VecInit(f1_datas.zipWithIndex.map { case(bank, i) => 247 val bank_hit_data = Mux1H(f1_bank_hit_vec(i).asUInt, bank) 248 bank_hit_data 249 }) 250 251 (0 until nWays).map{ w => 252 XSPerfAccumulate("line_0_hit_way_" + Integer.toString(w, 10), f1_fire && f1_bank_hit(0) && OHToUInt(f1_bank_hit_vec(0)) === w.U) 253 } 254 255 (0 until nWays).map{ w => 256 XSPerfAccumulate("line_0_victim_way_" + Integer.toString(w, 10), f1_fire && !f1_bank_hit(0) && OHToUInt(f1_victim_masks(0)) === w.U) 257 } 258 259 (0 until nWays).map{ w => 260 XSPerfAccumulate("line_1_hit_way_" + Integer.toString(w, 10), f1_fire && f1_doubleLine && f1_bank_hit(1) && OHToUInt(f1_bank_hit_vec(1)) === w.U) 261 } 262 263 (0 until nWays).map{ w => 264 XSPerfAccumulate("line_1_victim_way_" + Integer.toString(w, 10), f1_fire && f1_doubleLine && !f1_bank_hit(1) && OHToUInt(f1_victim_masks(1)) === w.U) 265 } 266 267 XSPerfAccumulate("ifu_bubble_f1_tlb_miss", f1_valid && !tlbRespAllValid ) 268 269 //--------------------------------------------- 270 // Fetch Stage 3 : 271 // * get data from last stage (hit from f1_hit_data/miss from missQueue response) 272 // * if at least one needed cacheline miss, wait for miss queue response (a wait_state machine) THIS IS TOO UGLY!!! 273 // * cut cacheline(s) and send to PreDecode 274 // * check if prediction is right (branch target and type, jump direction and type , jal target ) 275 //--------------------------------------------- 276 val f2_fetchFinish = Wire(Bool()) 277 278 val f2_valid = RegInit(false.B) 279 val f2_ftq_req = RegEnable(next = f1_ftq_req, enable = f1_fire) 280 val f2_situation = RegEnable(next = f1_situation, enable=f1_fire) 281 val f2_doubleLine = RegEnable(next = f1_doubleLine, enable=f1_fire) 282 val f2_fire = f2_valid && f2_fetchFinish && f3_ready 283 284 f2_ready := (f3_ready && f2_fetchFinish) || !f2_valid 285 286 when(f2_flush) {f2_valid := false.B} 287 .elsewhen(f1_fire && !f1_flush) {f2_valid := true.B } 288 .elsewhen(f2_fire) {f2_valid := false.B} 289 290 val pmpExcpAF = fromPMP.map(port => port.instr) 291 val mmio = fromPMP.map(port => port.mmio) // TODO: handle it 292 293 294 val f2_pAddrs = RegEnable(next = f1_pAddrs, enable = f1_fire) 295 val f2_hit = RegEnable(next = f1_hit , enable = f1_fire) 296 val f2_bank_hit = RegEnable(next = f1_bank_hit, enable = f1_fire) 297 val f2_miss = f2_valid && !f2_hit 298 val (f2_vSetIdx, f2_pTags) = (RegEnable(next = f1_vSetIdx, enable = f1_fire), RegEnable(next = f1_pTags, enable = f1_fire)) 299 val f2_waymask = RegEnable(next = f1_victim_masks, enable = f1_fire) 300 //exception information 301 val f2_except_pf = RegEnable(next = VecInit(tlbExcpPF), enable = f1_fire) 302 val f2_except_af = VecInit(RegEnable(next = VecInit(tlbExcpAF), enable = f1_fire).zip(pmpExcpAF).map(a => a._1 || DataHoldBypass(a._2, RegNext(f1_fire)).asBool)) 303 val f2_except = VecInit((0 until 2).map{i => f2_except_pf(i) || f2_except_af(i)}) 304 val f2_has_except = f2_valid && (f2_except_af.reduce(_||_) || f2_except_pf.reduce(_||_)) 305 //MMIO 306 val f2_mmio = DataHoldBypass(io.pmp(0).resp.mmio && !f2_except_af(0) && !f2_except_pf(0), RegNext(f1_fire)).asBool() 307 308 io.pmp.zipWithIndex.map { case (p, i) => 309 p.req.valid := f2_fire 310 p.req.bits.addr := f2_pAddrs(i) 311 p.req.bits.size := 3.U // TODO 312 p.req.bits.cmd := TlbCmd.exec 313 } 314 315 //instruction 316 val wait_idle :: wait_queue_ready :: wait_send_req :: wait_two_resp :: wait_0_resp :: wait_1_resp :: wait_one_resp ::wait_finish :: wait_send_mmio :: wait_mmio_resp ::Nil = Enum(10) 317 val wait_state = RegInit(wait_idle) 318 319 fromMissQueue.map{port => port.ready := true.B} 320 321 val (miss0_resp, miss1_resp) = (fromMissQueue(0).fire(), fromMissQueue(1).fire()) 322 val (bank0_fix, bank1_fix) = (miss0_resp && !f2_bank_hit(0), miss1_resp && f2_doubleLine && !f2_bank_hit(1)) 323 324 val only_0_miss = f2_valid && !f2_hit && !f2_doubleLine && !f2_has_except && !f2_mmio 325 val only_0_hit = f2_valid && f2_hit && !f2_doubleLine && !f2_mmio 326 val hit_0_hit_1 = f2_valid && f2_hit && f2_doubleLine && !f2_mmio 327 val (hit_0_miss_1 , miss_0_hit_1, miss_0_miss_1) = ( (f2_valid && !f2_bank_hit(1) && f2_bank_hit(0) && f2_doubleLine && !f2_has_except && !f2_mmio), 328 (f2_valid && !f2_bank_hit(0) && f2_bank_hit(1) && f2_doubleLine && !f2_has_except && !f2_mmio), 329 (f2_valid && !f2_bank_hit(0) && !f2_bank_hit(1) && f2_doubleLine && !f2_has_except && !f2_mmio), 330 ) 331 332 val hit_0_except_1 = f2_valid && f2_doubleLine && !f2_except(0) && f2_except(1) && f2_bank_hit(0) 333 val miss_0_except_1 = f2_valid && f2_doubleLine && !f2_except(0) && f2_except(1) && !f2_bank_hit(0) 334 //val fetch0_except_1 = hit_0_except_1 || miss_0_except_1 335 val except_0 = f2_valid && f2_except(0) 336 337 val f2_mq_datas = Reg(Vec(2, UInt(blockBits.W))) 338 val f2_mmio_data = Reg(UInt(maxInstrLen.W)) 339 340 when(fromMissQueue(0).fire) {f2_mq_datas(0) := fromMissQueue(0).bits.data} 341 when(fromMissQueue(1).fire) {f2_mq_datas(1) := fromMissQueue(1).bits.data} 342 when(fromUncache.fire()) {f2_mmio_data := fromUncache.bits.data} 343 344 switch(wait_state){ 345 is(wait_idle){ 346 when(f2_mmio && f2_valid && !f2_except_af(0) && !f2_except_pf(0)){ 347 wait_state := wait_send_mmio 348 }.elsewhen(miss_0_except_1){ 349 wait_state := Mux(toMissQueue(0).ready, wait_queue_ready ,wait_idle ) 350 }.elsewhen( only_0_miss || miss_0_hit_1){ 351 wait_state := Mux(toMissQueue(0).ready, wait_queue_ready ,wait_idle ) 352 }.elsewhen(hit_0_miss_1){ 353 wait_state := Mux(toMissQueue(1).ready, wait_queue_ready ,wait_idle ) 354 }.elsewhen( miss_0_miss_1 ){ 355 wait_state := Mux(toMissQueue(0).ready && toMissQueue(1).ready, wait_queue_ready ,wait_idle) 356 } 357 } 358 359 is(wait_send_mmio){ 360 wait_state := Mux(toUncache.fire(), wait_mmio_resp,wait_send_mmio ) 361 } 362 363 is(wait_mmio_resp){ 364 wait_state := Mux(fromUncache.fire(), wait_finish, wait_mmio_resp) 365 } 366 367 //TODO: naive logic for wait icache response 368 is(wait_queue_ready){ 369 wait_state := wait_send_req 370 } 371 372 is(wait_send_req) { 373 when(miss_0_except_1 || only_0_miss || hit_0_miss_1 || miss_0_hit_1){ 374 wait_state := wait_one_resp 375 }.elsewhen( miss_0_miss_1 ){ 376 wait_state := wait_two_resp 377 } 378 } 379 380 is(wait_one_resp) { 381 when( (miss_0_except_1 ||only_0_miss || miss_0_hit_1) && fromMissQueue(0).fire()){ 382 wait_state := wait_finish 383 }.elsewhen( hit_0_miss_1 && fromMissQueue(1).fire()){ 384 wait_state := wait_finish 385 } 386 } 387 388 is(wait_two_resp) { 389 when(fromMissQueue(0).fire() && fromMissQueue(1).fire()){ 390 wait_state := wait_finish 391 }.elsewhen( !fromMissQueue(0).fire() && fromMissQueue(1).fire() ){ 392 wait_state := wait_0_resp 393 }.elsewhen(fromMissQueue(0).fire() && !fromMissQueue(1).fire()){ 394 wait_state := wait_1_resp 395 } 396 } 397 398 is(wait_0_resp) { 399 when(fromMissQueue(0).fire()){ 400 wait_state := wait_finish 401 } 402 } 403 404 is(wait_1_resp) { 405 when(fromMissQueue(1).fire()){ 406 wait_state := wait_finish 407 } 408 } 409 410 is(wait_finish) { 411 when(f2_fire) {wait_state := wait_idle } 412 } 413 } 414 415 when(f2_flush) { wait_state := wait_idle } 416 417 (0 until 2).map { i => 418 if(i == 1) toMissQueue(i).valid := (hit_0_miss_1 || miss_0_miss_1) && wait_state === wait_queue_ready 419 else toMissQueue(i).valid := (only_0_miss || miss_0_hit_1 || miss_0_miss_1 || miss_0_except_1) && wait_state === wait_queue_ready 420 toMissQueue(i).bits.addr := f2_pAddrs(i) 421 toMissQueue(i).bits.vSetIdx := f2_vSetIdx(i) 422 toMissQueue(i).bits.waymask := f2_waymask(i) 423 toMissQueue(i).bits.clientID :=0.U 424 } 425 426 toUncache.valid := (wait_state === wait_send_mmio) && !f2_except_af(0) 427 //assert( (GTimer() < 5000.U && toUncache.fire()) || !toUncache.fire() ) 428 toUncache.bits.addr := f2_ftq_req.startAddr 429 430 fromUncache.ready := true.B 431 432 val miss_all_fix = (wait_state === wait_finish) 433 434 f2_fetchFinish := ((f2_valid && f2_hit) || miss_all_fix || hit_0_except_1 || except_0) 435 436 XSPerfAccumulate("ifu_bubble_f2_miss", f2_valid && !f2_fetchFinish ) 437 438 (touch_ways zip touch_sets).zipWithIndex.map{ case((t_w,t_s), i) => 439 t_s(0) := f1_vSetIdx(i) 440 t_w(0).valid := f1_bank_hit(i) 441 t_w(0).bits := OHToUInt(f1_bank_hit_vec(i)) 442 443 t_s(1) := f2_vSetIdx(i) 444 t_w(1).valid := f2_valid && !f2_bank_hit(i) 445 t_w(1).bits := OHToUInt(f2_waymask(i)) 446 } 447 448 val sec_miss_reg = RegInit(0.U.asTypeOf(Vec(4, Bool()))) 449 val reservedRefillData = Reg(Vec(2, UInt(blockBits.W))) 450 val f2_hit_datas = RegEnable(next = f1_hit_data, enable = f1_fire) 451 val f2_datas = Wire(Vec(2, UInt(blockBits.W))) 452 453 f2_datas.zipWithIndex.map{case(bank,i) => 454 if(i == 0) bank := Mux(f2_bank_hit(i), f2_hit_datas(i),Mux(sec_miss_reg(2),reservedRefillData(1),Mux(sec_miss_reg(0),reservedRefillData(0), f2_mq_datas(i)))) 455 else bank := Mux(f2_bank_hit(i), f2_hit_datas(i),Mux(sec_miss_reg(3),reservedRefillData(1),Mux(sec_miss_reg(1),reservedRefillData(0), f2_mq_datas(i)))) 456 } 457 458 val f2_jump_valids = Fill(PredictWidth, !preDecoderOut.cfiOffset.valid) | Fill(PredictWidth, 1.U(1.W)) >> (~preDecoderOut.cfiOffset.bits) 459 val f2_predecode_valids = VecInit(preDecoderOut.pd.map(instr => instr.valid)).asUInt & f2_jump_valids 460 461 def cut(cacheline: UInt, start: UInt) : Vec[UInt] ={ 462 if(HasCExtension){ 463 val result = Wire(Vec(PredictWidth + 1, UInt(16.W))) 464 val dataVec = cacheline.asTypeOf(Vec(blockBytes * 2/ 2, UInt(16.W))) 465 val startPtr = Cat(0.U(1.W), start(blockOffBits-1, 1)) 466 (0 until PredictWidth + 1).foreach( i => 467 result(i) := dataVec(startPtr + i.U) 468 ) 469 result 470 } else { 471 val result = Wire(Vec(PredictWidth, UInt(32.W)) ) 472 val dataVec = cacheline.asTypeOf(Vec(blockBytes * 2/ 4, UInt(32.W))) 473 val startPtr = Cat(0.U(1.W), start(blockOffBits-1, 2)) 474 (0 until PredictWidth).foreach( i => 475 result(i) := dataVec(startPtr + i.U) 476 ) 477 result 478 } 479 } 480 481 val f2_cut_data = cut( Cat(f2_datas.map(cacheline => cacheline.asUInt ).reverse).asUInt, f2_ftq_req.startAddr ) 482 when(f2_mmio){ 483 f2_cut_data(0) := f2_mmio_data(15, 0) 484 f2_cut_data(1) := f2_mmio_data(31, 16) 485 } 486 487 // deal with secondary miss in f1 488 val f2_0_f1_0 = ((f2_valid && !f2_bank_hit(0)) && f1_valid && (get_block_addr(f2_ftq_req.startAddr) === get_block_addr(f1_ftq_req.startAddr))) 489 val f2_0_f1_1 = ((f2_valid && !f2_bank_hit(0)) && f1_valid && f1_doubleLine && (get_block_addr(f2_ftq_req.startAddr) === get_block_addr(f1_ftq_req.startAddr + blockBytes.U))) 490 val f2_1_f1_0 = ((f2_valid && !f2_bank_hit(1) && f2_doubleLine) && f1_valid && (get_block_addr(f2_ftq_req.startAddr+ blockBytes.U) === get_block_addr(f1_ftq_req.startAddr) )) 491 val f2_1_f1_1 = ((f2_valid && !f2_bank_hit(1) && f2_doubleLine) && f1_valid && f1_doubleLine && (get_block_addr(f2_ftq_req.startAddr+ blockBytes.U) === get_block_addr(f1_ftq_req.startAddr + blockBytes.U) )) 492 493 val isSameLine = f2_0_f1_0 || f2_0_f1_1 || f2_1_f1_0 || f2_1_f1_1 494 val sec_miss_sit = VecInit(Seq(f2_0_f1_0, f2_0_f1_1, f2_1_f1_0, f2_1_f1_1)) 495 val hasSecMiss = RegInit(false.B) 496 497 when(f2_flush){ 498 sec_miss_reg.map(sig => sig := false.B) 499 hasSecMiss := false.B 500 }.elsewhen(isSameLine && !f1_flush && f2_fire){ 501 sec_miss_reg.zipWithIndex.map{case(sig, i) => sig := sec_miss_sit(i)} 502 hasSecMiss := true.B 503 }.elsewhen((!isSameLine || f1_flush) && hasSecMiss && f2_fire){ 504 sec_miss_reg.map(sig => sig := false.B) 505 hasSecMiss := false.B 506 } 507 508 when((f2_0_f1_0 || f2_0_f1_1) && f2_fire){ 509 reservedRefillData(0) := f2_mq_datas(0) 510 } 511 512 when((f2_1_f1_0 || f2_1_f1_1) && f2_fire){ 513 reservedRefillData(1) := f2_mq_datas(1) 514 } 515 516 517 //--------------------------------------------- 518 // Fetch Stage 4 : 519 // * get data from last stage (hit from f1_hit_data/miss from missQueue response) 520 // * if at least one needed cacheline miss, wait for miss queue response (a wait_state machine) THIS IS TOO UGLY!!! 521 // * cut cacheline(s) and send to PreDecode 522 // * check if prediction is right (branch target and type, jump direction and type , jal target ) 523 //--------------------------------------------- 524 val f3_valid = RegInit(false.B) 525 val f3_ftq_req = RegEnable(next = f2_ftq_req, enable=f2_fire) 526 val f3_situation = RegEnable(next = f2_situation, enable=f2_fire) 527 val f3_doubleLine = RegEnable(next = f2_doubleLine, enable=f2_fire) 528 val f3_fire = io.toIbuffer.fire() 529 530 when(f3_flush) {f3_valid := false.B} 531 .elsewhen(f2_fire && !f2_flush) {f3_valid := true.B } 532 .elsewhen(io.toIbuffer.fire()) {f3_valid := false.B} 533 534 f3_ready := io.toIbuffer.ready || !f2_valid 535 536 val f3_cut_data = RegEnable(next = f2_cut_data, enable=f2_fire) 537 val f3_except_pf = RegEnable(next = f2_except_pf, enable = f2_fire) 538 val f3_except_af = RegEnable(next = f2_except_af, enable = f2_fire) 539 val f3_hit = RegEnable(next = f2_hit , enable = f2_fire) 540 val f3_mmio = RegEnable(next = f2_mmio , enable = f2_fire) 541 542 val f3_lastHalf = RegInit(0.U.asTypeOf(new LastHalfInfo)) 543 val f3_lastHalfMatch = f3_lastHalf.matchThisBlock(f3_ftq_req.startAddr) 544 val f3_except = VecInit((0 until 2).map{i => f3_except_pf(i) || f3_except_af(i)}) 545 val f3_has_except = f3_valid && (f3_except_af.reduce(_||_) || f3_except_pf.reduce(_||_)) 546 547 //performance counter 548 val f3_only_0_hit = RegEnable(next = only_0_hit, enable = f2_fire) 549 val f3_only_0_miss = RegEnable(next = only_0_miss, enable = f2_fire) 550 val f3_hit_0_hit_1 = RegEnable(next = hit_0_hit_1, enable = f2_fire) 551 val f3_hit_0_miss_1 = RegEnable(next = hit_0_miss_1, enable = f2_fire) 552 val f3_miss_0_hit_1 = RegEnable(next = miss_0_hit_1, enable = f2_fire) 553 val f3_miss_0_miss_1 = RegEnable(next = miss_0_miss_1, enable = f2_fire) 554 555 val f3_bank_hit = RegEnable(next = f2_bank_hit, enable = f2_fire) 556 val f3_req_0 = io.toIbuffer.fire() 557 val f3_req_1 = io.toIbuffer.fire() && f3_doubleLine 558 val f3_hit_0 = io.toIbuffer.fire() & f3_bank_hit(0) 559 val f3_hit_1 = io.toIbuffer.fire() && f3_doubleLine & f3_bank_hit(1) 560 561 preDecoderIn.instValid := f3_valid && !f3_has_except 562 preDecoderIn.data := f3_cut_data 563 preDecoderIn.startAddr := f3_ftq_req.startAddr 564 preDecoderIn.fallThruAddr := f3_ftq_req.fallThruAddr 565 preDecoderIn.fallThruError := f3_ftq_req.fallThruError 566 preDecoderIn.isDoubleLine := f3_doubleLine 567 preDecoderIn.ftqOffset := f3_ftq_req.ftqOffset 568 preDecoderIn.target := f3_ftq_req.target 569 preDecoderIn.oversize := f3_ftq_req.oversize 570 preDecoderIn.lastHalfMatch := f3_lastHalfMatch 571 preDecoderIn.pageFault := f3_except_pf 572 preDecoderIn.accessFault := f3_except_af 573 preDecoderIn.mmio := f3_mmio 574 575 576 // TODO: What if next packet does not match? 577 when (f3_flush) { 578 f3_lastHalf.valid := false.B 579 }.elsewhen (io.toIbuffer.fire()) { 580 f3_lastHalf.valid := preDecoderOut.hasLastHalf 581 f3_lastHalf.middlePC := preDecoderOut.realEndPC 582 } 583 584 val f3_predecode_range = VecInit(preDecoderOut.pd.map(inst => inst.valid)).asUInt 585 val f3_mmio_range = VecInit((0 until PredictWidth).map(i => if(i ==0) true.B else false.B)) 586 587 io.toIbuffer.valid := f3_valid 588 io.toIbuffer.bits.instrs := preDecoderOut.instrs 589 io.toIbuffer.bits.valid := Mux(f3_mmio, f3_mmio_range.asUInt, f3_predecode_range & preDecoderOut.instrRange.asUInt) 590 io.toIbuffer.bits.pd := preDecoderOut.pd 591 io.toIbuffer.bits.ftqPtr := f3_ftq_req.ftqIdx 592 io.toIbuffer.bits.pc := preDecoderOut.pc 593 io.toIbuffer.bits.ftqOffset.zipWithIndex.map{case(a, i) => a.bits := i.U; a.valid := preDecoderOut.takens(i) && !f3_mmio} 594 io.toIbuffer.bits.foldpc := preDecoderOut.pc.map(i => XORFold(i(VAddrBits-1,1), MemPredPCWidth)) 595 io.toIbuffer.bits.ipf := preDecoderOut.pageFault 596 io.toIbuffer.bits.acf := preDecoderOut.accessFault 597 io.toIbuffer.bits.crossPageIPFFix := preDecoderOut.crossPageIPF 598 599 //Write back to Ftq 600 val finishFetchMaskReg = RegNext(f3_valid && !(f2_fire && !f2_flush)) 601 602 val f3_mmio_missOffset = Wire(ValidUndirectioned(UInt(log2Ceil(PredictWidth).W))) 603 f3_mmio_missOffset.valid := f3_mmio 604 f3_mmio_missOffset.bits := 0.U 605 606 toFtq.pdWb.valid := !finishFetchMaskReg && f3_valid 607 toFtq.pdWb.bits.pc := preDecoderOut.pc 608 toFtq.pdWb.bits.pd := preDecoderOut.pd 609 toFtq.pdWb.bits.pd.zipWithIndex.map{case(instr,i) => instr.valid := Mux(f3_mmio, f3_mmio_range(i), f3_predecode_range(i))} 610 toFtq.pdWb.bits.ftqIdx := f3_ftq_req.ftqIdx 611 toFtq.pdWb.bits.ftqOffset := f3_ftq_req.ftqOffset.bits 612 toFtq.pdWb.bits.misOffset := Mux(f3_mmio, f3_mmio_missOffset, preDecoderOut.misOffset) 613 toFtq.pdWb.bits.cfiOffset := preDecoderOut.cfiOffset 614 toFtq.pdWb.bits.target := Mux(f3_mmio,Mux(toFtq.pdWb.bits.pd(0).isRVC, toFtq.pdWb.bits.pc(0) + 2.U , toFtq.pdWb.bits.pc(0)+4.U) ,preDecoderOut.target) 615 toFtq.pdWb.bits.jalTarget := preDecoderOut.jalTarget 616 toFtq.pdWb.bits.instrRange := Mux(f3_mmio, f3_mmio_range, preDecoderOut.instrRange) 617 618 val predecodeFlush = ((preDecoderOut.misOffset.valid || f3_mmio) && f3_valid) 619 val predecodeFlushReg = RegNext(predecodeFlush && !(f2_fire && !f2_flush)) 620 621 val perfinfo = IO(new Bundle(){ 622 val perfEvents = Output(new PerfEventsBundle(15)) 623 }) 624 625 val perfEvents = Seq( 626 ("frontendFlush ", f3_redirect ), 627 ("ifu_req ", io.toIbuffer.fire() ), 628 ("ifu_miss ", io.toIbuffer.fire() && !f3_hit ), 629 ("ifu_req_cacheline_0 ", f3_req_0 ), 630 ("ifu_req_cacheline_1 ", f3_req_1 ), 631 ("ifu_req_cacheline_0_hit ", f3_hit_1 ), 632 ("ifu_req_cacheline_1_hit ", f3_hit_1 ), 633 ("only_0_hit ", f3_only_0_hit && io.toIbuffer.fire() ), 634 ("only_0_miss ", f3_only_0_miss && io.toIbuffer.fire() ), 635 ("hit_0_hit_1 ", f3_hit_0_hit_1 && io.toIbuffer.fire() ), 636 ("hit_0_miss_1 ", f3_hit_0_miss_1 && io.toIbuffer.fire() ), 637 ("miss_0_hit_1 ", f3_miss_0_hit_1 && io.toIbuffer.fire() ), 638 ("miss_0_miss_1 ", f3_miss_0_miss_1 && io.toIbuffer.fire() ), 639 ("cross_line_block ", io.toIbuffer.fire() && f3_situation(0) ), 640 ("fall_through_is_cacheline_end", io.toIbuffer.fire() && f3_situation(1) ), 641 ) 642 643 for (((perf_out,(perf_name,perf)),i) <- perfinfo.perfEvents.perf_events.zip(perfEvents).zipWithIndex) { 644 perf_out.incr_step := RegNext(perf) 645 } 646 647 f3_redirect := !predecodeFlushReg && predecodeFlush 648 649 XSPerfAccumulate("ifu_req", io.toIbuffer.fire() ) 650 XSPerfAccumulate("ifu_miss", io.toIbuffer.fire() && !f3_hit ) 651 XSPerfAccumulate("ifu_req_cacheline_0", f3_req_0 ) 652 XSPerfAccumulate("ifu_req_cacheline_1", f3_req_1 ) 653 XSPerfAccumulate("ifu_req_cacheline_0_hit", f3_hit_0 ) 654 XSPerfAccumulate("ifu_req_cacheline_1_hit", f3_hit_1 ) 655 XSPerfAccumulate("frontendFlush", f3_redirect ) 656 XSPerfAccumulate("only_0_hit", f3_only_0_hit && io.toIbuffer.fire() ) 657 XSPerfAccumulate("only_0_miss", f3_only_0_miss && io.toIbuffer.fire() ) 658 XSPerfAccumulate("hit_0_hit_1", f3_hit_0_hit_1 && io.toIbuffer.fire() ) 659 XSPerfAccumulate("hit_0_miss_1", f3_hit_0_miss_1 && io.toIbuffer.fire() ) 660 XSPerfAccumulate("miss_0_hit_1", f3_miss_0_hit_1 && io.toIbuffer.fire() ) 661 XSPerfAccumulate("miss_0_miss_1", f3_miss_0_miss_1 && io.toIbuffer.fire() ) 662 XSPerfAccumulate("cross_line_block", io.toIbuffer.fire() && f3_situation(0) ) 663 XSPerfAccumulate("fall_through_is_cacheline_end", io.toIbuffer.fire() && f3_situation(1) ) 664} 665