1package xiangshan.frontend 2 3import chisel3._ 4import chisel3.util._ 5import device.RAMHelper 6import xiangshan._ 7import utils._ 8import xiangshan.cache._ 9import chisel3.experimental.chiselName 10 11trait HasIFUConst extends HasXSParameter { 12 val resetVector = 0x80000000L//TODO: set reset vec 13 def align(pc: UInt, bytes: Int): UInt = Cat(pc(VAddrBits-1, log2Ceil(bytes)), 0.U(log2Ceil(bytes).W)) 14 val groupBytes = FetchWidth * 4 * 2 // correspond to cache line size 15 val groupOffsetBits = log2Ceil(groupBytes) 16 val nBanksInPacket = 2 17 val bankBytes = PredictWidth * 2 / nBanksInPacket 18 val nBanksInGroup = groupBytes / bankBytes 19 val bankWidth = PredictWidth / nBanksInPacket 20 val bankOffsetBits = log2Ceil(bankBytes) 21 // (0, nBanksInGroup-1) 22 def bankInGroup(pc: UInt) = pc(groupOffsetBits-1,bankOffsetBits) 23 def isInLastBank(pc: UInt) = bankInGroup(pc) === (nBanksInGroup-1).U 24 // (0, bankBytes/2-1) 25 def offsetInBank(pc: UInt) = pc(bankOffsetBits-1,1) 26 def bankAligned(pc: UInt) = align(pc, bankBytes) 27 def groupAligned(pc: UInt) = align(pc, groupBytes) 28 // each 1 bit in mask stands for 2 Bytes 29 // 8 bits, in which only the first 7 bits could be 0 30 def maskFirstHalf(pc: UInt): UInt = ((~(0.U(bankWidth.W))) >> offsetInBank(pc))(bankWidth-1,0) 31 // when in loop(buffer), we need to make use of the full packet 32 // and get the real mask in iCacheResp from loop buffer 33 // we may make predictions on more instructions than we could get from loop buffer 34 // and this will be handled in if4 35 def maskLastHalf(pc: UInt, inLoop: Bool = false.B): UInt = Mux(isInLastBank(pc) && !inLoop, 0.U(bankWidth.W), ~0.U(bankWidth.W)) 36 def mask(pc: UInt, inLoop: Bool = false.B): UInt = Reverse(Cat(maskFirstHalf(pc), maskLastHalf(pc, inLoop))) 37 def snpc(pc: UInt, inLoop: Bool = false.B): UInt = pc + (PopCount(mask(pc, inLoop)) << 1) 38 39 val enableGhistRepair = true 40 val IFUDebug = true 41} 42 43class GlobalHistory extends XSBundle { 44 val predHist = UInt(HistoryLength.W) 45 // val sawNTBr = Bool() 46 // val takenOnBr = Bool() 47 // val saveHalfRVI = Bool() 48 // def shifted = takenOnBr || sawNTBr 49 // def newPtr(ptr: UInt = nowPtr): UInt = Mux(shifted, ptr - 1.U, ptr) 50 def update(sawNTBr: Bool, takenOnBr: Bool, hist: UInt = predHist): GlobalHistory = { 51 val g = Wire(new GlobalHistory) 52 val shifted = takenOnBr || sawNTBr 53 g.predHist := Mux(shifted, (hist << 1) | takenOnBr.asUInt, hist) 54 g 55 } 56 57 final def === (that: GlobalHistory): Bool = { 58 predHist === that.predHist 59 } 60 61 final def =/= (that: GlobalHistory): Bool = !(this === that) 62 63 implicit val name = "IFU" 64 def debug(where: String) = XSDebug(p"[${where}_GlobalHistory] hist=${Binary(predHist)}\n") 65 // override def toString(): String = "histPtr=%d, sawNTBr=%d, takenOnBr=%d, saveHalfRVI=%d".format(histPtr, sawNTBr, takenOnBr, saveHalfRVI) 66} 67 68 69class IFUIO extends XSBundle 70{ 71 val fetchPacket = DecoupledIO(new FetchPacket) 72 val redirect = Flipped(ValidIO(UInt(VAddrBits.W))) 73 // val cfiUpdateInfo = Flipped(ValidIO(new CfiUpdateInfo)) 74 val cfiUpdateInfo = Flipped(ValidIO(new CfiUpdateInfo)) 75 val icacheReq = DecoupledIO(new ICacheReq) 76 val icacheResp = Flipped(DecoupledIO(new ICacheResp)) 77 val icacheFlush = Output(UInt(2.W)) 78 // val loopBufPar = Flipped(new LoopBufferParameters) 79} 80 81class PrevHalfInstr extends XSBundle { 82 val valid = Bool() 83 val taken = Bool() 84 val ghInfo = new GlobalHistory() 85 val fetchpc = UInt(VAddrBits.W) // only for debug 86 val idx = UInt(VAddrBits.W) // only for debug 87 val pc = UInt(VAddrBits.W) 88 val npc = UInt(VAddrBits.W) 89 val target = UInt(VAddrBits.W) 90 val instr = UInt(16.W) 91 val ipf = Bool() 92 val newPtr = UInt(log2Up(ExtHistoryLength).W) 93} 94 95@chiselName 96class IFU extends XSModule with HasIFUConst 97{ 98 val io = IO(new IFUIO) 99 val bpu = BPU(EnableBPU) 100 val pd = Module(new PreDecode) 101 val loopBuffer = if(EnableLB) { Module(new LoopBuffer) } else { Module(new FakeLoopBuffer) } 102 103 val if2_redirect, if3_redirect, if4_redirect = WireInit(false.B) 104 val if1_flush, if2_flush, if3_flush, if4_flush = WireInit(false.B) 105 106 val loopBufPar = loopBuffer.io.loopBufPar 107 val inLoop = WireInit(loopBuffer.io.out.valid) 108 val icacheResp = WireInit(Mux(inLoop, loopBuffer.io.out.bits, io.icacheResp.bits)) 109 110 if4_flush := io.redirect.valid || loopBufPar.LBredirect.valid 111 if3_flush := if4_flush || if4_redirect 112 if2_flush := if3_flush || if3_redirect 113 if1_flush := if2_flush || if2_redirect 114 115 loopBuffer.io.flush := io.redirect.valid 116 117 //********************** IF1 ****************************// 118 val if1_valid = !reset.asBool && GTimer() > 500.U 119 val if1_npc = WireInit(0.U(VAddrBits.W)) 120 val if2_ready = WireInit(false.B) 121 val if2_allReady = WireInit(if2_ready && (inLoop || io.icacheReq.ready)) 122 val if1_fire = if1_valid && (if2_allReady || if1_flush) 123 124 125 // val if2_newPtr, if3_newPtr, if4_newPtr = Wire(UInt(log2Up(ExtHistoryLength).W)) 126 127 val if1_gh, if2_gh, if3_gh, if4_gh = Wire(new GlobalHistory) 128 val if2_predicted_gh, if3_predicted_gh, if4_predicted_gh = Wire(new GlobalHistory) 129 val final_gh = RegInit(0.U.asTypeOf(new GlobalHistory)) 130 val final_gh_bypass = WireInit(0.U.asTypeOf(new GlobalHistory)) 131 val flush_final_gh = WireInit(false.B) 132 133 //********************** IF2 ****************************// 134 val if2_valid = RegInit(init = false.B) 135 val if3_ready = WireInit(false.B) 136 val if2_fire = if2_valid && if3_ready 137 val if2_pc = RegEnable(next = if1_npc, init = resetVector.U, enable = if1_fire) 138 val if2_snpc = snpc(if2_pc, inLoop) 139 val if2_predHist = RegEnable(if1_gh.predHist, enable=if1_fire) 140 if2_ready := if3_ready || !if2_valid 141 when (if1_fire) { if2_valid := true.B } 142 .elsewhen (if2_flush) { if2_valid := false.B } 143 .elsewhen (if2_fire) { if2_valid := false.B } 144 145 val npcGen = new PriorityMuxGenerator[UInt] 146 npcGen.register(true.B, RegNext(if1_npc)) 147 npcGen.register(if2_fire, if2_snpc) 148 val if2_bp = bpu.io.out(0) 149 150 // if taken, bp_redirect should be true 151 // when taken on half RVI, we suppress this redirect signal 152 if2_redirect := if2_valid && if2_bp.taken 153 npcGen.register(if2_redirect, if2_bp.target) 154 155 if2_predicted_gh := if2_gh.update(if2_bp.hasNotTakenBrs, if2_bp.takenOnBr) 156 157 //********************** IF3 ****************************// 158 val if3_valid = RegInit(init = false.B) 159 val if4_ready = WireInit(false.B) 160 val if3_allValid = if3_valid && (inLoop || io.icacheResp.valid) 161 val if3_fire = if3_allValid && if4_ready 162 val if3_pc = RegEnable(if2_pc, if2_fire) 163 val if3_predHist = RegEnable(if2_predHist, enable=if2_fire) 164 if3_ready := if4_ready || !if3_valid 165 when (if3_flush) { 166 if3_valid := false.B 167 }.elsewhen (if2_fire && !if2_flush) { 168 if3_valid := true.B 169 }.elsewhen (if3_fire) { 170 if3_valid := false.B 171 } 172 173 val if3_bp = bpu.io.out(1) 174 if3_predicted_gh := if3_gh.update(if3_bp.hasNotTakenBrs, if3_bp.takenOnBr) 175 176 177 val prevHalfInstrReq = Wire(new PrevHalfInstr) 178 // only valid when if4_fire 179 val hasPrevHalfInstrReq = prevHalfInstrReq.valid 180 181 val if3_prevHalfInstr = RegInit(0.U.asTypeOf(new PrevHalfInstr)) 182 183 // 32-bit instr crosses 2 pages, and the higher 16-bit triggers page fault 184 val crossPageIPF = WireInit(false.B) 185 186 val if3_pendingPrevHalfInstr = if3_prevHalfInstr.valid 187 188 // the previous half of RVI instruction waits until it meets its last half 189 val if3_prevHalfInstrMet = if3_pendingPrevHalfInstr && if3_prevHalfInstr.npc === if3_pc && if3_allValid 190 // set to invalid once consumed or redirect from backend 191 val if3_prevHalfConsumed = if3_prevHalfInstrMet && if3_fire 192 val if3_prevHalfFlush = if4_flush 193 when (hasPrevHalfInstrReq) { 194 if3_prevHalfInstr := prevHalfInstrReq 195 }.elsewhen (if3_prevHalfConsumed || if3_prevHalfFlush) { 196 if3_prevHalfInstr.valid := false.B 197 } 198 199 // when bp signal a redirect, we distinguish between taken and not taken 200 // if taken and saveHalfRVI is true, we do not redirect to the target 201 202 def if3_nextValidPCNotEquals(pc: UInt) = !if2_valid || if2_valid && if2_pc =/= pc 203 val if3_prevHalfMetRedirect = if3_pendingPrevHalfInstr && if3_prevHalfInstrMet && if3_prevHalfInstr.taken && if3_nextValidPCNotEquals(if3_prevHalfInstr.target) 204 val if3_prevHalfNotMetRedirect = if3_pendingPrevHalfInstr && !if3_prevHalfInstrMet && if3_nextValidPCNotEquals(if3_prevHalfInstr.pc + 2.U) 205 val if3_predTakenRedirect = !if3_pendingPrevHalfInstr && if3_bp.taken && if3_nextValidPCNotEquals(if3_bp.target) 206 val if3_predNotTakenRedirect = !if3_pendingPrevHalfInstr && !if3_bp.taken && if3_nextValidPCNotEquals(snpc(if3_pc, inLoop)) 207 // when pendingPrevHalfInstr, if3_GHInfo is set to the info of last prev half instr 208 // val if3_ghInfoNotIdenticalRedirect = !if3_pendingPrevHalfInstr && if3_GHInfo =/= if3_lastGHInfo && enableGhistRepair.B 209 210 if3_redirect := if3_allValid && ( 211 // prevHalf is consumed but the next packet is not where it meant to be 212 // we do not handle this condition because of the burden of building a correct GHInfo 213 // prevHalfMetRedirect || 214 // prevHalf does not match if3_pc and the next fetch packet is not snpc 215 if3_prevHalfNotMetRedirect || 216 // pred taken and next fetch packet is not the predicted target 217 if3_predTakenRedirect || 218 // pred not taken and next fetch packet is not snpc 219 if3_predNotTakenRedirect 220 // GHInfo from last pred does not corresponds with this packet 221 // if3_ghInfoNotIdenticalRedirect 222 ) 223 224 val if3_target = WireInit(snpc(if3_pc)) 225 226 /* when (prevHalfMetRedirect) { 227 if1_npc := if3_prevHalfInstr.target 228 }.else */ 229 when (if3_prevHalfNotMetRedirect) { 230 if3_target := if3_prevHalfInstr.pc + 2.U 231 }.elsewhen (if3_predTakenRedirect) { 232 if3_target := if3_bp.target 233 }.elsewhen (if3_predNotTakenRedirect) { 234 if3_target := snpc(if3_pc) 235 } 236 // }.elsewhen (if3_ghInfoNotIdenticalRedirect) { 237 // if3_target := Mux(if3_bp.taken, if3_bp.target, snpc(if3_pc)) 238 // } 239 npcGen.register(if3_redirect, if3_target) 240 241 // when (if3_redirect) { 242 // if1_npc := if3_target 243 // } 244 245 //********************** IF4 ****************************// 246 val if4_pd = RegEnable(pd.io.out, if3_fire) 247 val if4_ipf = RegEnable(icacheResp.ipf || if3_prevHalfInstrMet && if3_prevHalfInstr.ipf, if3_fire) 248 val if4_acf = RegEnable(icacheResp.acf, if3_fire) 249 val if4_crossPageIPF = RegEnable(crossPageIPF, if3_fire) 250 val if4_valid = RegInit(false.B) 251 val if4_fire = if4_valid && io.fetchPacket.ready 252 val if4_pc = RegEnable(if3_pc, if3_fire) 253 // This is the real mask given from icache or loop buffer 254 val if4_mask = RegEnable(icacheResp.mask, if3_fire) 255 val if4_snpc = Mux(inLoop, if4_pc + (PopCount(if4_mask) << 1), snpc(if4_pc)) 256 257 258 val if4_predHist = RegEnable(if3_predHist, enable=if3_fire) 259 // wait until prevHalfInstr written into reg 260 if4_ready := (io.fetchPacket.ready && !hasPrevHalfInstrReq || !if4_valid) && GTimer() > 500.U 261 when (if4_flush) { 262 if4_valid := false.B 263 }.elsewhen (if3_fire && !if3_flush) { 264 if4_valid := true.B 265 }.elsewhen (if4_fire) { 266 if4_valid := false.B 267 } 268 269 val if4_bp = Wire(new BranchPrediction) 270 if4_bp := bpu.io.out(2) 271 if4_bp.takens := bpu.io.out(2).takens & if4_mask 272 if4_bp.brMask := bpu.io.out(2).brMask & if4_mask 273 if4_bp.jalMask := bpu.io.out(2).jalMask & if4_mask 274 275 if4_predicted_gh := if4_gh.update(if4_bp.hasNotTakenBrs, if4_bp.takenOnBr) 276 277 def cal_jal_tgt(inst: UInt, rvc: Bool): UInt = { 278 Mux(rvc, 279 SignExt(Cat(inst(12), inst(8), inst(10, 9), inst(6), inst(7), inst(2), inst(11), inst(5, 3), 0.U(1.W)), XLEN), 280 SignExt(Cat(inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)), XLEN) 281 ) 282 } 283 val if4_instrs = if4_pd.instrs 284 val if4_jals = if4_bp.jalMask 285 val if4_jal_tgts = VecInit((0 until PredictWidth).map(i => if4_pd.pc(i) + cal_jal_tgt(if4_instrs(i), if4_pd.pd(i).isRVC))) 286 287 (0 until PredictWidth).foreach {i => 288 when (if4_jals(i)) { 289 if4_bp.targets(i) := if4_jal_tgts(i) 290 } 291 } 292 293 // we need this to tell BPU the prediction of prev half 294 // because the prediction is with the start of each inst 295 val if4_prevHalfInstr = RegInit(0.U.asTypeOf(new PrevHalfInstr)) 296 val if4_pendingPrevHalfInstr = if4_prevHalfInstr.valid 297 val if4_prevHalfInstrMet = if4_pendingPrevHalfInstr && if4_prevHalfInstr.npc === if4_pc && if4_valid 298 val if4_prevHalfConsumed = if4_prevHalfInstrMet && if4_fire 299 val if4_prevHalfFlush = if4_flush 300 301 val if4_takenPrevHalf = WireInit(if4_prevHalfInstrMet && if4_prevHalfInstr.taken) 302 when (if3_prevHalfConsumed) { 303 if4_prevHalfInstr := if3_prevHalfInstr 304 }.elsewhen (if4_prevHalfConsumed || if4_prevHalfFlush) { 305 if4_prevHalfInstr.valid := false.B 306 } 307 308 prevHalfInstrReq := 0.U.asTypeOf(new PrevHalfInstr) 309 when (if4_fire && if4_bp.saveHalfRVI) { 310 val idx = if4_bp.lastHalfRVIIdx 311 prevHalfInstrReq.valid := true.B 312 // this is result of the last half RVI 313 prevHalfInstrReq.taken := if4_bp.lastHalfRVITaken 314 prevHalfInstrReq.ghInfo := if4_gh 315 prevHalfInstrReq.newPtr := DontCare 316 prevHalfInstrReq.fetchpc := if4_pc 317 prevHalfInstrReq.idx := idx 318 prevHalfInstrReq.pc := if4_pd.pc(idx) 319 prevHalfInstrReq.npc := if4_pd.pc(idx) + 2.U 320 prevHalfInstrReq.target := if4_bp.lastHalfRVITarget 321 prevHalfInstrReq.instr := if4_pd.instrs(idx)(15, 0) 322 prevHalfInstrReq.ipf := if4_ipf 323 } 324 325 def if4_nextValidPCNotEquals(pc: UInt) = if3_valid && if3_pc =/= pc || 326 !if3_valid && (if2_valid && if2_pc =/= pc) || 327 !if3_valid && !if2_valid 328 329 val if4_prevHalfNextNotMet = hasPrevHalfInstrReq && if4_nextValidPCNotEquals(prevHalfInstrReq.pc+2.U) 330 val if4_predTakenRedirect = !hasPrevHalfInstrReq && if4_bp.taken && if4_nextValidPCNotEquals(if4_bp.target) 331 val if4_predNotTakenRedirect = !hasPrevHalfInstrReq && !if4_bp.taken && if4_nextValidPCNotEquals(if4_snpc) 332 // val if4_ghInfoNotIdenticalRedirect = if4_GHInfo =/= if4_lastGHInfo && enableGhistRepair.B 333 334 if4_redirect := if4_valid && ( 335 // when if4 has a lastHalfRVI, but the next fetch packet is not snpc 336 // if4_prevHalfNextNotMet || 337 // when if4 preds taken, but the pc of next fetch packet is not the target 338 if4_predTakenRedirect || 339 // when if4 preds not taken, but the pc of next fetch packet is not snpc 340 if4_predNotTakenRedirect 341 // GHInfo from last pred does not corresponds with this packet 342 // if4_ghInfoNotIdenticalRedirect 343 ) 344 345 val if4_target = WireInit(if4_snpc) 346 347 // when (if4_prevHalfNextNotMet) { 348 // if4_target := prevHalfInstrReq.pc+2.U 349 // }.else 350 when (if4_predTakenRedirect) { 351 if4_target := if4_bp.target 352 }.elsewhen (if4_predNotTakenRedirect) { 353 if4_target := if4_snpc 354 } 355 // }.elsewhen (if4_ghInfoNotIdenticalRedirect) { 356 // if4_target := Mux(if4_bp.taken, if4_bp.target, if4_snpc) 357 // } 358 npcGen.register(if4_redirect, if4_target) 359 360 when (if4_fire) { 361 final_gh := if4_predicted_gh 362 } 363 if4_gh := Mux(flush_final_gh, final_gh_bypass, final_gh) 364 if3_gh := Mux(if4_valid && !if4_flush, if4_predicted_gh, if4_gh) 365 if2_gh := Mux(if3_valid && !if3_flush, if3_predicted_gh, if3_gh) 366 if1_gh := Mux(if2_valid && !if2_flush, if2_predicted_gh, if2_gh) 367 368 369 370 371 val cfiUpdate = io.cfiUpdateInfo 372 when (cfiUpdate.valid && (cfiUpdate.bits.isMisPred || cfiUpdate.bits.isReplay)) { 373 val b = cfiUpdate.bits 374 val oldGh = b.bpuMeta.hist 375 val sawNTBr = b.bpuMeta.sawNotTakenBranch 376 val isBr = b.pd.isBr 377 val taken = b.taken 378 val updatedGh = oldGh.update(sawNTBr, isBr && taken) 379 final_gh := updatedGh 380 final_gh_bypass := updatedGh 381 flush_final_gh := true.B 382 } 383 384 npcGen.register(loopBufPar.LBredirect.valid, loopBufPar.LBredirect.bits) 385 npcGen.register(io.redirect.valid, io.redirect.bits) 386 npcGen.register(RegNext(reset.asBool) && !reset.asBool, resetVector.U(VAddrBits.W)) 387 388 if1_npc := npcGen() 389 390 when(inLoop) { 391 io.icacheReq.valid := if4_flush 392 }.otherwise { 393 io.icacheReq.valid := if1_valid && if2_ready 394 } 395 io.icacheResp.ready := if4_ready 396 io.icacheReq.bits.addr := if1_npc 397 398 // when(if4_bp.taken) { 399 // when(if4_bp.saveHalfRVI) { 400 // io.loopBufPar.LBReq := snpc(if4_pc) 401 // }.otherwise { 402 // io.loopBufPar.LBReq := if4_bp.target 403 // } 404 // }.otherwise { 405 // io.loopBufPar.LBReq := snpc(if4_pc) 406 // XSDebug(p"snpc(if4_pc)=${Hexadecimal(snpc(if4_pc))}\n") 407 // } 408 loopBufPar.fetchReq := if3_pc 409 410 io.icacheReq.bits.mask := mask(if1_npc) 411 412 io.icacheFlush := Cat(if3_flush, if2_flush) 413 414 bpu.io.cfiUpdateInfo <> io.cfiUpdateInfo 415 416 // bpu.io.flush := Cat(if4_flush, if3_flush, if2_flush) 417 bpu.io.flush := VecInit(if2_flush, if3_flush, if4_flush) 418 bpu.io.inFire(0) := if1_fire 419 bpu.io.inFire(1) := if2_fire 420 bpu.io.inFire(2) := if3_fire 421 bpu.io.inFire(3) := if4_fire 422 bpu.io.in.pc := if1_npc 423 bpu.io.in.hist := if1_gh.asUInt 424 // bpu.io.in.histPtr := ptr 425 bpu.io.in.inMask := mask(if1_npc) 426 bpu.io.predecode.mask := if4_pd.mask 427 bpu.io.predecode.lastHalf := if4_pd.lastHalf 428 bpu.io.predecode.pd := if4_pd.pd 429 bpu.io.predecode.hasLastHalfRVI := if4_prevHalfInstrMet 430 bpu.io.realMask := if4_mask 431 bpu.io.prevHalf := if4_prevHalfInstr 432 433 pd.io.in := icacheResp 434 when(inLoop) { 435 pd.io.in.mask := loopBuffer.io.out.bits.mask // TODO: Maybe this is unnecessary 436 // XSDebug("Fetch from LB\n") 437 // XSDebug(p"pc=${Hexadecimal(io.loopBufPar.LBResp.pc)}\n") 438 // XSDebug(p"data=${Hexadecimal(io.loopBufPar.LBResp.data)}\n") 439 // XSDebug(p"mask=${Hexadecimal(io.loopBufPar.LBResp.mask)}\n") 440 } 441 442 pd.io.prev.valid := if3_prevHalfInstrMet 443 pd.io.prev.bits := if3_prevHalfInstr.instr 444 // if a fetch packet triggers page fault, set the pf instruction to nop 445 when (!if3_prevHalfInstrMet && icacheResp.ipf) { 446 val instrs = Wire(Vec(FetchWidth, UInt(32.W))) 447 (0 until FetchWidth).foreach(i => instrs(i) := ZeroExt("b0010011".U, 32)) // nop 448 pd.io.in.data := instrs.asUInt 449 }.elsewhen (if3_prevHalfInstrMet && (if3_prevHalfInstr.ipf || icacheResp.ipf)) { 450 pd.io.prev.bits := ZeroExt("b0010011".U, 16) 451 val instrs = Wire(Vec(FetchWidth, UInt(32.W))) 452 (0 until FetchWidth).foreach(i => instrs(i) := Cat(ZeroExt("b0010011".U, 16), Fill(16, 0.U(1.W)))) 453 pd.io.in.data := instrs.asUInt 454 455 when (icacheResp.ipf && !if3_prevHalfInstr.ipf) { crossPageIPF := true.B } // higher 16 bits page fault 456 } 457 458 //Performance Counter 459 // if (!env.FPGAPlatform ) { 460 // ExcitingUtils.addSource(io.fetchPacket.fire && !inLoop, "CntFetchFromICache", Perf) 461 // ExcitingUtils.addSource(io.fetchPacket.fire && inLoop, "CntFetchFromLoopBuffer", Perf) 462 // } 463 464 val fetchPacketValid = if4_valid && !io.redirect.valid 465 val fetchPacketWire = Wire(new FetchPacket) 466 467 // io.fetchPacket.valid := if4_valid && !io.redirect.valid 468 fetchPacketWire.instrs := if4_pd.instrs 469 fetchPacketWire.mask := if4_pd.mask & (Fill(PredictWidth, !if4_bp.taken) | (Fill(PredictWidth, 1.U(1.W)) >> (~if4_bp.jmpIdx))) 470 fetchPacketWire.pdmask := if4_pd.mask 471 472 loopBufPar.noTakenMask := if4_pd.mask 473 fetchPacketWire.pc := if4_pd.pc 474 (0 until PredictWidth).foreach(i => fetchPacketWire.pnpc(i) := if4_pd.pc(i) + Mux(if4_pd.pd(i).isRVC, 2.U, 4.U)) 475 when (if4_bp.taken) { 476 fetchPacketWire.pnpc(if4_bp.jmpIdx) := if4_bp.target 477 } 478 fetchPacketWire.bpuMeta := bpu.io.bpuMeta 479 (0 until PredictWidth).foreach(i => fetchPacketWire.bpuMeta(i).hist := final_gh) 480 (0 until PredictWidth).foreach(i => fetchPacketWire.bpuMeta(i).predHist := if4_predHist.asTypeOf(new GlobalHistory)) 481 fetchPacketWire.pd := if4_pd.pd 482 fetchPacketWire.ipf := if4_ipf 483 fetchPacketWire.acf := if4_acf 484 fetchPacketWire.crossPageIPFFix := if4_crossPageIPF 485 486 // predTaken Vec 487 fetchPacketWire.predTaken := if4_bp.taken 488 489 loopBuffer.io.in.bits := fetchPacketWire 490 io.fetchPacket.bits := fetchPacketWire 491 io.fetchPacket.valid := fetchPacketValid 492 loopBuffer.io.in.valid := io.fetchPacket.fire 493 494 // debug info 495 if (IFUDebug) { 496 XSDebug(RegNext(reset.asBool) && !reset.asBool, "Reseting...\n") 497 XSDebug(io.icacheFlush(0).asBool, "Flush icache stage2...\n") 498 XSDebug(io.icacheFlush(1).asBool, "Flush icache stage3...\n") 499 XSDebug(io.redirect.valid, p"Redirect from backend! target=${Hexadecimal(io.redirect.bits)}\n") 500 501 XSDebug("[IF1] v=%d fire=%d flush=%d pc=%x mask=%b\n", if1_valid, if1_fire, if1_flush, if1_npc, mask(if1_npc)) 502 XSDebug("[IF2] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x snpc=%x\n", if2_valid, if2_ready, if2_fire, if2_redirect, if2_flush, if2_pc, if2_snpc) 503 XSDebug("[IF3] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x crossPageIPF=%d sawNTBrs=%d\n", if3_valid, if3_ready, if3_fire, if3_redirect, if3_flush, if3_pc, crossPageIPF, if3_bp.hasNotTakenBrs) 504 XSDebug("[IF4] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x crossPageIPF=%d sawNTBrs=%d\n", if4_valid, if4_ready, if4_fire, if4_redirect, if4_flush, if4_pc, if4_crossPageIPF, if4_bp.hasNotTakenBrs) 505 XSDebug("[IF1][icacheReq] v=%d r=%d addr=%x\n", io.icacheReq.valid, io.icacheReq.ready, io.icacheReq.bits.addr) 506 XSDebug("[IF1][ghr] hist=%b\n", if1_gh.asUInt) 507 XSDebug("[IF1][ghr] extHist=%b\n\n", if1_gh.asUInt) 508 509 XSDebug("[IF2][bp] taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n\n", if2_bp.taken, if2_bp.jmpIdx, if2_bp.hasNotTakenBrs, if2_bp.target, if2_bp.saveHalfRVI) 510 if2_gh.debug("if2") 511 512 XSDebug("[IF3][icacheResp] v=%d r=%d pc=%x mask=%b\n", io.icacheResp.valid, io.icacheResp.ready, io.icacheResp.bits.pc, io.icacheResp.bits.mask) 513 XSDebug("[IF3][bp] taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if3_bp.taken, if3_bp.jmpIdx, if3_bp.hasNotTakenBrs, if3_bp.target, if3_bp.saveHalfRVI) 514 XSDebug("[IF3][redirect]: v=%d, prevMet=%d, prevNMet=%d, predT=%d, predNT=%d\n", if3_redirect, if3_prevHalfMetRedirect, if3_prevHalfNotMetRedirect, if3_predTakenRedirect, if3_predNotTakenRedirect) 515 // XSDebug("[IF3][prevHalfInstr] v=%d redirect=%d fetchpc=%x idx=%d tgt=%x taken=%d instr=%x\n\n", 516 // prev_half_valid, prev_half_redirect, prev_half_fetchpc, prev_half_idx, prev_half_tgt, prev_half_taken, prev_half_instr) 517 XSDebug("[IF3][ prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x ipf=%d\n", 518 if3_prevHalfInstr.valid, if3_prevHalfInstr.taken, if3_prevHalfInstr.fetchpc, if3_prevHalfInstr.idx, if3_prevHalfInstr.pc, if3_prevHalfInstr.target, if3_prevHalfInstr.instr, if3_prevHalfInstr.ipf) 519 XSDebug("[IF3][if3_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x ipf=%d\n\n", 520 if3_prevHalfInstr.valid, if3_prevHalfInstr.taken, if3_prevHalfInstr.fetchpc, if3_prevHalfInstr.idx, if3_prevHalfInstr.pc, if3_prevHalfInstr.target, if3_prevHalfInstr.instr, if3_prevHalfInstr.ipf) 521 if3_gh.debug("if3") 522 523 XSDebug("[IF4][predecode] mask=%b\n", if4_pd.mask) 524 XSDebug("[IF4][snpc]: %x, realMask=%b\n", if4_snpc, if4_mask) 525 XSDebug("[IF4][bp] taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if4_bp.taken, if4_bp.jmpIdx, if4_bp.hasNotTakenBrs, if4_bp.target, if4_bp.saveHalfRVI) 526 XSDebug("[IF4][redirect]: v=%d, prevNotMet=%d, predT=%d, predNT=%d\n", if4_redirect, if4_prevHalfNextNotMet, if4_predTakenRedirect, if4_predNotTakenRedirect) 527 XSDebug(if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken, "[IF4] cfi is jal! instr=%x target=%x\n", if4_instrs(if4_bp.jmpIdx), if4_jal_tgts(if4_bp.jmpIdx)) 528 XSDebug("[IF4][if4_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x ipf=%d\n", 529 if4_prevHalfInstr.valid, if4_prevHalfInstr.taken, if4_prevHalfInstr.fetchpc, if4_prevHalfInstr.idx, if4_prevHalfInstr.pc, if4_prevHalfInstr.target, if4_prevHalfInstr.instr, if4_prevHalfInstr.ipf) 530 if4_gh.debug("if4") 531 XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] v=%d r=%d mask=%b ipf=%d acf=%d crossPageIPF=%d\n", 532 io.fetchPacket.valid, io.fetchPacket.ready, io.fetchPacket.bits.mask, io.fetchPacket.bits.ipf, io.fetchPacket.bits.acf, io.fetchPacket.bits.crossPageIPFFix) 533 for (i <- 0 until PredictWidth) { 534 XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] %b %x pc=%x pnpc=%x pd: rvc=%d brType=%b call=%d ret=%d\n", 535 io.fetchPacket.bits.mask(i), 536 io.fetchPacket.bits.instrs(i), 537 io.fetchPacket.bits.pc(i), 538 io.fetchPacket.bits.pnpc(i), 539 io.fetchPacket.bits.pd(i).isRVC, 540 io.fetchPacket.bits.pd(i).brType, 541 io.fetchPacket.bits.pd(i).isCall, 542 io.fetchPacket.bits.pd(i).isRet 543 ) 544 } 545 } 546}