1package xiangshan.frontend 2 3import chisel3._ 4import chisel3.util._ 5import device.RAMHelper 6import xiangshan._ 7import utils._ 8 9trait HasIFUConst { this: XSModule => 10 val resetVector = 0x80000000L//TODO: set reset vec 11 val groupAlign = log2Up(FetchWidth * 4 * 2) 12 def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W)) 13 // each 1 bit in mask stands for 2 Bytes 14 def mask(pc: UInt): UInt = (Fill(PredictWidth * 2, 1.U(1.W)) >> pc(groupAlign - 1, 1))(PredictWidth - 1, 0) 15 def snpc(pc: UInt): UInt = pc + (PopCount(mask(pc)) << 1) 16 17 val IFUDebug = false 18} 19 20class IFUIO extends XSBundle 21{ 22 val fetchPacket = DecoupledIO(new FetchPacket) 23 val redirect = Flipped(ValidIO(new Redirect)) 24 val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 25 val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 26 val icacheReq = DecoupledIO(new FakeIcacheReq) 27 val icacheResp = Flipped(DecoupledIO(new FakeIcacheResp)) 28 val icacheFlush = Output(UInt(2.W)) 29} 30 31 32class IFU extends XSModule with HasIFUConst 33{ 34 val io = IO(new IFUIO) 35 val bpu = BPU(EnableBPU) 36 val pd = Module(new PreDecode) 37 38 val if2_redirect, if3_redirect, if4_redirect = WireInit(false.B) 39 val if1_flush, if2_flush, if3_flush, if4_flush = WireInit(false.B) 40 41 if4_flush := io.redirect.valid 42 if3_flush := if4_flush || if4_redirect 43 if2_flush := if3_flush || if3_redirect 44 if1_flush := if2_flush || if2_redirect 45 46 //********************** IF1 ****************************// 47 val if1_valid = !reset.asBool 48 val if1_npc = WireInit(0.U(VAddrBits.W)) 49 val if2_ready = WireInit(false.B) 50 val if1_fire = if1_valid && (if2_ready || if1_flush) && io.icacheReq.ready 51 52 // val extHist = VecInit(Fill(ExtHistoryLength, RegInit(0.U(1.W)))) 53 val extHist = RegInit(VecInit(Seq.fill(ExtHistoryLength)(0.U(1.W)))) 54 val headPtr = RegInit(0.U(log2Up(ExtHistoryLength).W)) 55 val shiftPtr = WireInit(false.B) 56 val newPtr = Wire(UInt(log2Up(ExtHistoryLength).W)) 57 val ptr = Mux(shiftPtr, newPtr, headPtr) 58 when (shiftPtr) { headPtr := newPtr } 59 val hist = Wire(Vec(HistoryLength, UInt(1.W))) 60 for (i <- 0 until HistoryLength) { 61 hist(i) := extHist(ptr + i.U) 62 } 63 64 newPtr := headPtr 65 shiftPtr := false.B 66 67 //********************** IF2 ****************************// 68 val if2_valid = RegEnable(next = if1_valid, init = false.B, enable = if1_fire) 69 val if3_ready = WireInit(false.B) 70 val if2_fire = if2_valid && if3_ready && !if2_flush 71 val if2_pc = RegEnable(next = if1_npc, init = resetVector.U, enable = if1_fire) 72 val if2_snpc = snpc(if2_pc) 73 val if2_histPtr = RegEnable(ptr, if1_fire) 74 if2_ready := if2_fire || !if2_valid || if2_flush 75 when (if2_flush) { if2_valid := if1_fire } 76 .elsewhen (if1_fire) { if2_valid := if1_valid } 77 .elsewhen (if2_fire) { if2_valid := false.B } 78 79 when (RegNext(reset.asBool) && !reset.asBool) { 80 if1_npc := resetVector.U(VAddrBits.W) 81 }.elsewhen (if2_fire) { 82 if1_npc := if2_snpc 83 }.otherwise { 84 if1_npc := RegNext(if1_npc) 85 } 86 87 val if2_bp = bpu.io.out(0).bits 88 if2_redirect := if2_fire && bpu.io.out(0).valid && if2_bp.redirect// && !if2_bp.saveHalfRVI 89 when (if2_redirect) { 90 if1_npc := if2_bp.target 91 } 92 93 when (if2_fire && (if2_bp.takenOnBr || if2_bp.hasNotTakenBrs)) { 94 shiftPtr := true.B 95 newPtr := headPtr - 1.U 96 hist(0) := if2_bp.takenOnBr.asUInt 97 extHist(newPtr) := if2_bp.takenOnBr.asUInt 98 } 99 100 //********************** IF3 ****************************// 101 val if3_valid = RegEnable(next = if2_valid, init = false.B, enable = if2_fire) 102 val if4_ready = WireInit(false.B) 103 val if3_fire = if3_valid && if4_ready && io.icacheResp.valid && !if3_flush 104 val if3_pc = RegEnable(if2_pc, if2_fire) 105 val if3_histPtr = RegEnable(if2_histPtr, if2_fire) 106 if3_ready := if3_fire || !if3_valid || if3_flush 107 when (if3_flush) { if3_valid := false.B } 108 .elsewhen (if2_fire) { if3_valid := if2_valid } 109 .elsewhen (if3_fire) { if3_valid := false.B } 110 111 val if3_bp = bpu.io.out(1).bits 112 113 class PrevHalfInstr extends Bundle { 114 val valid = Bool() 115 val taken = Bool() 116 val fetchpc = UInt(VAddrBits.W) // only for debug 117 val idx = UInt(VAddrBits.W) // only for debug 118 val pc = UInt(VAddrBits.W) 119 val target = UInt(VAddrBits.W) 120 val instr = UInt(16.W) 121 val takenOnBr = Bool() 122 } 123 124 val if3_prevHalfInstr = RegInit(0.U.asTypeOf(new PrevHalfInstr)) 125 val if4_prevHalfInstr = Wire(new PrevHalfInstr) 126 when (if4_prevHalfInstr.valid) { 127 if3_prevHalfInstr := if4_prevHalfInstr 128 } 129 val prevHalfInstr = Mux(if4_prevHalfInstr.valid, if4_prevHalfInstr, if3_prevHalfInstr) 130 131 val if3_hasPrevHalfInstr = prevHalfInstr.valid && (prevHalfInstr.pc + 2.U) === if3_pc 132 if3_redirect := if3_fire && bpu.io.out(1).valid && (if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.redirect/* && !if3_bp.saveHalfRVI*/ ) 133 when (if3_redirect) { 134 if1_npc := Mux(if3_hasPrevHalfInstr && prevHalfInstr.taken, prevHalfInstr.target, if3_bp.target) 135 } 136 137 when (if3_fire && if3_redirect) { 138 shiftPtr := true.B 139 newPtr := Mux(if3_hasPrevHalfInstr && prevHalfInstr.takenOnBr || if3_bp.takenOnBr || if3_bp.hasNotTakenBrs, if3_histPtr - 1.U, if3_histPtr) 140 hist(0) := Mux(if3_hasPrevHalfInstr && prevHalfInstr.takenOnBr || if3_bp.takenOnBr || if3_bp.hasNotTakenBrs, 141 (if3_hasPrevHalfInstr && prevHalfInstr.takenOnBr || if3_bp.takenOnBr).asUInt, 142 extHist(if3_histPtr)) 143 extHist(newPtr) := Mux(if3_hasPrevHalfInstr && prevHalfInstr.takenOnBr || if3_bp.takenOnBr || if3_bp.hasNotTakenBrs, 144 (if3_hasPrevHalfInstr && prevHalfInstr.takenOnBr || if3_bp.takenOnBr).asUInt, 145 extHist(if3_histPtr)) 146 } 147 148 149 150 // val prev_half_valid = RegInit(false.B) 151 // val prev_half_redirect = RegInit(false.B) 152 // val prev_half_fetchpc = Reg(UInt(VAddrBits.W)) 153 // val prev_half_idx = Reg(UInt(log2Up(PredictWidth).W)) 154 // val prev_half_tgt = Reg(UInt(VAddrBits.W)) 155 // val prev_half_taken = RegInit(false.B) 156 // val prev_half_instr = Reg(UInt(16.W)) 157 // when (if3_flush) { 158 // prev_half_valid := false.B 159 // prev_half_redirect := false.B 160 // }.elsewhen (if3_fire && if3_bp.saveHalfRVI) { 161 // prev_half_valid := true.B 162 // prev_half_redirect := if3_bp.redirect && bpu.io.out(1).valid 163 // prev_half_fetchpc := if3_pc 164 // val idx = Mux(if3_bp.redirect && bpu.io.out(1).valid, if3_bp.jmpIdx, PopCount(mask(if3_pc)) - 1.U) 165 // prev_half_idx := idx 166 // prev_half_tgt := if3_bp.target 167 // prev_half_taken := if3_bp.taken 168 // prev_half_instr := pd.io.out.instrs(idx)(15, 0) 169 // }.elsewhen (if3_fire) { 170 // prev_half_valid := false.B 171 // prev_half_redirect := false.B 172 // } 173 174 // when (bpu.io.out(1).valid && if3_fire) { 175 // when (prev_half_valid && prev_half_taken) { 176 // if3_redirect := true.B 177 // if1_npc := prev_half_tgt 178 // shiftPtr := true.B 179 // newPtr := if3_histPtr - 1.U 180 // hist(0) := 1.U 181 // extHist(newPtr) := 1.U 182 // }.elsewhen (if3_bp.redirect && !if3_bp.saveHalfRVI) { 183 // if3_redirect := true.B 184 // if1_npc := if3_bp.target 185 // shiftPtr := true.B 186 // newPtr := Mux(if3_bp.taken || if3_bp.hasNotTakenBrs, if3_histPtr - 1.U, if3_histPtr) 187 // hist(0) := Mux(if3_bp.taken || if3_bp.hasNotTakenBrs, if3_bp.taken.asUInt, extHist(if3_histPtr)) 188 // extHist(newPtr) := Mux(if3_bp.taken || if3_bp.hasNotTakenBrs, if3_bp.taken.asUInt, extHist(if3_histPtr)) 189 // }.elsewhen (if3_bp.saveHalfRVI) { 190 // if3_redirect := true.B 191 // if1_npc := snpc(if3_pc) 192 // shiftPtr := true.B 193 // newPtr := Mux(if3_bp.hasNotTakenBrs, if3_histPtr - 1.U, if3_histPtr) 194 // hist(0) := Mux(if3_bp.hasNotTakenBrs, 0.U, extHist(if3_histPtr)) 195 // extHist(newPtr) := Mux(if3_bp.hasNotTakenBrs, 0.U, extHist(if3_histPtr)) 196 // }.otherwise { 197 // if3_redirect := false.B 198 // } 199 // }.otherwise { 200 // if3_redirect := false.B 201 // } 202 203 204 //********************** IF4 ****************************// 205 val if4_pd = RegEnable(pd.io.out, if3_fire) 206 val if4_valid = RegInit(false.B) 207 val if4_fire = if4_valid && io.fetchPacket.ready 208 val if4_pc = RegEnable(if3_pc, if3_fire) 209 val if4_histPtr = RegEnable(if3_histPtr, if3_fire) 210 if4_ready := (if4_fire || !if4_valid || if4_flush) && GTimer() > 500.U 211 when (if4_flush) { if4_valid := false.B } 212 .elsewhen (if3_fire) { if4_valid := if3_valid } 213 .elsewhen(if4_fire) { if4_valid := false.B } 214 215 val if4_bp = Wire(new BranchPrediction) 216 if4_bp := bpu.io.out(2).bits 217 218 val if4_cfi_jal = if4_pd.instrs(if4_bp.jmpIdx) 219 val if4_cfi_jal_tgt = if4_pd.pc(if4_bp.jmpIdx) + Mux(if4_pd.pd(if4_bp.jmpIdx).isRVC, 220 SignExt(Cat(if4_cfi_jal(12), if4_cfi_jal(8), if4_cfi_jal(10, 9), if4_cfi_jal(6), if4_cfi_jal(7), if4_cfi_jal(2), if4_cfi_jal(11), if4_cfi_jal(5, 3), 0.U(1.W)), XLEN), 221 SignExt(Cat(if4_cfi_jal(31), if4_cfi_jal(19, 12), if4_cfi_jal(20), if4_cfi_jal(30, 21), 0.U(1.W)), XLEN)) 222 if4_bp.target := Mux(if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken, if4_cfi_jal_tgt, bpu.io.out(2).bits.target) 223 if4_bp.redirect := bpu.io.out(2).bits.redirect || if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken && if4_cfi_jal_tgt =/= bpu.io.out(2).bits.target 224 225 if4_prevHalfInstr := 0.U.asTypeOf(new PrevHalfInstr) 226 when (bpu.io.out(2).valid && if4_fire && if4_bp.saveHalfRVI) { 227 if4_prevHalfInstr.valid := true.B 228 if4_prevHalfInstr.taken := if4_bp.taken 229 if4_prevHalfInstr.takenOnBr := if4_bp.takenOnBr 230 if4_prevHalfInstr.fetchpc := if4_pc 231 if4_prevHalfInstr.idx := PopCount(mask(if4_pc)) - 1.U 232 if4_prevHalfInstr.pc := if4_pd.pc(if4_prevHalfInstr.idx) 233 if4_prevHalfInstr.target := if4_bp.target 234 if4_prevHalfInstr.instr := if4_pd.instrs(if4_prevHalfInstr.idx)(15, 0) 235 } 236 237 when (bpu.io.out(2).valid && if4_fire && if4_bp.redirect) { 238 if4_redirect := true.B 239 shiftPtr := true.B 240 newPtr := Mux(if4_bp.takenOnBr || if4_bp.hasNotTakenBrs, if4_histPtr - 1.U, if4_histPtr) 241 hist(0) := Mux(if4_bp.takenOnBr || if4_bp.hasNotTakenBrs, if4_bp.takenOnBr.asUInt, extHist(if4_histPtr)) 242 extHist(newPtr) := Mux(if4_bp.takenOnBr || if4_bp.hasNotTakenBrs, if4_bp.takenOnBr.asUInt, extHist(if4_histPtr)) 243 when (if4_bp.saveHalfRVI) { 244 if1_npc := snpc(if4_pc) 245 }.otherwise { 246 if1_npc := if4_bp.target 247 } 248 }.elsewhen (bpu.io.out(2).valid && if4_fire/* && !if4_bp.redirect*/) { 249 when (if4_bp.saveHalfRVI && if4_bp.takenOnBr) { 250 if4_redirect := true.B 251 if1_npc := snpc(if4_pc) 252 shiftPtr := true.B 253 newPtr := if4_histPtr - 1.U 254 hist(0) := 1.U 255 extHist(newPtr) := 1.U 256 }.elsewhen (if4_bp.saveHalfRVI && if4_bp.taken) { 257 if4_redirect := true.B 258 if1_npc := snpc(if4_pc) 259 shiftPtr := true.B 260 newPtr := if4_histPtr 261 hist(0) := extHist(if4_histPtr) 262 extHist(newPtr) := extHist(if4_histPtr) 263 }.otherwise { 264 if4_redirect := false.B 265 } 266 }.otherwise { 267 if4_redirect := false.B 268 } 269 270 271 272 // when (bpu.io.out(2).valid && if4_fire && if4_bp.redirect) { 273 // when (!if4_bp.saveHalfRVI) { 274 // if4_redirect := true.B 275 // // if1_npc := if4_bp.target 276 // if1_npc := Mux(if4_bp.taken, if4_bp.target, snpc(if4_pc)) 277 278 // shiftPtr := true.B 279 // newPtr := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_histPtr - 1.U, if4_histPtr) 280 // hist(0) := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_bp.taken.asUInt, extHist(if4_histPtr)) 281 // extHist(newPtr) := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_bp.taken.asUInt, extHist(if4_histPtr)) 282 283 // }.otherwise { 284 // if4_redirect := true.B 285 // if1_npc := snpc(if4_pc) 286 287 // prev_half_valid := true.B 288 // prev_half_redirect := true.B 289 // prev_half_fetchpc := if4_pc 290 // val idx = PopCount(mask(if4_pc)) - 1.U 291 // prev_half_idx := idx 292 // prev_half_tgt := if4_bp.target 293 // prev_half_taken := if4_bp.taken 294 // prev_half_instr := if4_pd.instrs(idx)(15, 0) 295 296 // shiftPtr := true.B 297 // newPtr := Mux(if4_bp.hasNotTakenBrs, if4_histPtr - 1.U, if4_histPtr) 298 // hist(0) := Mux(if4_bp.hasNotTakenBrs, 0.U, extHist(if4_histPtr)) 299 // extHist(newPtr) := Mux(if4_bp.hasNotTakenBrs, 0.U, extHist(if4_histPtr)) 300 // } 301 // }.otherwise { 302 // if4_redirect := false.B 303 // } 304 305 when (io.outOfOrderBrInfo.valid && io.outOfOrderBrInfo.bits.isMisPred) { 306 val b = io.outOfOrderBrInfo.bits 307 val oldPtr = b.brInfo.histPtr 308 shiftPtr := true.B 309 when (!b.pd.isBr && !b.brInfo.sawNotTakenBranch) { 310 // If mispredicted cfi is not a branch, 311 // and there wasn't any not taken branch before it, 312 // we should only recover the pointer to an unshifted state 313 newPtr := oldPtr 314 }.otherwise { 315 newPtr := oldPtr - 1.U 316 hist(0) := b.taken 317 extHist(newPtr) := b.taken 318 } 319 } 320 321 when (io.redirect.valid) { 322 if1_npc := io.redirect.bits.target 323 } 324 325 io.icacheReq.valid := if1_valid && if2_ready 326 io.icacheReq.bits.addr := if1_npc 327 io.icacheResp.ready := if3_ready 328 io.icacheFlush := Cat(if3_flush, if2_flush) 329 330 val inOrderBrHist = Wire(Vec(HistoryLength, UInt(1.W))) 331 (0 until HistoryLength).foreach(i => inOrderBrHist(i) := extHist(i.U + io.inOrderBrInfo.bits.brInfo.histPtr)) 332 bpu.io.inOrderBrInfo.valid := io.inOrderBrInfo.valid 333 bpu.io.inOrderBrInfo.bits := BranchUpdateInfoWithHist(io.inOrderBrInfo.bits, inOrderBrHist.asUInt) 334 bpu.io.outOfOrderBrInfo.valid := io.outOfOrderBrInfo.valid 335 bpu.io.outOfOrderBrInfo.bits := BranchUpdateInfoWithHist(io.outOfOrderBrInfo.bits, inOrderBrHist.asUInt) // Dont care about hist 336 337 // bpu.io.flush := Cat(if4_flush, if3_flush, if2_flush) 338 bpu.io.flush := VecInit(if2_flush, if3_flush, if4_flush) 339 bpu.io.in.valid := if1_fire 340 bpu.io.in.bits.pc := if1_npc 341 bpu.io.in.bits.hist := hist.asUInt 342 bpu.io.in.bits.inMask := mask(if1_npc) 343 bpu.io.out(0).ready := if2_fire 344 bpu.io.out(1).ready := if3_fire 345 bpu.io.out(2).ready := if4_fire 346 bpu.io.predecode.valid := if4_valid 347 bpu.io.predecode.bits.mask := if4_pd.mask 348 bpu.io.predecode.bits.pd := if4_pd.pd 349 bpu.io.predecode.bits.isFetchpcEqualFirstpc := if4_pc === if4_pd.pc(0) 350 bpu.io.branchInfo.ready := if4_fire 351 352 pd.io.in := io.icacheResp.bits 353 pd.io.prev.valid := if3_hasPrevHalfInstr 354 pd.io.prev.bits := prevHalfInstr.instr 355 356 io.fetchPacket.valid := if4_valid && !io.redirect.valid 357 io.fetchPacket.bits.instrs := if4_pd.instrs 358 io.fetchPacket.bits.mask := if4_pd.mask & (Fill(PredictWidth, !if4_bp.taken) | (Fill(PredictWidth, 1.U(1.W)) >> (~if4_bp.jmpIdx))) 359 io.fetchPacket.bits.pc := if4_pd.pc 360 (0 until PredictWidth).foreach(i => io.fetchPacket.bits.pnpc(i) := if4_pd.pc(i) + Mux(if4_pd.pd(i).isRVC, 2.U, 4.U)) 361 when (if4_bp.taken) { 362 io.fetchPacket.bits.pnpc(if4_bp.jmpIdx) := if4_bp.target 363 } 364 io.fetchPacket.bits.brInfo := bpu.io.branchInfo.bits 365 (0 until PredictWidth).foreach(i => io.fetchPacket.bits.brInfo(i).histPtr := if4_histPtr) 366 io.fetchPacket.bits.pd := if4_pd.pd 367 368 // debug info 369 if (IFUDebug) { 370 XSDebug(RegNext(reset.asBool) && !reset.asBool, "Reseting...\n") 371 XSDebug(io.icacheFlush(0).asBool, "Flush icache stage2...\n") 372 XSDebug(io.icacheFlush(1).asBool, "Flush icache stage3...\n") 373 XSDebug(io.redirect.valid, "Redirect from backend! isExcp=%d isMisPred=%d isReplay=%d pc=%x\n", 374 io.redirect.bits.isException, io.redirect.bits.isMisPred, io.redirect.bits.isReplay, io.redirect.bits.pc) 375 XSDebug(io.redirect.valid, p"Redirect from backend! target=${Hexadecimal(io.redirect.bits.target)} brTag=${io.redirect.bits.brTag}\n") 376 377 XSDebug("[IF1] v=%d fire=%d flush=%d pc=%x ptr=%d mask=%b\n", if1_valid, if1_fire, if1_flush, if1_npc, ptr, mask(if1_npc)) 378 XSDebug("[IF2] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d snpc=%x\n", if2_valid, if2_ready, if2_fire, if2_redirect, if2_flush, if2_pc, if2_histPtr, if2_snpc) 379 XSDebug("[IF3] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d\n", if3_valid, if3_ready, if3_fire, if3_redirect, if3_flush, if3_pc, if3_histPtr) 380 XSDebug("[IF4] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d\n", if4_valid, if4_ready, if4_fire, if4_redirect, if4_flush, if4_pc, if4_histPtr) 381 382 XSDebug("[IF1][icacheReq] v=%d r=%d addr=%x\n", io.icacheReq.valid, io.icacheReq.ready, io.icacheReq.bits.addr) 383 XSDebug("[IF1][ghr] headPtr=%d shiftPtr=%d newPtr=%d ptr=%d\n", headPtr, shiftPtr, newPtr, ptr) 384 XSDebug("[IF1][ghr] hist=%b\n", hist.asUInt) 385 XSDebug("[IF1][ghr] extHist=%b\n\n", extHist.asUInt) 386 387 XSDebug("[IF2][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n\n", if2_bp.redirect, if2_bp.taken, if2_bp.jmpIdx, if2_bp.hasNotTakenBrs, if2_bp.target, if2_bp.saveHalfRVI) 388 389 XSDebug("[IF3][icacheResp] v=%d r=%d pc=%x mask=%b\n", io.icacheResp.valid, io.icacheResp.ready, io.icacheResp.bits.pc, io.icacheResp.bits.mask) 390 XSDebug("[IF3][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if3_bp.redirect, if3_bp.taken, if3_bp.jmpIdx, if3_bp.hasNotTakenBrs, if3_bp.target, if3_bp.saveHalfRVI) 391 // XSDebug("[IF3][prevHalfInstr] v=%d redirect=%d fetchpc=%x idx=%d tgt=%x taken=%d instr=%x\n\n", 392 // prev_half_valid, prev_half_redirect, prev_half_fetchpc, prev_half_idx, prev_half_tgt, prev_half_taken, prev_half_instr) 393 XSDebug("[IF3][ prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x\n", 394 prevHalfInstr.valid, prevHalfInstr.taken, prevHalfInstr.fetchpc, prevHalfInstr.idx, prevHalfInstr.pc, prevHalfInstr.target, prevHalfInstr.instr) 395 XSDebug("[IF3][if3_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x\n\n", 396 if3_prevHalfInstr.valid, if3_prevHalfInstr.taken, if3_prevHalfInstr.fetchpc, if3_prevHalfInstr.idx, if3_prevHalfInstr.pc, if3_prevHalfInstr.target, if3_prevHalfInstr.instr) 397 398 399 XSDebug("[IF4][predecode] mask=%b\n", if4_pd.mask) 400 XSDebug("[IF4][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if4_bp.redirect, if4_bp.taken, if4_bp.jmpIdx, if4_bp.hasNotTakenBrs, if4_bp.target, if4_bp.saveHalfRVI) 401 XSDebug(if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken, "[IF4] cfi is jal! instr=%x target=%x\n", if4_cfi_jal, if4_cfi_jal_tgt) 402 XSDebug("[IF4][if4_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x\n", 403 if4_prevHalfInstr.valid, if4_prevHalfInstr.taken, if4_prevHalfInstr.fetchpc, if4_prevHalfInstr.idx, if4_prevHalfInstr.pc, if4_prevHalfInstr.target, if4_prevHalfInstr.instr) 404 XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] v=%d r=%d mask=%b\n", io.fetchPacket.valid, io.fetchPacket.ready, io.fetchPacket.bits.mask) 405 for (i <- 0 until PredictWidth) { 406 XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] %b %x pc=%x pnpc=%x pd: rvc=%d brType=%b call=%d ret=%d\n", 407 io.fetchPacket.bits.mask(i), 408 io.fetchPacket.bits.instrs(i), 409 io.fetchPacket.bits.pc(i), 410 io.fetchPacket.bits.pnpc(i), 411 io.fetchPacket.bits.pd(i).isRVC, 412 io.fetchPacket.bits.pd(i).brType, 413 io.fetchPacket.bits.pd(i).isCall, 414 io.fetchPacket.bits.pd(i).isRet 415 ) 416 } 417 } 418}