xref: /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala (revision 866dacaf1f52cde4ee0da6ca348714e85fc6e238) 
1package xiangshan.frontend
2
3import chisel3._
4import chisel3.util._
5import device.RAMHelper
6import xiangshan._
7import xiangshan.utils._
8
9trait HasIFUConst { this: XSModule =>
10  val resetVector = 0x80000000L//TODO: set reset vec
11
12  val groupAlign = log2Up(FetchWidth * 4)
13  def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W))
14
15}
16
17class IFUIO extends XSBundle
18{
19    val fetchPacket = DecoupledIO(new FetchPacket)
20    val redirectInfo = Input(new RedirectInfo)
21    val icacheReq = DecoupledIO(new FakeIcacheReq)
22    val icacheResp = Flipped(DecoupledIO(new FakeIcacheResp))
23}
24
25class FakeBPU extends XSModule{
26  val io = IO(new Bundle() {
27    val in = new Bundle { val pc = Flipped(Valid(UInt(VAddrBits.W))) }
28    val btbOut = ValidIO(new BranchPrediction)
29    val tageOut = ValidIO(new BranchPrediction)
30    val predecode = Flipped(ValidIO(new Predecode))
31  })
32
33  io.btbOut.valid := false.B
34  io.btbOut.bits <> DontCare
35  io.tageOut.valid := false.B
36  io.tageOut.bits <> DontCare
37}
38
39
40
41class IFU extends XSModule with HasIFUConst
42{
43    val io = IO(new IFUIO)
44    //val bpu = Module(new BPU)
45    val bpu = Module(new FakeBPU)
46
47    //-------------------------
48    //      IF1  PC update
49    //-------------------------
50    //local
51    val if1_npc = WireInit(0.U(VAddrBits.W))
52    val if1_valid = !reset.asBool //TODO:this is ugly
53    val if1_pc = RegInit(resetVector.U(VAddrBits.W))
54    //next
55    val if2_ready = WireInit(false.B)
56    val if2_snpc = Cat(if1_pc(VAddrBits-1, groupAlign) + 1.U, 0.U(groupAlign.W))
57    val if1_ready = if2_ready
58
59    //pipe fire
60    val if1_fire = if1_valid && if1_ready
61    val if1_pcUpdate = io.redirectInfo.flush() || if1_fire
62
63    when(RegNext(reset.asBool) && !reset.asBool){
64    //when((GTimer() === 501.U)){ //TODO:this is ugly
65      XSDebug("RESET....\n")
66      if1_npc := resetVector.U(VAddrBits.W)
67    } .otherwise{
68      if1_npc := if2_snpc
69    }
70
71    when(if1_pcUpdate)
72    {
73      if1_pc := if1_npc
74    }
75
76    bpu.io.in.pc.valid := if1_valid
77    bpu.io.in.pc.bits := if1_npc
78
79    XSDebug("[IF1]if1_valid:%d  ||  if1_npc:0x%x  || if1_pcUpdate:%d if1_pc:0x%x  || if2_ready:%d",if1_valid,if1_npc,if1_pcUpdate,if1_pc,if2_ready)
80    XSDebug(false,if1_fire,"------IF1->fire!!!")
81    XSDebug(false,true.B,"\n")
82
83    //-------------------------
84    //      IF2  btb resonse
85    //           icache visit
86    //-------------------------
87    //local
88    val if2_valid = RegEnable(next=if1_valid,init=false.B,enable=if1_fire)
89    val if2_pc = if1_pc
90    val if2_btb_taken = bpu.io.btbOut.valid
91    val if2_btb_insMask = bpu.io.btbOut.bits.instrValid
92    val if2_btb_target = bpu.io.btbOut.bits.target
93
94    //next
95    val if3_ready = WireInit(false.B)
96
97    //pipe fire
98    val if2_fire = if2_valid && if3_ready && io.icacheReq.fire()
99    if2_ready := (if2_fire) || !if2_valid
100
101    io.icacheReq.valid := if2_valid
102    io.icacheReq.bits.addr := groupPC(if2_pc)
103    io.icacheReq.bits.flush := io.redirectInfo.flush()
104
105    when(if2_valid && if2_btb_taken)
106    {
107      if1_npc := if2_btb_target
108    }
109
110    XSDebug("[IF2]if2_valid:%d  ||  if2_pc:0x%x   || if3_ready:%d                                        ",if2_valid,if2_pc,if3_ready)
111    //XSDebug("[IF2-BPU-out]if2_btbTaken:%d || if2_btb_insMask:%b || if2_btb_target:0x%x \n",if2_btb_taken,if2_btb_insMask.asUInt,if2_btb_target)
112    XSDebug(false,if2_fire,"------IF2->fire!!!")
113    XSDebug(false,true.B,"\n")
114    XSDebug("[IF2-Icache-Req] icache_in_valid:%d  icache_in_ready:%d\n",io.icacheReq.valid,io.icacheReq.ready)
115
116    //-------------------------
117    //      IF3  icache hit check
118    //-------------------------
119    //local
120    val if3_valid = RegEnable(next=if2_valid,init=false.B,enable=if2_fire)
121    val if3_pc = RegEnable(if2_pc,if2_fire)
122    val if3_npc = RegEnable(if1_npc,if2_fire)
123    val if3_btb_target = RegEnable(if2_btb_target,if2_fire)
124    val if3_btb_taken = RegEnable(if2_btb_taken,if2_fire)
125
126    //next
127    val if4_ready = WireInit(false.B)
128
129    //pipe fire
130    val if3_fire = if3_valid && if4_ready
131    if3_ready := if3_fire  || !if3_valid
132
133
134    XSDebug("[IF3]if3_valid:%d  ||  if3_pc:0x%x   if3_npc:0x%x || if4_ready:%d                    ",if3_valid,if3_pc,if3_npc,if4_ready)
135    XSDebug(false,if3_fire,"------IF3->fire!!!")
136    XSDebug(false,true.B,"\n")
137
138    //-------------------------
139    //      IF4  icache resonse
140    //           RAS result
141    //           taget generate
142    //-------------------------
143    val if4_valid = RegEnable(next=if3_valid,init=false.B,enable=if3_fire)
144    val if4_pc = RegEnable(if3_pc,if3_fire)
145    val if4_npc = RegEnable(if3_npc,if3_fire)
146    val if4_btb_target = RegEnable(if3_btb_target,if3_fire)
147    val if4_btb_taken = RegEnable(if3_btb_taken,if3_fire)
148    val if4_tage_target = bpu.io.tageOut.bits.target
149    val if4_tage_taken = bpu.io.tageOut.valid
150    val if4_tage_insMask = bpu.io.tageOut.bits.instrValid
151    XSDebug("[IF4]if4_valid:%d  ||  if4_pc:0x%x   if4_npc:0x%x\n",if4_valid,if4_pc,if4_npc)
152    //XSDebug("[IF4-TAGE-out]if4_tage_taken:%d || if4_btb_insMask:%b || if4_tage_target:0x%x \n",if4_tage_taken,if4_tage_insMask.asUInt,if4_tage_target)
153    XSDebug("[IF4-ICACHE-RESP]icacheResp.valid:%d   icacheResp.ready:%d\n",io.icacheResp.valid,io.icacheResp.ready)
154
155    when(if4_valid && io.icacheResp.fire() && if4_tage_taken)
156    {
157      if1_npc := if4_tage_target
158    }
159
160
161    //redirect: miss predict
162    when(io.redirectInfo.flush()){
163      if1_npc := io.redirectInfo.redirect.target
164      if3_valid := false.B
165      if4_valid := false.B
166    }
167    XSDebug(io.redirectInfo.flush(),"[IFU-REDIRECT] target:0x%x  \n",io.redirectInfo.redirect.target.asUInt)
168
169    //Output -> iBuffer
170    //io.fetchPacket <> DontCare
171    if4_ready := io.fetchPacket.ready && (io.icacheResp.valid || !if4_valid) //&& (GTimer() > 500.U)
172    io.fetchPacket.valid := if4_valid && !io.redirectInfo.flush()
173    io.fetchPacket.bits.instrs := io.icacheResp.bits.icacheOut
174    io.fetchPacket.bits.mask := Fill(FetchWidth*2, 1.U(1.W)) << if4_pc(2+log2Up(FetchWidth)-1, 1)
175    io.fetchPacket.bits.pc := if4_pc
176
177    XSDebug(io.fetchPacket.fire,"[IFU-Out-FetchPacket] starPC:0x%x   GroupPC:0x%xn\n",if4_pc.asUInt,groupPC(if4_pc).asUInt)
178    XSDebug(io.fetchPacket.fire,"[IFU-Out-FetchPacket] instrmask %b\n",io.fetchPacket.bits.mask.asUInt)
179    for(i <- 0 until FetchWidth){
180      io.fetchPacket.bits.pnpc(i) := if1_npc
181      XSDebug(io.fetchPacket.fire,"[IFU-Out-FetchPacket] instruction %x    pnpc:0x%x\n",io.fetchPacket.bits.instrs(i).asUInt,if1_npc.asUInt)
182    }
183
184    //to BPU
185    bpu.io.predecode.valid := io.icacheResp.fire() && if4_valid
186    bpu.io.predecode.bits <> io.icacheResp.bits.predecode
187    bpu.io.predecode.bits.mask := Fill(FetchWidth, 1.U(1.W)) << if4_pc(2+log2Up(FetchWidth)-1, 2) //TODO: consider RVC
188
189    io.icacheResp.ready := io.fetchPacket.ready //&& (GTimer() > 500.U)
190
191}
192
193