1package xiangshan.frontend 2 3import chisel3._ 4import chisel3.util._ 5import device.RAMHelper 6import xiangshan._ 7import utils._ 8import xiangshan.cache._ 9 10trait HasIFUConst { this: XSModule => 11 val resetVector = 0x80000000L//TODO: set reset vec 12 val groupAlign = log2Up(FetchWidth * 4 * 2) 13 def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W)) 14 // each 1 bit in mask stands for 2 Bytes 15 def mask(pc: UInt): UInt = (Fill(PredictWidth * 2, 1.U(1.W)) >> pc(groupAlign - 1, 1))(PredictWidth - 1, 0) 16 def snpc(pc: UInt): UInt = pc + (PopCount(mask(pc)) << 1) 17} 18 19class IFUIO extends XSBundle 20{ 21 val fetchPacket = DecoupledIO(new FetchPacket) 22 val redirect = Flipped(ValidIO(new Redirect)) 23 val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 24 val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 25 val icacheReq = DecoupledIO(new ICacheReq) 26 val icacheResp = Flipped(DecoupledIO(new ICacheResp)) 27 val icacheFlush = Output(UInt(2.W)) 28} 29 30 31class IFU extends XSModule with HasIFUConst 32{ 33 val io = IO(new IFUIO) 34 val bpu = BPU(EnableBPU) 35 val pd = Module(new PreDecode) 36 37 val if2_redirect, if3_redirect, if4_redirect = WireInit(false.B) 38 val if1_flush, if2_flush, if3_flush, if4_flush = WireInit(false.B) 39 40 if4_flush := io.redirect.valid 41 if3_flush := if4_flush || if4_redirect 42 if2_flush := if3_flush || if3_redirect 43 if1_flush := if2_flush || if2_redirect 44 45 //********************** IF1 ****************************// 46 val if1_valid = !reset.asBool && GTimer() > 500.U 47 val if1_npc = WireInit(0.U(VAddrBits.W)) 48 val if2_ready = WireInit(false.B) 49 val if1_fire = if1_valid && (if2_ready || if1_flush) && io.icacheReq.ready 50 51 // val extHist = VecInit(Fill(ExtHistoryLength, RegInit(0.U(1.W)))) 52 val extHist = RegInit(VecInit(Seq.fill(ExtHistoryLength)(0.U(1.W)))) 53 val headPtr = RegInit(0.U(log2Up(ExtHistoryLength).W)) 54 val shiftPtr = WireInit(false.B) 55 val newPtr = Wire(UInt(log2Up(ExtHistoryLength).W)) 56 val ptr = Mux(shiftPtr, newPtr, headPtr) 57 when (shiftPtr) { headPtr := newPtr } 58 val hist = Wire(Vec(HistoryLength, UInt(1.W))) 59 for (i <- 0 until HistoryLength) { 60 hist(i) := extHist(ptr + i.U) 61 } 62 63 newPtr := headPtr 64 shiftPtr := false.B 65 66 //********************** IF2 ****************************// 67 val if2_valid = RegEnable(next = if1_valid, init = false.B, enable = if1_fire) 68 val if3_ready = WireInit(false.B) 69 val if2_fire = if2_valid && if3_ready && !if2_flush 70 val if2_pc = RegEnable(next = if1_npc, init = resetVector.U, enable = if1_fire) 71 val if2_snpc = snpc(if2_pc) 72 val if2_histPtr = RegEnable(ptr, if1_fire) 73 if2_ready := if2_fire || !if2_valid || if2_flush 74 when (if2_flush) { if2_valid := if1_fire } 75 .elsewhen (if1_fire) { if2_valid := if1_valid } 76 .elsewhen (if2_fire) { if2_valid := false.B } 77 78 when (RegNext(reset.asBool) && !reset.asBool) { 79 if1_npc := resetVector.U(VAddrBits.W) 80 }.elsewhen (if2_fire) { 81 if1_npc := if2_snpc 82 }.otherwise { 83 if1_npc := RegNext(if1_npc) 84 } 85 86 val if2_bp = bpu.io.out(0).bits 87 if2_redirect := if2_fire && bpu.io.out(0).valid && if2_bp.redirect// && !if2_bp.saveHalfRVI 88 when (if2_redirect) { 89 if1_npc := if2_bp.target 90 } 91 92 when (if2_fire && (if2_bp.taken || if2_bp.hasNotTakenBrs)) { 93 shiftPtr := true.B 94 newPtr := headPtr - 1.U 95 hist(0) := if2_bp.taken.asUInt 96 extHist(newPtr) := if2_bp.taken.asUInt 97 } 98 99 //********************** IF3 ****************************// 100 val if3_valid = RegEnable(next = if2_valid, init = false.B, enable = if2_fire) 101 val if4_ready = WireInit(false.B) 102 val if3_fire = if3_valid && if4_ready && io.icacheResp.valid && !if3_flush 103 val if3_pc = RegEnable(if2_pc, if2_fire) 104 val if3_histPtr = RegEnable(if2_histPtr, if2_fire) 105 if3_ready := if3_fire || !if3_valid || if3_flush 106 when (if3_flush) { if3_valid := false.B } 107 .elsewhen (if2_fire) { if3_valid := if2_valid } 108 .elsewhen (if3_fire) { if3_valid := false.B } 109 110 val if3_bp = bpu.io.out(1).bits 111 112 class PrevHalfInstr extends Bundle { 113 val valid = Bool() 114 val taken = Bool() 115 val fetchpc = UInt(VAddrBits.W) // only for debug 116 val idx = UInt(VAddrBits.W) // only for debug 117 val pc = UInt(VAddrBits.W) 118 val target = UInt(VAddrBits.W) 119 val instr = UInt(16.W) 120 } 121 122 val if3_prevHalfInstr = RegInit(0.U.asTypeOf(new PrevHalfInstr)) 123 val if4_prevHalfInstr = Wire(new PrevHalfInstr) 124 when (if4_prevHalfInstr.valid) { 125 if3_prevHalfInstr := if4_prevHalfInstr 126 } 127 val prevHalfInstr = Mux(if4_prevHalfInstr.valid, if4_prevHalfInstr, if3_prevHalfInstr) 128 129 val if3_hasPrevHalfInstr = prevHalfInstr.valid && (prevHalfInstr.pc + 2.U) === if3_pc 130 if3_redirect := if3_fire && bpu.io.out(1).valid && (if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.redirect/* && !if3_bp.saveHalfRVI*/ ) 131 when (if3_redirect) { 132 if1_npc := Mux(if3_hasPrevHalfInstr && prevHalfInstr.taken, prevHalfInstr.target, if3_bp.target) 133 } 134 135 when (if3_fire && if3_redirect) { 136 shiftPtr := true.B 137 newPtr := Mux(if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.taken || if3_bp.hasNotTakenBrs, if3_histPtr - 1.U, if3_histPtr) 138 hist(0) := Mux(if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.taken || if3_bp.hasNotTakenBrs, 139 (if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.taken).asUInt, 140 extHist(if3_histPtr)) 141 extHist(newPtr) := Mux(if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.taken || if3_bp.hasNotTakenBrs, 142 (if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.taken).asUInt, 143 extHist(if3_histPtr)) 144 } 145 146 147 148 // val prev_half_valid = RegInit(false.B) 149 // val prev_half_redirect = RegInit(false.B) 150 // val prev_half_fetchpc = Reg(UInt(VAddrBits.W)) 151 // val prev_half_idx = Reg(UInt(log2Up(PredictWidth).W)) 152 // val prev_half_tgt = Reg(UInt(VAddrBits.W)) 153 // val prev_half_taken = RegInit(false.B) 154 // val prev_half_instr = Reg(UInt(16.W)) 155 // when (if3_flush) { 156 // prev_half_valid := false.B 157 // prev_half_redirect := false.B 158 // }.elsewhen (if3_fire && if3_bp.saveHalfRVI) { 159 // prev_half_valid := true.B 160 // prev_half_redirect := if3_bp.redirect && bpu.io.out(1).valid 161 // prev_half_fetchpc := if3_pc 162 // val idx = Mux(if3_bp.redirect && bpu.io.out(1).valid, if3_bp.jmpIdx, PopCount(mask(if3_pc)) - 1.U) 163 // prev_half_idx := idx 164 // prev_half_tgt := if3_bp.target 165 // prev_half_taken := if3_bp.taken 166 // prev_half_instr := pd.io.out.instrs(idx)(15, 0) 167 // }.elsewhen (if3_fire) { 168 // prev_half_valid := false.B 169 // prev_half_redirect := false.B 170 // } 171 172 // when (bpu.io.out(1).valid && if3_fire) { 173 // when (prev_half_valid && prev_half_taken) { 174 // if3_redirect := true.B 175 // if1_npc := prev_half_tgt 176 // shiftPtr := true.B 177 // newPtr := if3_histPtr - 1.U 178 // hist(0) := 1.U 179 // extHist(newPtr) := 1.U 180 // }.elsewhen (if3_bp.redirect && !if3_bp.saveHalfRVI) { 181 // if3_redirect := true.B 182 // if1_npc := if3_bp.target 183 // shiftPtr := true.B 184 // newPtr := Mux(if3_bp.taken || if3_bp.hasNotTakenBrs, if3_histPtr - 1.U, if3_histPtr) 185 // hist(0) := Mux(if3_bp.taken || if3_bp.hasNotTakenBrs, if3_bp.taken.asUInt, extHist(if3_histPtr)) 186 // extHist(newPtr) := Mux(if3_bp.taken || if3_bp.hasNotTakenBrs, if3_bp.taken.asUInt, extHist(if3_histPtr)) 187 // }.elsewhen (if3_bp.saveHalfRVI) { 188 // if3_redirect := true.B 189 // if1_npc := snpc(if3_pc) 190 // shiftPtr := true.B 191 // newPtr := Mux(if3_bp.hasNotTakenBrs, if3_histPtr - 1.U, if3_histPtr) 192 // hist(0) := Mux(if3_bp.hasNotTakenBrs, 0.U, extHist(if3_histPtr)) 193 // extHist(newPtr) := Mux(if3_bp.hasNotTakenBrs, 0.U, extHist(if3_histPtr)) 194 // }.otherwise { 195 // if3_redirect := false.B 196 // } 197 // }.otherwise { 198 // if3_redirect := false.B 199 // } 200 201 202 //********************** IF4 ****************************// 203 val if4_pd = RegEnable(pd.io.out, if3_fire) 204 val if4_valid = RegInit(false.B) 205 val if4_fire = if4_valid && io.fetchPacket.ready 206 val if4_pc = RegEnable(if3_pc, if3_fire) 207 val if4_histPtr = RegEnable(if3_histPtr, if3_fire) 208 if4_ready := (if4_fire || !if4_valid || if4_flush) && GTimer() > 500.U 209 when (if4_flush) { if4_valid := false.B } 210 .elsewhen (if3_fire) { if4_valid := if3_valid } 211 .elsewhen(if4_fire) { if4_valid := false.B } 212 213 val if4_bp = Wire(new BranchPrediction) 214 if4_bp := bpu.io.out(2).bits 215 216 val if4_cfi_jal = if4_pd.instrs(if4_bp.jmpIdx) 217 val if4_cfi_jal_tgt = if4_pd.pc(if4_bp.jmpIdx) + Mux(if4_pd.pd(if4_bp.jmpIdx).isRVC, 218 SignExt(Cat(if4_cfi_jal(12), if4_cfi_jal(8), if4_cfi_jal(10, 9), if4_cfi_jal(6), if4_cfi_jal(7), if4_cfi_jal(2), if4_cfi_jal(11), if4_cfi_jal(5, 3), 0.U(1.W)), XLEN), 219 SignExt(Cat(if4_cfi_jal(31), if4_cfi_jal(19, 12), if4_cfi_jal(20), if4_cfi_jal(30, 21), 0.U(1.W)), XLEN)) 220 if4_bp.target := Mux(if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken, if4_cfi_jal_tgt, bpu.io.out(2).bits.target) 221 if4_bp.redirect := bpu.io.out(2).bits.redirect || if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken && if4_cfi_jal_tgt =/= bpu.io.out(2).bits.target 222 223 if4_prevHalfInstr := 0.U.asTypeOf(new PrevHalfInstr) 224 when (bpu.io.out(2).valid && if4_fire && if4_bp.saveHalfRVI) { 225 if4_prevHalfInstr.valid := true.B 226 if4_prevHalfInstr.taken := if4_bp.taken 227 if4_prevHalfInstr.fetchpc := if4_pc 228 if4_prevHalfInstr.idx := PopCount(mask(if4_pc)) - 1.U 229 if4_prevHalfInstr.pc := if4_pd.pc(if4_prevHalfInstr.idx) 230 if4_prevHalfInstr.target := if4_bp.target 231 if4_prevHalfInstr.instr := if4_pd.instrs(if4_prevHalfInstr.idx)(15, 0) 232 } 233 234 when (bpu.io.out(2).valid && if4_fire && if4_bp.redirect) { 235 if4_redirect := true.B 236 shiftPtr := true.B 237 newPtr := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_histPtr - 1.U, if4_histPtr) 238 hist(0) := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_bp.taken.asUInt, extHist(if4_histPtr)) 239 extHist(newPtr) := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_bp.taken.asUInt, extHist(if4_histPtr)) 240 when (if4_bp.saveHalfRVI) { 241 if1_npc := snpc(if4_pc) 242 }.otherwise { 243 if1_npc := if4_bp.target 244 } 245 }.elsewhen (bpu.io.out(2).valid && if4_fire/* && !if4_bp.redirect*/) { 246 when (if4_bp.saveHalfRVI && if4_bp.taken) { 247 if4_redirect := true.B 248 if1_npc := snpc(if4_pc) 249 shiftPtr := true.B 250 newPtr := if4_histPtr - 1.U 251 hist(0) := 1.U 252 extHist(newPtr) := 1.U 253 }.otherwise { 254 if4_redirect := false.B 255 } 256 }.otherwise { 257 if4_redirect := false.B 258 } 259 260 261 262 // when (bpu.io.out(2).valid && if4_fire && if4_bp.redirect) { 263 // when (!if4_bp.saveHalfRVI) { 264 // if4_redirect := true.B 265 // // if1_npc := if4_bp.target 266 // if1_npc := Mux(if4_bp.taken, if4_bp.target, snpc(if4_pc)) 267 268 // shiftPtr := true.B 269 // newPtr := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_histPtr - 1.U, if4_histPtr) 270 // hist(0) := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_bp.taken.asUInt, extHist(if4_histPtr)) 271 // extHist(newPtr) := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_bp.taken.asUInt, extHist(if4_histPtr)) 272 273 // }.otherwise { 274 // if4_redirect := true.B 275 // if1_npc := snpc(if4_pc) 276 277 // prev_half_valid := true.B 278 // prev_half_redirect := true.B 279 // prev_half_fetchpc := if4_pc 280 // val idx = PopCount(mask(if4_pc)) - 1.U 281 // prev_half_idx := idx 282 // prev_half_tgt := if4_bp.target 283 // prev_half_taken := if4_bp.taken 284 // prev_half_instr := if4_pd.instrs(idx)(15, 0) 285 286 // shiftPtr := true.B 287 // newPtr := Mux(if4_bp.hasNotTakenBrs, if4_histPtr - 1.U, if4_histPtr) 288 // hist(0) := Mux(if4_bp.hasNotTakenBrs, 0.U, extHist(if4_histPtr)) 289 // extHist(newPtr) := Mux(if4_bp.hasNotTakenBrs, 0.U, extHist(if4_histPtr)) 290 // } 291 // }.otherwise { 292 // if4_redirect := false.B 293 // } 294 295 when (io.outOfOrderBrInfo.valid && io.outOfOrderBrInfo.bits.isMisPred) { 296 shiftPtr := true.B 297 newPtr := io.outOfOrderBrInfo.bits.brInfo.histPtr - 1.U 298 hist(0) := io.outOfOrderBrInfo.bits.taken 299 extHist(newPtr) := io.outOfOrderBrInfo.bits.taken 300 } 301 302 when (io.redirect.valid) { 303 if1_npc := io.redirect.bits.target 304 } 305 306 io.icacheReq.valid := if1_valid && if2_ready 307 io.icacheReq.bits.addr := if1_npc 308 io.icacheReq.bits.mask := mask(if1_npc) 309 //io.icacheResp.ready := if3_ready 310 io.icacheResp.ready := if3_valid 311 io.icacheFlush := Cat(if3_flush, if2_flush) 312 313 val inOrderBrHist = Wire(Vec(HistoryLength, UInt(1.W))) 314 (0 until HistoryLength).foreach(i => inOrderBrHist(i) := extHist(i.U + io.inOrderBrInfo.bits.brInfo.histPtr)) 315 bpu.io.inOrderBrInfo.valid := io.inOrderBrInfo.valid 316 bpu.io.inOrderBrInfo.bits := BranchUpdateInfoWithHist(io.inOrderBrInfo.bits, inOrderBrHist.asUInt) 317 bpu.io.outOfOrderBrInfo.valid := io.outOfOrderBrInfo.valid 318 bpu.io.outOfOrderBrInfo.bits := BranchUpdateInfoWithHist(io.outOfOrderBrInfo.bits, inOrderBrHist.asUInt) // Dont care about hist 319 320 // bpu.io.flush := Cat(if4_flush, if3_flush, if2_flush) 321 bpu.io.flush := VecInit(if2_flush, if3_flush, if4_flush) 322 bpu.io.in.valid := if1_fire 323 bpu.io.in.bits.pc := if1_npc 324 bpu.io.in.bits.hist := hist.asUInt 325 bpu.io.in.bits.inMask := mask(if1_npc) 326 bpu.io.out(0).ready := if2_fire 327 bpu.io.out(1).ready := if3_fire 328 bpu.io.out(2).ready := if4_fire 329 bpu.io.predecode.valid := if4_valid 330 bpu.io.predecode.bits.mask := if4_pd.mask 331 bpu.io.predecode.bits.pd := if4_pd.pd 332 bpu.io.predecode.bits.isFetchpcEqualFirstpc := if4_pc === if4_pd.pc(0) 333 bpu.io.branchInfo.ready := if4_fire 334 335 pd.io.in := io.icacheResp.bits 336 pd.io.prev.valid := if3_hasPrevHalfInstr 337 pd.io.prev.bits := prevHalfInstr.instr 338 339 io.fetchPacket.valid := if4_valid && !io.redirect.valid 340 io.fetchPacket.bits.instrs := if4_pd.instrs 341 io.fetchPacket.bits.mask := if4_pd.mask & (Fill(PredictWidth, !if4_bp.taken) | (Fill(PredictWidth, 1.U(1.W)) >> (~if4_bp.jmpIdx))) 342 io.fetchPacket.bits.pc := if4_pd.pc 343 (0 until PredictWidth).foreach(i => io.fetchPacket.bits.pnpc(i) := if4_pd.pc(i) + Mux(if4_pd.pd(i).isRVC, 2.U, 4.U)) 344 when (if4_bp.taken) { 345 io.fetchPacket.bits.pnpc(if4_bp.jmpIdx) := if4_bp.target 346 } 347 io.fetchPacket.bits.brInfo := bpu.io.branchInfo.bits 348 (0 until PredictWidth).foreach(i => io.fetchPacket.bits.brInfo(i).histPtr := if4_histPtr) 349 io.fetchPacket.bits.pd := if4_pd.pd 350 351 // debug info 352 XSDebug(RegNext(reset.asBool) && !reset.asBool, "Reseting...\n") 353 XSDebug(io.icacheFlush(0).asBool, "Flush icache stage2...\n") 354 XSDebug(io.icacheFlush(1).asBool, "Flush icache stage3...\n") 355 XSDebug(io.redirect.valid, "Redirect from backend! isExcp=%d isMisPred=%d isReplay=%d pc=%x\n", 356 io.redirect.bits.isException, io.redirect.bits.isMisPred, io.redirect.bits.isReplay, io.redirect.bits.pc) 357 XSDebug(io.redirect.valid, p"Redirect from backend! target=${Hexadecimal(io.redirect.bits.target)} brTag=${io.redirect.bits.brTag}\n") 358 359 XSDebug("[IF1] v=%d fire=%d flush=%d pc=%x ptr=%d mask=%b\n", if1_valid, if1_fire, if1_flush, if1_npc, ptr, mask(if1_npc)) 360 XSDebug("[IF2] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d snpc=%x\n", if2_valid, if2_ready, if2_fire, if2_redirect, if2_flush, if2_pc, if2_histPtr, if2_snpc) 361 XSDebug("[IF3] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d\n", if3_valid, if3_ready, if3_fire, if3_redirect, if3_flush, if3_pc, if3_histPtr) 362 XSDebug("[IF4] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d\n", if4_valid, if4_ready, if4_fire, if4_redirect, if4_flush, if4_pc, if4_histPtr) 363 364 XSDebug("[IF1][icacheReq] v=%d r=%d addr=%x\n", io.icacheReq.valid, io.icacheReq.ready, io.icacheReq.bits.addr) 365 XSDebug("[IF1][ghr] headPtr=%d shiftPtr=%d newPtr=%d ptr=%d\n", headPtr, shiftPtr, newPtr, ptr) 366 XSDebug("[IF1][ghr] hist=%b\n", hist.asUInt) 367 XSDebug("[IF1][ghr] extHist=%b\n\n", extHist.asUInt) 368 369 XSDebug("[IF2][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n\n", if2_bp.redirect, if2_bp.taken, if2_bp.jmpIdx, if2_bp.hasNotTakenBrs, if2_bp.target, if2_bp.saveHalfRVI) 370 371 XSDebug("[IF3][icacheResp] v=%d r=%d pc=%x mask=%b\n", io.icacheResp.valid, io.icacheResp.ready, io.icacheResp.bits.pc, io.icacheResp.bits.mask) 372 XSDebug("[IF3][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if3_bp.redirect, if3_bp.taken, if3_bp.jmpIdx, if3_bp.hasNotTakenBrs, if3_bp.target, if3_bp.saveHalfRVI) 373 // XSDebug("[IF3][prevHalfInstr] v=%d redirect=%d fetchpc=%x idx=%d tgt=%x taken=%d instr=%x\n\n", 374 // prev_half_valid, prev_half_redirect, prev_half_fetchpc, prev_half_idx, prev_half_tgt, prev_half_taken, prev_half_instr) 375 XSDebug("[IF3][ prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x\n", 376 prevHalfInstr.valid, prevHalfInstr.taken, prevHalfInstr.fetchpc, prevHalfInstr.idx, prevHalfInstr.pc, prevHalfInstr.target, prevHalfInstr.instr) 377 XSDebug("[IF3][if3_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x\n\n", 378 if3_prevHalfInstr.valid, if3_prevHalfInstr.taken, if3_prevHalfInstr.fetchpc, if3_prevHalfInstr.idx, if3_prevHalfInstr.pc, if3_prevHalfInstr.target, if3_prevHalfInstr.instr) 379 380 381 XSDebug("[IF4][predecode] mask=%b\n", if4_pd.mask) 382 XSDebug("[IF4][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if4_bp.redirect, if4_bp.taken, if4_bp.jmpIdx, if4_bp.hasNotTakenBrs, if4_bp.target, if4_bp.saveHalfRVI) 383 XSDebug(if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken, "[IF4] cfi is jal! instr=%x target=%x\n", if4_cfi_jal, if4_cfi_jal_tgt) 384 XSDebug("[IF4][if4_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x\n", 385 if4_prevHalfInstr.valid, if4_prevHalfInstr.taken, if4_prevHalfInstr.fetchpc, if4_prevHalfInstr.idx, if4_prevHalfInstr.pc, if4_prevHalfInstr.target, if4_prevHalfInstr.instr) 386 XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] v=%d r=%d mask=%b\n", io.fetchPacket.valid, io.fetchPacket.ready, io.fetchPacket.bits.mask) 387 for (i <- 0 until PredictWidth) { 388 XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] %b %x pc=%x pnpc=%x pd: rvc=%d brType=%b call=%d ret=%d\n", 389 io.fetchPacket.bits.mask(i), 390 io.fetchPacket.bits.instrs(i), 391 io.fetchPacket.bits.pc(i), 392 io.fetchPacket.bits.pnpc(i), 393 io.fetchPacket.bits.pd(i).isRVC, 394 io.fetchPacket.bits.pd(i).brType, 395 io.fetchPacket.bits.pd(i).isCall, 396 io.fetchPacket.bits.pd(i).isRet 397 ) 398 } 399}