1package xiangshan.frontend 2 3import chisel3._ 4import chisel3.util._ 5import device.RAMHelper 6import xiangshan._ 7import xiangshan.utils._ 8 9trait HasIFUConst { this: XSModule => 10 val resetVector = 0x80000000L//TODO: set reset vec 11 val enableBPU = false 12 val groupAlign = log2Up(FetchWidth * 4) 13 def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W)) 14 15} 16 17class IFUIO extends XSBundle 18{ 19 val fetchPacket = DecoupledIO(new FetchPacket) 20 val redirectInfo = Input(new RedirectInfo) 21 val icacheReq = DecoupledIO(new FakeIcacheReq) 22 val icacheResp = Flipped(DecoupledIO(new FakeIcacheResp)) 23} 24 25class FakeBPU extends XSModule{ 26 val io = IO(new Bundle() { 27 val redirectInfo = Input(new RedirectInfo) 28 val in = new Bundle { val pc = Flipped(Valid(UInt(VAddrBits.W))) } 29 val btbOut = ValidIO(new BranchPrediction) 30 val tageOut = ValidIO(new BranchPrediction) 31 val predecode = Flipped(ValidIO(new Predecode)) 32 }) 33 34 io.btbOut.valid := false.B 35 io.btbOut.bits <> DontCare 36 io.tageOut.valid := false.B 37 io.tageOut.bits <> DontCare 38} 39 40 41class IFU extends XSModule with HasIFUConst 42{ 43 val io = IO(new IFUIO) 44 //val bpu = Module(new BPU) 45 val bpu = Module(new FakeBPU) 46 47 //------------------------- 48 // IF1 PC update 49 //------------------------- 50 //local 51 val if1_npc = WireInit(0.U(VAddrBits.W)) 52 val if1_valid = !reset.asBool && (GTimer() > 500.U)//TODO:this is ugly 53 val if1_pc = RegInit(resetVector.U(VAddrBits.W)) 54 //next 55 val if2_ready = WireInit(false.B) 56 val if2_snpc = Cat(if1_pc(VAddrBits-1, groupAlign) + 1.U, 0.U(groupAlign.W)) 57 val if1_ready = if2_ready 58 59 //pipe fire 60 val if1_fire = if1_valid && if1_ready 61 val if1_pcUpdate = io.redirectInfo.flush() || if1_fire 62 63 when(RegNext(reset.asBool) && !reset.asBool){ 64 //when((GTimer() === 501.U)){ //TODO:this is ugly 65 XSDebug("RESET....\n") 66 if1_npc := resetVector.U(VAddrBits.W) 67 } .elsewhen(GTimer() === 501.U){ 68 if1_npc := resetVector.U(VAddrBits.W) 69 } .otherwise{ 70 if1_npc := if2_snpc 71 } 72 73 when(if1_pcUpdate) 74 { 75 if1_pc := if1_npc 76 } 77 78 bpu.io.in.pc.valid := if1_fire 79 bpu.io.in.pc.bits := if1_npc 80 bpu.io.redirectInfo := io.redirectInfo 81 82 XSDebug("[IF1]if1_valid:%d || if1_npc:0x%x || if1_pcUpdate:%d if1_pc:0x%x || if2_ready:%d",if1_valid,if1_npc,if1_pcUpdate,if1_pc,if2_ready) 83 XSDebug(false,if1_fire,"------IF1->fire!!!") 84 XSDebug(false,true.B,"\n") 85 86 //------------------------- 87 // IF2 btb response 88 // icache visit 89 //------------------------- 90 //local 91 val if2_valid = RegEnable(next=if1_valid,init=false.B,enable=if1_fire) 92 val if2_pc = if1_pc 93 val if2_btb_taken = bpu.io.btbOut.valid && bpu.io.btbOut.bits.redirect 94 val if2_btb_insMask = bpu.io.btbOut.bits.instrValid 95 val if2_btb_target = bpu.io.btbOut.bits.target 96 97 //next 98 val if3_ready = WireInit(false.B) 99 100 //pipe fire 101 val if2_fire = if2_valid && if3_ready && io.icacheReq.fire() 102 if2_ready := (if2_fire) || !if2_valid 103 104 io.icacheReq.valid := if2_valid 105 io.icacheReq.bits.addr := groupPC(if2_pc) 106 io.icacheReq.bits.flush := io.redirectInfo.flush() 107 108 when(if2_valid && if2_btb_taken) 109 { 110 if1_npc := if2_btb_target 111 } 112 113 XSDebug("[IF2]if2_valid:%d || if2_pc:0x%x || if3_ready:%d ",if2_valid,if2_pc,if3_ready) 114 //XSDebug("[IF2-BPU-out]if2_btbTaken:%d || if2_btb_insMask:%b || if2_btb_target:0x%x \n",if2_btb_taken,if2_btb_insMask.asUInt,if2_btb_target) 115 XSDebug(false,if2_fire,"------IF2->fire!!!") 116 XSDebug(false,true.B,"\n") 117 XSDebug("[IF2-Icache-Req] icache_in_valid:%d icache_in_ready:%d\n",io.icacheReq.valid,io.icacheReq.ready) 118 119 //------------------------- 120 // IF3 icache hit check 121 //------------------------- 122 //local 123 val if3_valid = RegEnable(next=if2_valid,init=false.B,enable=if2_fire) 124 val if3_pc = RegEnable(if2_pc,if2_fire) 125 val if3_npc = RegEnable(if1_npc,if2_fire) 126 val if3_btb_target = RegEnable(if2_btb_target,if2_fire) 127 val if3_btb_taken = RegEnable(if2_btb_taken,if2_fire) 128 129 //next 130 val if4_ready = WireInit(false.B) 131 132 //pipe fire 133 val if3_fire = if3_valid && if4_ready 134 if3_ready := if3_fire || !if3_valid 135 136 137 XSDebug("[IF3]if3_valid:%d || if3_pc:0x%x if3_npc:0x%x || if4_ready:%d ",if3_valid,if3_pc,if3_npc,if4_ready) 138 XSDebug(false,if3_fire,"------IF3->fire!!!") 139 XSDebug(false,true.B,"\n") 140 141 //------------------------- 142 // IF4 icache response 143 // RAS result 144 // taget generate 145 //------------------------- 146 val if4_valid = RegEnable(next=if3_valid,init=false.B,enable=if3_fire) 147 val if4_pc = RegEnable(if3_pc,if3_fire) 148 val if4_npc = RegEnable(if3_npc,if3_fire) 149 val if4_btb_target = RegEnable(if3_btb_target,if3_fire) 150 val if4_btb_taken = RegEnable(if3_btb_taken,if3_fire) 151 val if4_tage_target = bpu.io.tageOut.bits.target 152 val if4_tage_taken = bpu.io.tageOut.valid && bpu.io.tageOut.bits.redirect 153 val if4_tage_insMask = bpu.io.tageOut.bits.instrValid 154 XSDebug("[IF4]if4_valid:%d || if4_pc:0x%x if4_npc:0x%x\n",if4_valid,if4_pc,if4_npc) 155 //XSDebug("[IF4-TAGE-out]if4_tage_taken:%d || if4_btb_insMask:%b || if4_tage_target:0x%x \n",if4_tage_taken,if4_tage_insMask.asUInt,if4_tage_target) 156 XSDebug("[IF4-ICACHE-RESP]icacheResp.valid:%d icacheResp.ready:%d\n",io.icacheResp.valid,io.icacheResp.ready) 157 158 when(if4_valid && io.icacheResp.fire() && if4_tage_taken) 159 { 160 if1_npc := if4_tage_target 161 } 162 163 164 //redirect: miss predict 165 when(io.redirectInfo.flush()){ 166 if1_npc := io.redirectInfo.redirect.target 167 if3_valid := false.B 168 if4_valid := false.B 169 } 170 XSDebug(io.redirectInfo.flush(),"[IFU-REDIRECT] target:0x%x \n",io.redirectInfo.redirect.target.asUInt) 171 172 //Output -> iBuffer 173 //io.fetchPacket <> DontCare 174 if4_ready := io.fetchPacket.ready && (io.icacheResp.valid || !if4_valid) 175 io.fetchPacket.valid := if4_valid && !io.redirectInfo.flush() 176 io.fetchPacket.bits.instrs := io.icacheResp.bits.icacheOut 177 if(enableBPU){io.fetchPacket.bits.mask := (Fill(FetchWidth*2, 1.U(1.W)) & Cat(if4_tage_insMask.map(i => Fill(2, i.asUInt))).asUInt) << if4_pc(2+log2Up(FetchWidth)-1, 1)} 178 else{io.fetchPacket.bits.mask := Fill(FetchWidth*2, 1.U(1.W)) << if4_pc(2+log2Up(FetchWidth)-1, 1)} 179 io.fetchPacket.bits.pc := if4_pc 180 181 XSDebug(io.fetchPacket.fire,"[IFU-Out-FetchPacket] starPC:0x%x GroupPC:0x%xn\n",if4_pc.asUInt,groupPC(if4_pc).asUInt) 182 XSDebug(io.fetchPacket.fire,"[IFU-Out-FetchPacket] instrmask %b\n",io.fetchPacket.bits.mask.asUInt) 183 for(i <- 0 until FetchWidth){ 184 //io.fetchPacket.bits.pnpc(i) := if1_npc 185 when (if4_tage_taken && i.U === OHToUInt(HighestBit(if4_tage_insMask.asUInt, FetchWidth))) { 186 io.fetchPacket.bits.pnpc(i) := if1_npc 187 }.otherwise { 188 io.fetchPacket.bits.pnpc(i) := groupPC(if4_pc) + ((i + 1).U << 2.U) // TODO: has bug 189 } 190 XSDebug(io.fetchPacket.fire,"[IFU-Out-FetchPacket] instruction %x pnpc:0x%x\n",io.fetchPacket.bits.instrs(i).asUInt,io.fetchPacket.bits.pnpc(i).asUInt) 191 } 192 io.fetchPacket.bits.hist := bpu.io.tageOut.bits.hist 193 io.fetchPacket.bits.btbVictimWay := bpu.io.tageOut.bits.btbVictimWay 194 io.fetchPacket.bits.predCtr := bpu.io.tageOut.bits.predCtr 195 io.fetchPacket.bits.btbHitWay := bpu.io.tageOut.bits.btbHitWay 196 io.fetchPacket.bits.tageMeta := bpu.io.tageOut.bits.tageMeta 197 io.fetchPacket.bits.rasSp := bpu.io.tageOut.bits.rasSp 198 io.fetchPacket.bits.rasTopCtr := bpu.io.tageOut.bits.rasTopCtr 199 200 //to BPU 201 bpu.io.predecode.valid := io.icacheResp.fire() && if4_valid 202 bpu.io.predecode.bits <> io.icacheResp.bits.predecode 203 bpu.io.predecode.bits.mask := Fill(FetchWidth, 1.U(1.W)) << if4_pc(2+log2Up(FetchWidth)-1, 2) //TODO: consider RVC 204 205 bpu.io.redirectInfo := io.redirectInfo 206 207 io.icacheResp.ready := io.fetchPacket.ready 208 209} 210 211