1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.RVCDecoder 23import xiangshan._ 24import xiangshan.cache.mmu._ 25import xiangshan.frontend.icache._ 26import utils._ 27import xiangshan.backend.fu.{PMPReqBundle, PMPRespBundle} 28 29trait HasInstrMMIOConst extends HasXSParameter with HasIFUConst{ 30 def mmioBusWidth = 64 31 def mmioBusBytes = mmioBusWidth / 8 32 def maxInstrLen = 32 33} 34 35trait HasIFUConst extends HasXSParameter{ 36 def addrAlign(addr: UInt, bytes: Int, highest: Int): UInt = Cat(addr(highest-1, log2Ceil(bytes)), 0.U(log2Ceil(bytes).W)) 37 def fetchQueueSize = 2 38 39 def getBasicBlockIdx( pc: UInt, start: UInt ): UInt = { 40 val byteOffset = pc - start 41 (byteOffset - instBytes.U)(log2Ceil(PredictWidth),instOffsetBits) 42 } 43} 44 45class IfuToFtqIO(implicit p:Parameters) extends XSBundle { 46 val pdWb = Valid(new PredecodeWritebackBundle) 47} 48 49class FtqInterface(implicit p: Parameters) extends XSBundle { 50 val fromFtq = Flipped(new FtqToIfuIO) 51 val toFtq = new IfuToFtqIO 52} 53 54class UncacheInterface(implicit p: Parameters) extends XSBundle { 55 val fromUncache = Flipped(DecoupledIO(new InsUncacheResp)) 56 val toUncache = DecoupledIO( new InsUncacheReq ) 57} 58 59class NewIFUIO(implicit p: Parameters) extends XSBundle { 60 val ftqInter = new FtqInterface 61 val icacheInter = Flipped(new IFUICacheIO) 62 val icacheStop = Output(Bool()) 63 val icachePerfInfo = Input(new ICachePerfInfo) 64 val toIbuffer = Decoupled(new FetchToIBuffer) 65 val uncacheInter = new UncacheInterface 66 val frontendTrigger = Flipped(new FrontendTdataDistributeIO) 67 val csrTriggerEnable = Input(Vec(4, Bool())) 68 val rob_commits = Flipped(Vec(CommitWidth, Valid(new RobCommitInfo))) 69 val iTLBInter = new TlbRequestIO 70 val pmp = new ICachePMPBundle 71 val mmioCommitRead = new mmioCommitRead 72} 73 74// record the situation in which fallThruAddr falls into 75// the middle of an RVI inst 76class LastHalfInfo(implicit p: Parameters) extends XSBundle { 77 val valid = Bool() 78 val middlePC = UInt(VAddrBits.W) 79 def matchThisBlock(startAddr: UInt) = valid && middlePC === startAddr 80} 81 82class IfuToPreDecode(implicit p: Parameters) extends XSBundle { 83 val data = if(HasCExtension) Vec(PredictWidth + 1, UInt(16.W)) else Vec(PredictWidth, UInt(32.W)) 84 val frontendTrigger = new FrontendTdataDistributeIO 85 val csrTriggerEnable = Vec(4, Bool()) 86 val pc = Vec(PredictWidth, UInt(VAddrBits.W)) 87} 88 89 90class IfuToPredChecker(implicit p: Parameters) extends XSBundle { 91 val ftqOffset = Valid(UInt(log2Ceil(PredictWidth).W)) 92 val jumpOffset = Vec(PredictWidth, UInt(XLEN.W)) 93 val target = UInt(VAddrBits.W) 94 val instrRange = Vec(PredictWidth, Bool()) 95 val instrValid = Vec(PredictWidth, Bool()) 96 val pds = Vec(PredictWidth, new PreDecodeInfo) 97 val pc = Vec(PredictWidth, UInt(VAddrBits.W)) 98} 99 100class NewIFU(implicit p: Parameters) extends XSModule 101 with HasICacheParameters 102 with HasIFUConst 103 with HasPdConst 104 with HasCircularQueuePtrHelper 105 with HasPerfEvents 106{ 107 val io = IO(new NewIFUIO) 108 val (toFtq, fromFtq) = (io.ftqInter.toFtq, io.ftqInter.fromFtq) 109 val fromICache = io.icacheInter.resp 110 val (toUncache, fromUncache) = (io.uncacheInter.toUncache , io.uncacheInter.fromUncache) 111 112 def isCrossLineReq(start: UInt, end: UInt): Bool = start(blockOffBits) ^ end(blockOffBits) 113 114 def isLastInCacheline(addr: UInt): Bool = addr(blockOffBits - 1, 1) === 0.U 115 116 class TlbExept(implicit p: Parameters) extends XSBundle{ 117 val pageFault = Bool() 118 val accessFault = Bool() 119 val mmio = Bool() 120 } 121 122 val preDecoders = Seq.fill(4){ Module(new PreDecode) } 123 124 val predChecker = Module(new PredChecker) 125 val frontendTrigger = Module(new FrontendTrigger) 126 val (checkerIn, checkerOutStage1, checkerOutStage2) = (predChecker.io.in, predChecker.io.out.stage1Out,predChecker.io.out.stage2Out) 127 128 io.iTLBInter.req_kill := false.B 129 io.iTLBInter.resp.ready := true.B 130 131 /** 132 ****************************************************************************** 133 * IFU Stage 0 134 * - send cacheline fetch request to ICacheMainPipe 135 ****************************************************************************** 136 */ 137 138 val f0_valid = fromFtq.req.valid 139 val f0_ftq_req = fromFtq.req.bits 140 val f0_doubleLine = fromFtq.req.bits.crossCacheline 141 val f0_vSetIdx = VecInit(get_idx((f0_ftq_req.startAddr)), get_idx(f0_ftq_req.nextlineStart)) 142 val f0_fire = fromFtq.req.fire() 143 144 val f0_flush, f1_flush, f2_flush, f3_flush = WireInit(false.B) 145 val from_bpu_f0_flush, from_bpu_f1_flush, from_bpu_f2_flush, from_bpu_f3_flush = WireInit(false.B) 146 147 from_bpu_f0_flush := fromFtq.flushFromBpu.shouldFlushByStage2(f0_ftq_req.ftqIdx) || 148 fromFtq.flushFromBpu.shouldFlushByStage3(f0_ftq_req.ftqIdx) 149 150 val wb_redirect , mmio_redirect, backend_redirect= WireInit(false.B) 151 val f3_wb_not_flush = WireInit(false.B) 152 153 backend_redirect := fromFtq.redirect.valid 154 f3_flush := backend_redirect || (wb_redirect && !f3_wb_not_flush) 155 f2_flush := backend_redirect || mmio_redirect || wb_redirect 156 f1_flush := f2_flush || from_bpu_f1_flush 157 f0_flush := f1_flush || from_bpu_f0_flush 158 159 val f1_ready, f2_ready, f3_ready = WireInit(false.B) 160 161 fromFtq.req.ready := f1_ready && io.icacheInter.icacheReady 162 163 /** <PERF> f0 fetch bubble */ 164 165 XSPerfAccumulate("fetch_bubble_ftq_not_valid", !fromFtq.req.valid && fromFtq.req.ready ) 166 // XSPerfAccumulate("fetch_bubble_pipe_stall", f0_valid && toICache(0).ready && toICache(1).ready && !f1_ready ) 167 // XSPerfAccumulate("fetch_bubble_icache_0_busy", f0_valid && !toICache(0).ready ) 168 // XSPerfAccumulate("fetch_bubble_icache_1_busy", f0_valid && !toICache(1).ready ) 169 XSPerfAccumulate("fetch_flush_backend_redirect", backend_redirect ) 170 XSPerfAccumulate("fetch_flush_wb_redirect", wb_redirect ) 171 XSPerfAccumulate("fetch_flush_bpu_f1_flush", from_bpu_f1_flush ) 172 XSPerfAccumulate("fetch_flush_bpu_f0_flush", from_bpu_f0_flush ) 173 174 175 /** 176 ****************************************************************************** 177 * IFU Stage 1 178 * - calculate pc/half_pc/cut_ptr for every instruction 179 ****************************************************************************** 180 */ 181 182 val f1_valid = RegInit(false.B) 183 val f1_ftq_req = RegEnable(f0_ftq_req, f0_fire) 184 // val f1_situation = RegEnable(f0_situation, f0_fire) 185 val f1_doubleLine = RegEnable(f0_doubleLine, f0_fire) 186 val f1_vSetIdx = RegEnable(f0_vSetIdx, f0_fire) 187 val f1_fire = f1_valid && f2_ready 188 189 f1_ready := f1_fire || !f1_valid 190 191 from_bpu_f1_flush := fromFtq.flushFromBpu.shouldFlushByStage3(f1_ftq_req.ftqIdx) && f1_valid 192 // from_bpu_f1_flush := false.B 193 194 when(f1_flush) {f1_valid := false.B} 195 .elsewhen(f0_fire && !f0_flush) {f1_valid := true.B} 196 .elsewhen(f1_fire) {f1_valid := false.B} 197 198 val f1_pc = VecInit((0 until PredictWidth).map(i => f1_ftq_req.startAddr + (i * 2).U)) 199 val f1_half_snpc = VecInit((0 until PredictWidth).map(i => f1_ftq_req.startAddr + ((i+2) * 2).U)) 200 val f1_cut_ptr = if(HasCExtension) VecInit((0 until PredictWidth + 1).map(i => Cat(0.U(1.W), f1_ftq_req.startAddr(blockOffBits-1, 1)) + i.U )) 201 else VecInit((0 until PredictWidth).map(i => Cat(0.U(1.W), f1_ftq_req.startAddr(blockOffBits-1, 2)) + i.U )) 202 203 /** 204 ****************************************************************************** 205 * IFU Stage 2 206 * - icache response data (latched for pipeline stop) 207 * - generate exceprion bits for every instruciton (page fault/access fault/mmio) 208 * - generate predicted instruction range (1 means this instruciton is in this fetch packet) 209 * - cut data from cachlines to packet instruction code 210 * - instruction predecode and RVC expand 211 ****************************************************************************** 212 */ 213 214 val icacheRespAllValid = WireInit(false.B) 215 216 val f2_valid = RegInit(false.B) 217 val f2_ftq_req = RegEnable(f1_ftq_req, f1_fire) 218 // val f2_situation = RegEnable(f1_situation, f1_fire) 219 val f2_doubleLine = RegEnable(f1_doubleLine, f1_fire) 220 val f2_vSetIdx = RegEnable(f1_vSetIdx, f1_fire) 221 val f2_fire = f2_valid && f3_ready && icacheRespAllValid 222 223 f2_ready := f2_fire || !f2_valid 224 //TODO: addr compare may be timing critical 225 val f2_icache_all_resp_wire = fromICache(0).valid && (fromICache(0).bits.vaddr === f2_ftq_req.startAddr) && ((fromICache(1).valid && (fromICache(1).bits.vaddr === f2_ftq_req.nextlineStart)) || !f2_doubleLine) 226 val f2_icache_all_resp_reg = RegInit(false.B) 227 228 icacheRespAllValid := f2_icache_all_resp_reg || f2_icache_all_resp_wire 229 230 io.icacheStop := !f3_ready 231 232 when(f2_flush) {f2_icache_all_resp_reg := false.B} 233 .elsewhen(f2_valid && f2_icache_all_resp_wire && !f3_ready) {f2_icache_all_resp_reg := true.B} 234 .elsewhen(f2_fire && f2_icache_all_resp_reg) {f2_icache_all_resp_reg := false.B} 235 236 when(f2_flush) {f2_valid := false.B} 237 .elsewhen(f1_fire && !f1_flush) {f2_valid := true.B } 238 .elsewhen(f2_fire) {f2_valid := false.B} 239 240 // val f2_cache_response_data = ResultHoldBypass(valid = f2_icache_all_resp_wire, data = VecInit(fromICache.map(_.bits.readData))) 241 val f2_cache_response_reg_data = VecInit(fromICache.map(_.bits.registerData)) 242 val f2_cache_response_sram_data = VecInit(fromICache.map(_.bits.sramData)) 243 val f2_cache_response_select = VecInit(fromICache.map(_.bits.select)) 244 245 246 val f2_except_pf = VecInit((0 until PortNumber).map(i => fromICache(i).bits.tlbExcp.pageFault)) 247 val f2_except_af = VecInit((0 until PortNumber).map(i => fromICache(i).bits.tlbExcp.accessFault)) 248 val f2_mmio = fromICache(0).bits.tlbExcp.mmio && !fromICache(0).bits.tlbExcp.accessFault && 249 !fromICache(0).bits.tlbExcp.pageFault 250 251 val f2_pc = RegEnable(f1_pc, f1_fire) 252 val f2_half_snpc = RegEnable(f1_half_snpc, f1_fire) 253 val f2_cut_ptr = RegEnable(f1_cut_ptr, f1_fire) 254 255 val f2_resend_vaddr = RegEnable(f1_ftq_req.startAddr + 2.U, f1_fire) 256 257 def isNextLine(pc: UInt, startAddr: UInt) = { 258 startAddr(blockOffBits) ^ pc(blockOffBits) 259 } 260 261 def isLastInLine(pc: UInt) = { 262 pc(blockOffBits - 1, 0) === "b111110".U 263 } 264 265 val f2_foldpc = VecInit(f2_pc.map(i => XORFold(i(VAddrBits-1,1), MemPredPCWidth))) 266 val f2_jump_range = Fill(PredictWidth, !f2_ftq_req.ftqOffset.valid) | Fill(PredictWidth, 1.U(1.W)) >> ~f2_ftq_req.ftqOffset.bits 267 val f2_ftr_range = Fill(PredictWidth, f2_ftq_req.ftqOffset.valid) | Fill(PredictWidth, 1.U(1.W)) >> ~getBasicBlockIdx(f2_ftq_req.nextStartAddr, f2_ftq_req.startAddr) 268 val f2_instr_range = f2_jump_range & f2_ftr_range 269 val f2_pf_vec = VecInit((0 until PredictWidth).map(i => (!isNextLine(f2_pc(i), f2_ftq_req.startAddr) && f2_except_pf(0) || isNextLine(f2_pc(i), f2_ftq_req.startAddr) && f2_doubleLine && f2_except_pf(1)))) 270 val f2_af_vec = VecInit((0 until PredictWidth).map(i => (!isNextLine(f2_pc(i), f2_ftq_req.startAddr) && f2_except_af(0) || isNextLine(f2_pc(i), f2_ftq_req.startAddr) && f2_doubleLine && f2_except_af(1)))) 271 272 val f2_paddrs = VecInit((0 until PortNumber).map(i => fromICache(i).bits.paddr)) 273 val f2_perf_info = io.icachePerfInfo 274 275 def cut(cacheline: UInt, cutPtr: Vec[UInt]) : Vec[UInt] ={ 276 require(HasCExtension) 277 // if(HasCExtension){ 278 val partCacheline = cacheline((blockBytes * 8 * 2 * 3) / 4 - 1, 0) 279 val result = Wire(Vec(PredictWidth + 1, UInt(16.W))) 280 val dataVec = cacheline.asTypeOf(Vec(blockBytes * 3 /4, UInt(16.W))) //47 16-bit data vector 281 (0 until PredictWidth + 1).foreach( i => 282 result(i) := dataVec(cutPtr(i)) //the max ptr is 3*blockBytes/4-1 283 ) 284 result 285 // } else { 286 // val result = Wire(Vec(PredictWidth, UInt(32.W)) ) 287 // val dataVec = cacheline.asTypeOf(Vec(blockBytes * 2/ 4, UInt(32.W))) 288 // (0 until PredictWidth).foreach( i => 289 // result(i) := dataVec(cutPtr(i)) 290 // ) 291 // result 292 // } 293 } 294 295 val f2_data_2_cacheline = Wire(Vec(4, UInt((2 * blockBits).W))) 296 f2_data_2_cacheline(0) := Cat(f2_cache_response_reg_data(1) , f2_cache_response_reg_data(0)) 297 f2_data_2_cacheline(1) := Cat(f2_cache_response_reg_data(1) , f2_cache_response_sram_data(0)) 298 f2_data_2_cacheline(2) := Cat(f2_cache_response_sram_data(1) , f2_cache_response_reg_data(0)) 299 f2_data_2_cacheline(3) := Cat(f2_cache_response_sram_data(1) , f2_cache_response_sram_data(0)) 300 301 val f2_cut_data = VecInit(f2_data_2_cacheline.map(data => cut( data, f2_cut_ptr ))) 302 303 val f2_predecod_ptr = Wire(UInt(2.W)) 304 f2_predecod_ptr := Cat(f2_cache_response_select(1),f2_cache_response_select(0)) 305 306 /** predecode (include RVC expander) */ 307 // preDecoderRegIn.data := f2_reg_cut_data 308 // preDecoderRegInIn.frontendTrigger := io.frontendTrigger 309 // preDecoderRegInIn.csrTriggerEnable := io.csrTriggerEnable 310 // preDecoderRegIn.pc := f2_pc 311 312 val preDecoderOut = Mux1H(UIntToOH(f2_predecod_ptr), preDecoders.map(_.io.out)) 313 for(i <- 0 until 4){ 314 val preDecoderIn = preDecoders(i).io.in 315 preDecoderIn.data := f2_cut_data(i) 316 preDecoderIn.frontendTrigger := io.frontendTrigger 317 preDecoderIn.csrTriggerEnable := io.csrTriggerEnable 318 preDecoderIn.pc := f2_pc 319 } 320 321 //val f2_expd_instr = preDecoderOut.expInstr 322 val f2_instr = preDecoderOut.instr 323 val f2_pd = preDecoderOut.pd 324 val f2_jump_offset = preDecoderOut.jumpOffset 325 val f2_hasHalfValid = preDecoderOut.hasHalfValid 326 val f2_crossPageFault = VecInit((0 until PredictWidth).map(i => isLastInLine(f2_pc(i)) && !f2_except_pf(0) && f2_doubleLine && f2_except_pf(1) && !f2_pd(i).isRVC )) 327 328 XSPerfAccumulate("fetch_bubble_icache_not_resp", f2_valid && !icacheRespAllValid ) 329 330 331 /** 332 ****************************************************************************** 333 * IFU Stage 3 334 * - handle MMIO instruciton 335 * -send request to Uncache fetch Unit 336 * -every packet include 1 MMIO instruction 337 * -MMIO instructions will stop fetch pipeline until commiting from RoB 338 * -flush to snpc (send ifu_redirect to Ftq) 339 * - Ibuffer enqueue 340 * - check predict result in Frontend (jalFault/retFault/notCFIFault/invalidTakenFault/targetFault) 341 * - handle last half RVI instruction 342 ****************************************************************************** 343 */ 344 345 val f3_valid = RegInit(false.B) 346 val f3_ftq_req = RegEnable(f2_ftq_req, f2_fire) 347 // val f3_situation = RegEnable(f2_situation, f2_fire) 348 val f3_doubleLine = RegEnable(f2_doubleLine, f2_fire) 349 val f3_fire = io.toIbuffer.fire() 350 351 f3_ready := f3_fire || !f3_valid 352 353 val f3_cut_data = RegEnable(next = f2_cut_data(f2_predecod_ptr), enable=f2_fire) 354 355 val f3_except_pf = RegEnable(f2_except_pf, f2_fire) 356 val f3_except_af = RegEnable(f2_except_af, f2_fire) 357 val f3_mmio = RegEnable(f2_mmio , f2_fire) 358 359 //val f3_expd_instr = RegEnable(next = f2_expd_instr, enable = f2_fire) 360 val f3_instr = RegEnable(next = f2_instr, enable = f2_fire) 361 val f3_expd_instr = VecInit((0 until PredictWidth).map{ i => 362 val expander = Module(new RVCExpander) 363 expander.io.in := f3_instr(i) 364 expander.io.out.bits 365 }) 366 367 val f3_pd = RegEnable(next = f2_pd, enable = f2_fire) 368 val f3_jump_offset = RegEnable(next = f2_jump_offset, enable = f2_fire) 369 val f3_af_vec = RegEnable(next = f2_af_vec, enable = f2_fire) 370 val f3_pf_vec = RegEnable(next = f2_pf_vec , enable = f2_fire) 371 val f3_pc = RegEnable(next = f2_pc, enable = f2_fire) 372 val f3_half_snpc = RegEnable(next = f2_half_snpc, enable = f2_fire) 373 val f3_instr_range = RegEnable(next = f2_instr_range, enable = f2_fire) 374 val f3_foldpc = RegEnable(next = f2_foldpc, enable = f2_fire) 375 val f3_crossPageFault = RegEnable(next = f2_crossPageFault, enable = f2_fire) 376 val f3_hasHalfValid = RegEnable(next = f2_hasHalfValid, enable = f2_fire) 377 val f3_except = VecInit((0 until 2).map{i => f3_except_pf(i) || f3_except_af(i)}) 378 val f3_has_except = f3_valid && (f3_except_af.reduce(_||_) || f3_except_pf.reduce(_||_)) 379 val f3_pAddrs = RegEnable(f2_paddrs, f2_fire) 380 val f3_resend_vaddr = RegEnable(f2_resend_vaddr, f2_fire) 381 382 when(f3_valid && !f3_ftq_req.ftqOffset.valid){ 383 assert(f3_ftq_req.startAddr + 32.U >= f3_ftq_req.nextStartAddr , "More tha 32 Bytes fetch is not allowed!") 384 } 385 386 /*** MMIO State Machine***/ 387 val f3_mmio_data = Reg(Vec(2, UInt(16.W))) 388 val mmio_is_RVC = RegInit(false.B) 389 val mmio_resend_addr =RegInit(0.U(PAddrBits.W)) 390 val mmio_resend_af = RegInit(false.B) 391 val mmio_resend_pf = RegInit(false.B) 392 393 //last instuction finish 394 val is_first_instr = RegInit(true.B) 395 io.mmioCommitRead.mmioFtqPtr := RegNext(f3_ftq_req.ftqIdx + 1.U) 396 397 val m_idle :: m_waitLastCmt:: m_sendReq :: m_waitResp :: m_sendTLB :: m_tlbResp :: m_sendPMP :: m_resendReq :: m_waitResendResp :: m_waitCommit :: m_commited :: Nil = Enum(11) 398 val mmio_state = RegInit(m_idle) 399 400 val f3_req_is_mmio = f3_mmio && f3_valid 401 val mmio_commit = VecInit(io.rob_commits.map{commit => commit.valid && commit.bits.ftqIdx === f3_ftq_req.ftqIdx && commit.bits.ftqOffset === 0.U}).asUInt.orR 402 val f3_mmio_req_commit = f3_req_is_mmio && mmio_state === m_commited 403 404 val f3_mmio_to_commit = f3_req_is_mmio && mmio_state === m_waitCommit 405 val f3_mmio_to_commit_next = RegNext(f3_mmio_to_commit) 406 val f3_mmio_can_go = f3_mmio_to_commit && !f3_mmio_to_commit_next 407 408 val fromFtqRedirectReg = RegNext(fromFtq.redirect,init = 0.U.asTypeOf(fromFtq.redirect)) 409 val mmioF3Flush = RegNext(f3_flush,init = false.B) 410 val f3_ftq_flush_self = fromFtqRedirectReg.valid && RedirectLevel.flushItself(fromFtqRedirectReg.bits.level) 411 val f3_ftq_flush_by_older = fromFtqRedirectReg.valid && isBefore(fromFtqRedirectReg.bits.ftqIdx, f3_ftq_req.ftqIdx) 412 413 val f3_need_not_flush = f3_req_is_mmio && fromFtqRedirectReg.valid && !f3_ftq_flush_self && !f3_ftq_flush_by_older 414 415 when(is_first_instr && mmio_commit){ 416 is_first_instr := false.B 417 } 418 419 when(f3_flush && !f3_req_is_mmio) {f3_valid := false.B} 420 .elsewhen(mmioF3Flush && f3_req_is_mmio && !f3_need_not_flush) {f3_valid := false.B} 421 .elsewhen(f2_fire && !f2_flush ) {f3_valid := true.B } 422 .elsewhen(io.toIbuffer.fire() && !f3_req_is_mmio) {f3_valid := false.B} 423 .elsewhen{f3_req_is_mmio && f3_mmio_req_commit} {f3_valid := false.B} 424 425 val f3_mmio_use_seq_pc = RegInit(false.B) 426 427 val (redirect_ftqIdx, redirect_ftqOffset) = (fromFtqRedirectReg.bits.ftqIdx,fromFtqRedirectReg.bits.ftqOffset) 428 val redirect_mmio_req = fromFtqRedirectReg.valid && redirect_ftqIdx === f3_ftq_req.ftqIdx && redirect_ftqOffset === 0.U 429 430 when(RegNext(f2_fire && !f2_flush) && f3_req_is_mmio) { f3_mmio_use_seq_pc := true.B } 431 .elsewhen(redirect_mmio_req) { f3_mmio_use_seq_pc := false.B } 432 433 f3_ready := Mux(f3_req_is_mmio, io.toIbuffer.ready && f3_mmio_req_commit || !f3_valid , io.toIbuffer.ready || !f3_valid) 434 435 // mmio state machine 436 switch(mmio_state){ 437 is(m_idle){ 438 when(f3_req_is_mmio){ 439 mmio_state := m_waitLastCmt 440 } 441 } 442 443 is(m_waitLastCmt){ 444 when(is_first_instr){ 445 mmio_state := m_sendReq 446 }.otherwise{ 447 mmio_state := Mux(io.mmioCommitRead.mmioLastCommit, m_sendReq, m_waitLastCmt) 448 } 449 } 450 451 is(m_sendReq){ 452 mmio_state := Mux(toUncache.fire(), m_waitResp, m_sendReq ) 453 } 454 455 is(m_waitResp){ 456 when(fromUncache.fire()){ 457 val isRVC = fromUncache.bits.data(1,0) =/= 3.U 458 val needResend = !isRVC && f3_pAddrs(0)(2,1) === 3.U 459 mmio_state := Mux(needResend, m_sendTLB , m_waitCommit) 460 461 mmio_is_RVC := isRVC 462 f3_mmio_data(0) := fromUncache.bits.data(15,0) 463 f3_mmio_data(1) := fromUncache.bits.data(31,16) 464 } 465 } 466 467 is(m_sendTLB){ 468 when( io.iTLBInter.req.valid && !io.iTLBInter.resp.bits.miss ){ 469 mmio_state := m_tlbResp 470 } 471 } 472 473 is(m_tlbResp){ 474 val tlbExept = io.iTLBInter.resp.bits.excp(0).pf.instr || 475 io.iTLBInter.resp.bits.excp(0).af.instr 476 mmio_state := Mux(tlbExept,m_waitCommit,m_sendPMP) 477 mmio_resend_addr := io.iTLBInter.resp.bits.paddr(0) 478 mmio_resend_af := mmio_resend_af || io.iTLBInter.resp.bits.excp(0).af.instr 479 mmio_resend_pf := mmio_resend_pf || io.iTLBInter.resp.bits.excp(0).pf.instr 480 } 481 482 is(m_sendPMP){ 483 val pmpExcpAF = io.pmp.resp.instr || !io.pmp.resp.mmio 484 mmio_state := Mux(pmpExcpAF, m_waitCommit , m_resendReq) 485 mmio_resend_af := pmpExcpAF 486 } 487 488 is(m_resendReq){ 489 mmio_state := Mux(toUncache.fire(), m_waitResendResp, m_resendReq ) 490 } 491 492 is(m_waitResendResp){ 493 when(fromUncache.fire()){ 494 mmio_state := m_waitCommit 495 f3_mmio_data(1) := fromUncache.bits.data(15,0) 496 } 497 } 498 499 is(m_waitCommit){ 500 when(mmio_commit){ 501 mmio_state := m_commited 502 } 503 } 504 505 //normal mmio instruction 506 is(m_commited){ 507 mmio_state := m_idle 508 mmio_is_RVC := false.B 509 mmio_resend_addr := 0.U 510 } 511 } 512 513 //exception or flush by older branch prediction 514 when(f3_ftq_flush_self || f3_ftq_flush_by_older) { 515 mmio_state := m_idle 516 mmio_is_RVC := false.B 517 mmio_resend_addr := 0.U 518 mmio_resend_af := false.B 519 f3_mmio_data.map(_ := 0.U) 520 } 521 522 toUncache.valid := ((mmio_state === m_sendReq) || (mmio_state === m_resendReq)) && f3_req_is_mmio 523 toUncache.bits.addr := Mux((mmio_state === m_resendReq), mmio_resend_addr, f3_pAddrs(0)) 524 fromUncache.ready := true.B 525 526 io.iTLBInter.req.valid := (mmio_state === m_sendTLB) && f3_req_is_mmio 527 io.iTLBInter.req.bits.size := 3.U 528 io.iTLBInter.req.bits.vaddr := f3_resend_vaddr 529 io.iTLBInter.req.bits.debug.pc := f3_resend_vaddr 530 531 io.iTLBInter.req.bits.kill := false.B // IFU use itlb for mmio, doesn't need sync, set it to false 532 io.iTLBInter.req.bits.cmd := TlbCmd.exec 533 io.iTLBInter.req.bits.debug.robIdx := DontCare 534 io.iTLBInter.req.bits.debug.isFirstIssue := DontCare 535 536 io.pmp.req.valid := (mmio_state === m_sendPMP) && f3_req_is_mmio 537 io.pmp.req.bits.addr := mmio_resend_addr 538 io.pmp.req.bits.size := 3.U 539 io.pmp.req.bits.cmd := TlbCmd.exec 540 541 val f3_lastHalf = RegInit(0.U.asTypeOf(new LastHalfInfo)) 542 543 val f3_predecode_range = VecInit(preDecoderOut.pd.map(inst => inst.valid)).asUInt 544 val f3_mmio_range = VecInit((0 until PredictWidth).map(i => if(i ==0) true.B else false.B)) 545 val f3_instr_valid = Wire(Vec(PredictWidth, Bool())) 546 547 /*** prediction result check ***/ 548 checkerIn.ftqOffset := f3_ftq_req.ftqOffset 549 checkerIn.jumpOffset := f3_jump_offset 550 checkerIn.target := f3_ftq_req.nextStartAddr 551 checkerIn.instrRange := f3_instr_range.asTypeOf(Vec(PredictWidth, Bool())) 552 checkerIn.instrValid := f3_instr_valid.asTypeOf(Vec(PredictWidth, Bool())) 553 checkerIn.pds := f3_pd 554 checkerIn.pc := f3_pc 555 556 /*** handle half RVI in the last 2 Bytes ***/ 557 558 def hasLastHalf(idx: UInt) = { 559 //!f3_pd(idx).isRVC && checkerOutStage1.fixedRange(idx) && f3_instr_valid(idx) && !checkerOutStage1.fixedTaken(idx) && !checkerOutStage2.fixedMissPred(idx) && ! f3_req_is_mmio 560 !f3_pd(idx).isRVC && checkerOutStage1.fixedRange(idx) && f3_instr_valid(idx) && !checkerOutStage1.fixedTaken(idx) && ! f3_req_is_mmio 561 } 562 563 val f3_last_validIdx = ~ParallelPriorityEncoder(checkerOutStage1.fixedRange.reverse) 564 565 val f3_hasLastHalf = hasLastHalf((PredictWidth - 1).U) 566 val f3_false_lastHalf = hasLastHalf(f3_last_validIdx) 567 val f3_false_snpc = f3_half_snpc(f3_last_validIdx) 568 569 val f3_lastHalf_mask = VecInit((0 until PredictWidth).map( i => if(i ==0) false.B else true.B )).asUInt() 570 val f3_lastHalf_disable = RegInit(false.B) 571 572 when(f3_flush || (f3_fire && f3_lastHalf_disable)){ 573 f3_lastHalf_disable := false.B 574 } 575 576 when (f3_flush) { 577 f3_lastHalf.valid := false.B 578 }.elsewhen (f3_fire) { 579 f3_lastHalf.valid := f3_hasLastHalf && !f3_lastHalf_disable 580 f3_lastHalf.middlePC := f3_ftq_req.nextStartAddr 581 } 582 583 f3_instr_valid := Mux(f3_lastHalf.valid,f3_hasHalfValid ,VecInit(f3_pd.map(inst => inst.valid))) 584 585 /*** frontend Trigger ***/ 586 frontendTrigger.io.pds := f3_pd 587 frontendTrigger.io.pc := f3_pc 588 frontendTrigger.io.data := f3_cut_data 589 590 frontendTrigger.io.frontendTrigger := io.frontendTrigger 591 frontendTrigger.io.csrTriggerEnable := io.csrTriggerEnable 592 593 val f3_triggered = frontendTrigger.io.triggered 594 595 /*** send to Ibuffer ***/ 596 597 io.toIbuffer.valid := f3_valid && (!f3_req_is_mmio || f3_mmio_can_go) && !f3_flush 598 io.toIbuffer.bits.instrs := f3_expd_instr 599 io.toIbuffer.bits.valid := f3_instr_valid.asUInt 600 io.toIbuffer.bits.enqEnable := checkerOutStage1.fixedRange.asUInt & f3_instr_valid.asUInt 601 io.toIbuffer.bits.pd := f3_pd 602 io.toIbuffer.bits.ftqPtr := f3_ftq_req.ftqIdx 603 io.toIbuffer.bits.pc := f3_pc 604 io.toIbuffer.bits.ftqOffset.zipWithIndex.map{case(a, i) => a.bits := i.U; a.valid := checkerOutStage1.fixedTaken(i) && !f3_req_is_mmio} 605 io.toIbuffer.bits.foldpc := f3_foldpc 606 io.toIbuffer.bits.ipf := VecInit(f3_pf_vec.zip(f3_crossPageFault).map{case (pf, crossPF) => pf || crossPF}) 607 io.toIbuffer.bits.acf := f3_af_vec 608 io.toIbuffer.bits.crossPageIPFFix := f3_crossPageFault 609 io.toIbuffer.bits.triggered := f3_triggered 610 611 when(f3_lastHalf.valid){ 612 io.toIbuffer.bits.enqEnable := checkerOutStage1.fixedRange.asUInt & f3_instr_valid.asUInt & f3_lastHalf_mask 613 io.toIbuffer.bits.valid := f3_lastHalf_mask & f3_instr_valid.asUInt 614 } 615 616 617 618 //Write back to Ftq 619 val f3_cache_fetch = f3_valid && !(f2_fire && !f2_flush) 620 val finishFetchMaskReg = RegNext(f3_cache_fetch) 621 622 val mmioFlushWb = Wire(Valid(new PredecodeWritebackBundle)) 623 val f3_mmio_missOffset = Wire(ValidUndirectioned(UInt(log2Ceil(PredictWidth).W))) 624 f3_mmio_missOffset.valid := f3_req_is_mmio 625 f3_mmio_missOffset.bits := 0.U 626 627 mmioFlushWb.valid := (f3_req_is_mmio && mmio_state === m_waitCommit && RegNext(fromUncache.fire()) && f3_mmio_use_seq_pc) 628 mmioFlushWb.bits.pc := f3_pc 629 mmioFlushWb.bits.pd := f3_pd 630 mmioFlushWb.bits.pd.zipWithIndex.map{case(instr,i) => instr.valid := f3_mmio_range(i)} 631 mmioFlushWb.bits.ftqIdx := f3_ftq_req.ftqIdx 632 mmioFlushWb.bits.ftqOffset := f3_ftq_req.ftqOffset.bits 633 mmioFlushWb.bits.misOffset := f3_mmio_missOffset 634 mmioFlushWb.bits.cfiOffset := DontCare 635 mmioFlushWb.bits.target := Mux(mmio_is_RVC, f3_ftq_req.startAddr + 2.U , f3_ftq_req.startAddr + 4.U) 636 mmioFlushWb.bits.jalTarget := DontCare 637 mmioFlushWb.bits.instrRange := f3_mmio_range 638 639 /** external predecode for MMIO instruction */ 640 when(f3_req_is_mmio){ 641 val inst = Cat(f3_mmio_data(1), f3_mmio_data(0)) 642 val currentIsRVC = isRVC(inst) 643 644 val brType::isCall::isRet::Nil = brInfo(inst) 645 val jalOffset = jal_offset(inst, currentIsRVC) 646 val brOffset = br_offset(inst, currentIsRVC) 647 648 io.toIbuffer.bits.instrs (0) := new RVCDecoder(inst, XLEN).decode.bits 649 650 651 io.toIbuffer.bits.pd(0).valid := true.B 652 io.toIbuffer.bits.pd(0).isRVC := currentIsRVC 653 io.toIbuffer.bits.pd(0).brType := brType 654 io.toIbuffer.bits.pd(0).isCall := isCall 655 io.toIbuffer.bits.pd(0).isRet := isRet 656 657 io.toIbuffer.bits.acf(0) := mmio_resend_af 658 io.toIbuffer.bits.ipf(0) := mmio_resend_pf 659 io.toIbuffer.bits.crossPageIPFFix(0) := mmio_resend_pf 660 661 io.toIbuffer.bits.enqEnable := f3_mmio_range.asUInt 662 663 mmioFlushWb.bits.pd(0).valid := true.B 664 mmioFlushWb.bits.pd(0).isRVC := currentIsRVC 665 mmioFlushWb.bits.pd(0).brType := brType 666 mmioFlushWb.bits.pd(0).isCall := isCall 667 mmioFlushWb.bits.pd(0).isRet := isRet 668 } 669 670 mmio_redirect := (f3_req_is_mmio && mmio_state === m_waitCommit && RegNext(fromUncache.fire()) && f3_mmio_use_seq_pc) 671 672 XSPerfAccumulate("fetch_bubble_ibuffer_not_ready", io.toIbuffer.valid && !io.toIbuffer.ready ) 673 674 675 /** 676 ****************************************************************************** 677 * IFU Write Back Stage 678 * - write back predecode information to Ftq to update 679 * - redirect if found fault prediction 680 * - redirect if has false hit last half (last PC is not start + 32 Bytes, but in the midle of an notCFI RVI instruction) 681 ****************************************************************************** 682 */ 683 684 val wb_valid = RegNext(RegNext(f2_fire && !f2_flush) && !f3_req_is_mmio && !f3_flush) 685 val wb_ftq_req = RegNext(f3_ftq_req) 686 687 val wb_check_result_stage1 = RegNext(checkerOutStage1) 688 val wb_check_result_stage2 = checkerOutStage2 689 val wb_instr_range = RegNext(io.toIbuffer.bits.enqEnable) 690 val wb_pc = RegNext(f3_pc) 691 val wb_pd = RegNext(f3_pd) 692 val wb_instr_valid = RegNext(f3_instr_valid) 693 694 /* false hit lastHalf */ 695 val wb_lastIdx = RegNext(f3_last_validIdx) 696 val wb_false_lastHalf = RegNext(f3_false_lastHalf) && wb_lastIdx =/= (PredictWidth - 1).U 697 val wb_false_target = RegNext(f3_false_snpc) 698 699 val wb_half_flush = wb_false_lastHalf 700 val wb_half_target = wb_false_target 701 702 /* false oversize */ 703 val lastIsRVC = wb_instr_range.asTypeOf(Vec(PredictWidth,Bool())).last && wb_pd.last.isRVC 704 val lastIsRVI = wb_instr_range.asTypeOf(Vec(PredictWidth,Bool()))(PredictWidth - 2) && !wb_pd(PredictWidth - 2).isRVC 705 val lastTaken = wb_check_result_stage1.fixedTaken.last 706 707 f3_wb_not_flush := wb_ftq_req.ftqIdx === f3_ftq_req.ftqIdx && f3_valid && wb_valid 708 709 /** if a req with a last half but miss predicted enters in wb stage, and this cycle f3 stalls, 710 * we set a flag to notify f3 that the last half flag need not to be set. 711 */ 712 //f3_fire is after wb_valid 713 when(wb_valid && RegNext(f3_hasLastHalf,init = false.B) 714 && wb_check_result_stage2.fixedMissPred(PredictWidth - 1) && !f3_fire && !RegNext(f3_fire,init = false.B) && !f3_flush 715 ){ 716 f3_lastHalf_disable := true.B 717 } 718 719 //wb_valid and f3_fire are in same cycle 720 when(wb_valid && RegNext(f3_hasLastHalf,init = false.B) 721 && wb_check_result_stage2.fixedMissPred(PredictWidth - 1) && f3_fire 722 ){ 723 f3_lastHalf.valid := false.B 724 } 725 726 val checkFlushWb = Wire(Valid(new PredecodeWritebackBundle)) 727 checkFlushWb.valid := wb_valid 728 checkFlushWb.bits.pc := wb_pc 729 checkFlushWb.bits.pd := wb_pd 730 checkFlushWb.bits.pd.zipWithIndex.map{case(instr,i) => instr.valid := wb_instr_valid(i)} 731 checkFlushWb.bits.ftqIdx := wb_ftq_req.ftqIdx 732 checkFlushWb.bits.ftqOffset := wb_ftq_req.ftqOffset.bits 733 checkFlushWb.bits.misOffset.valid := ParallelOR(wb_check_result_stage2.fixedMissPred) || wb_half_flush 734 checkFlushWb.bits.misOffset.bits := Mux(wb_half_flush, wb_lastIdx, ParallelPriorityEncoder(wb_check_result_stage2.fixedMissPred)) 735 checkFlushWb.bits.cfiOffset.valid := ParallelOR(wb_check_result_stage1.fixedTaken) 736 checkFlushWb.bits.cfiOffset.bits := ParallelPriorityEncoder(wb_check_result_stage1.fixedTaken) 737 checkFlushWb.bits.target := Mux(wb_half_flush, wb_half_target, wb_check_result_stage2.fixedTarget(ParallelPriorityEncoder(wb_check_result_stage2.fixedMissPred))) 738 checkFlushWb.bits.jalTarget := wb_check_result_stage2.fixedTarget(ParallelPriorityEncoder(VecInit(wb_pd.zip(wb_instr_valid).map{case (pd, v) => v && pd.isJal }))) 739 checkFlushWb.bits.instrRange := wb_instr_range.asTypeOf(Vec(PredictWidth, Bool())) 740 741 toFtq.pdWb := Mux(wb_valid, checkFlushWb, mmioFlushWb) 742 743 wb_redirect := checkFlushWb.bits.misOffset.valid && wb_valid 744 745 /*write back flush type*/ 746 val checkFaultType = wb_check_result_stage2.faultType 747 val checkJalFault = wb_valid && checkFaultType.map(_.isjalFault).reduce(_||_) 748 val checkRetFault = wb_valid && checkFaultType.map(_.isRetFault).reduce(_||_) 749 val checkTargetFault = wb_valid && checkFaultType.map(_.istargetFault).reduce(_||_) 750 val checkNotCFIFault = wb_valid && checkFaultType.map(_.notCFIFault).reduce(_||_) 751 val checkInvalidTaken = wb_valid && checkFaultType.map(_.invalidTakenFault).reduce(_||_) 752 753 754 XSPerfAccumulate("predecode_flush_jalFault", checkJalFault ) 755 XSPerfAccumulate("predecode_flush_retFault", checkRetFault ) 756 XSPerfAccumulate("predecode_flush_targetFault", checkTargetFault ) 757 XSPerfAccumulate("predecode_flush_notCFIFault", checkNotCFIFault ) 758 XSPerfAccumulate("predecode_flush_incalidTakenFault", checkInvalidTaken ) 759 760 when(checkRetFault){ 761 XSDebug("startAddr:%x nextstartAddr:%x taken:%d takenIdx:%d\n", 762 wb_ftq_req.startAddr, wb_ftq_req.nextStartAddr, wb_ftq_req.ftqOffset.valid, wb_ftq_req.ftqOffset.bits) 763 } 764 765 /** performance counter */ 766 val f3_perf_info = RegEnable(f2_perf_info, f2_fire) 767 val f3_req_0 = io.toIbuffer.fire() 768 val f3_req_1 = io.toIbuffer.fire() && f3_doubleLine 769 val f3_hit_0 = io.toIbuffer.fire() && f3_perf_info.bank_hit(0) 770 val f3_hit_1 = io.toIbuffer.fire() && f3_doubleLine & f3_perf_info.bank_hit(1) 771 val f3_hit = f3_perf_info.hit 772 val perfEvents = Seq( 773 ("frontendFlush ", wb_redirect ), 774 ("ifu_req ", io.toIbuffer.fire() ), 775 ("ifu_miss ", io.toIbuffer.fire() && !f3_perf_info.hit ), 776 ("ifu_req_cacheline_0 ", f3_req_0 ), 777 ("ifu_req_cacheline_1 ", f3_req_1 ), 778 ("ifu_req_cacheline_0_hit ", f3_hit_1 ), 779 ("ifu_req_cacheline_1_hit ", f3_hit_1 ), 780 ("only_0_hit ", f3_perf_info.only_0_hit && io.toIbuffer.fire() ), 781 ("only_0_miss ", f3_perf_info.only_0_miss && io.toIbuffer.fire() ), 782 ("hit_0_hit_1 ", f3_perf_info.hit_0_hit_1 && io.toIbuffer.fire() ), 783 ("hit_0_miss_1 ", f3_perf_info.hit_0_miss_1 && io.toIbuffer.fire() ), 784 ("miss_0_hit_1 ", f3_perf_info.miss_0_hit_1 && io.toIbuffer.fire() ), 785 ("miss_0_miss_1 ", f3_perf_info.miss_0_miss_1 && io.toIbuffer.fire() ), 786 ) 787 generatePerfEvent() 788 789 XSPerfAccumulate("ifu_req", io.toIbuffer.fire() ) 790 XSPerfAccumulate("ifu_miss", io.toIbuffer.fire() && !f3_hit ) 791 XSPerfAccumulate("ifu_req_cacheline_0", f3_req_0 ) 792 XSPerfAccumulate("ifu_req_cacheline_1", f3_req_1 ) 793 XSPerfAccumulate("ifu_req_cacheline_0_hit", f3_hit_0 ) 794 XSPerfAccumulate("ifu_req_cacheline_1_hit", f3_hit_1 ) 795 XSPerfAccumulate("frontendFlush", wb_redirect ) 796 XSPerfAccumulate("only_0_hit", f3_perf_info.only_0_hit && io.toIbuffer.fire() ) 797 XSPerfAccumulate("only_0_miss", f3_perf_info.only_0_miss && io.toIbuffer.fire() ) 798 XSPerfAccumulate("hit_0_hit_1", f3_perf_info.hit_0_hit_1 && io.toIbuffer.fire() ) 799 XSPerfAccumulate("hit_0_miss_1", f3_perf_info.hit_0_miss_1 && io.toIbuffer.fire() ) 800 XSPerfAccumulate("miss_0_hit_1", f3_perf_info.miss_0_hit_1 && io.toIbuffer.fire() ) 801 XSPerfAccumulate("miss_0_miss_1", f3_perf_info.miss_0_miss_1 && io.toIbuffer.fire() ) 802 XSPerfAccumulate("hit_0_except_1", f3_perf_info.hit_0_except_1 && io.toIbuffer.fire() ) 803 XSPerfAccumulate("miss_0_except_1", f3_perf_info.miss_0_except_1 && io.toIbuffer.fire() ) 804 XSPerfAccumulate("except_0", f3_perf_info.except_0 && io.toIbuffer.fire() ) 805} 806 807