1package xiangshan.frontend 2 3import chisel3._ 4import chisel3.util._ 5import device.RAMHelper 6import xiangshan._ 7import utils._ 8 9trait HasIFUConst { this: XSModule => 10 val resetVector = 0x80000000L//TODO: set reset vec 11 val groupAlign = log2Up(FetchWidth * 4 * 2) 12 def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W)) 13 // each 1 bit in mask stands for 2 Bytes 14 def mask(pc: UInt): UInt = (Fill(PredictWidth * 2, 1.U(1.W)) >> pc(groupAlign - 1, 1))(PredictWidth - 1, 0) 15 def snpc(pc: UInt): UInt = pc + (PopCount(mask(pc)) << 1) 16} 17 18class IFUIO extends XSBundle 19{ 20 val fetchPacket = DecoupledIO(new FetchPacket) 21 val redirect = Flipped(ValidIO(new Redirect)) 22 val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 23 val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 24 val icacheReq = DecoupledIO(new FakeIcacheReq) 25 val icacheResp = Flipped(DecoupledIO(new FakeIcacheResp)) 26 val icacheFlush = Output(UInt(2.W)) 27} 28 29 30class IFU extends XSModule with HasIFUConst 31{ 32 val io = IO(new IFUIO) 33 val bpu = BPU(EnableBPU) 34 val pd = Module(new PreDecode) 35 36 val if2_redirect, if3_redirect, if4_redirect = WireInit(false.B) 37 val if1_flush, if2_flush, if3_flush, if4_flush = WireInit(false.B) 38 39 if4_flush := io.redirect.valid 40 if3_flush := if4_flush || if4_redirect 41 if2_flush := if3_flush || if3_redirect 42 if1_flush := if2_flush || if2_redirect 43 44 //********************** IF1 ****************************// 45 val if1_valid = !reset.asBool 46 val if1_npc = WireInit(0.U(VAddrBits.W)) 47 val if2_ready = WireInit(false.B) 48 val if1_fire = if1_valid && (if2_ready || if1_flush) && io.icacheReq.ready 49 50 // val extHist = VecInit(Fill(ExtHistoryLength, RegInit(0.U(1.W)))) 51 val extHist = RegInit(VecInit(Seq.fill(ExtHistoryLength)(0.U(1.W)))) 52 val headPtr = RegInit(0.U(log2Up(ExtHistoryLength).W)) 53 val shiftPtr = WireInit(false.B) 54 val newPtr = Wire(UInt(log2Up(ExtHistoryLength).W)) 55 val ptr = Mux(shiftPtr, newPtr, headPtr) 56 when (shiftPtr) { headPtr := newPtr } 57 val hist = Wire(Vec(HistoryLength, UInt(1.W))) 58 for (i <- 0 until HistoryLength) { 59 hist(i) := extHist(ptr + i.U) 60 } 61 62 newPtr := headPtr 63 shiftPtr := false.B 64 65 //********************** IF2 ****************************// 66 val if2_valid = RegEnable(next = if1_valid, init = false.B, enable = if1_fire) 67 val if3_ready = WireInit(false.B) 68 val if2_fire = if2_valid && if3_ready && !if2_flush 69 val if2_pc = RegEnable(next = if1_npc, init = resetVector.U, enable = if1_fire) 70 val if2_snpc = snpc(if2_pc) 71 val if2_histPtr = RegEnable(ptr, if1_fire) 72 if2_ready := if2_fire || !if2_valid || if2_flush 73 when (if2_flush) { if2_valid := if1_fire } 74 .elsewhen (if1_fire) { if2_valid := if1_valid } 75 .elsewhen (if2_fire) { if2_valid := false.B } 76 77 when (RegNext(reset.asBool) && !reset.asBool) { 78 if1_npc := resetVector.U(VAddrBits.W) 79 }.elsewhen (if2_fire) { 80 if1_npc := if2_snpc 81 }.otherwise { 82 if1_npc := RegNext(if1_npc) 83 } 84 85 val if2_bp = bpu.io.out(0).bits 86 if2_redirect := if2_fire && bpu.io.out(0).valid && if2_bp.redirect// && !if2_bp.saveHalfRVI 87 when (if2_redirect) { 88 if1_npc := if2_bp.target 89 } 90 91 when (if2_fire && (if2_bp.takenOnBr || if2_bp.hasNotTakenBrs)) { 92 shiftPtr := true.B 93 newPtr := headPtr - 1.U 94 hist(0) := if2_bp.takenOnBr.asUInt 95 extHist(newPtr) := if2_bp.takenOnBr.asUInt 96 } 97 98 //********************** IF3 ****************************// 99 val if3_valid = RegEnable(next = if2_valid, init = false.B, enable = if2_fire) 100 val if4_ready = WireInit(false.B) 101 val if3_fire = if3_valid && if4_ready && io.icacheResp.valid && !if3_flush 102 val if3_pc = RegEnable(if2_pc, if2_fire) 103 val if3_histPtr = RegEnable(if2_histPtr, if2_fire) 104 if3_ready := if3_fire || !if3_valid || if3_flush 105 when (if3_flush) { if3_valid := false.B } 106 .elsewhen (if2_fire) { if3_valid := if2_valid } 107 .elsewhen (if3_fire) { if3_valid := false.B } 108 109 val if3_bp = bpu.io.out(1).bits 110 111 class PrevHalfInstr extends Bundle { 112 val valid = Bool() 113 val taken = Bool() 114 val fetchpc = UInt(VAddrBits.W) // only for debug 115 val idx = UInt(VAddrBits.W) // only for debug 116 val pc = UInt(VAddrBits.W) 117 val target = UInt(VAddrBits.W) 118 val instr = UInt(16.W) 119 val takenOnBr = Bool() 120 } 121 122 val if3_prevHalfInstr = RegInit(0.U.asTypeOf(new PrevHalfInstr)) 123 val if4_prevHalfInstr = Wire(new PrevHalfInstr) 124 when (if4_prevHalfInstr.valid) { 125 if3_prevHalfInstr := if4_prevHalfInstr 126 } 127 val prevHalfInstr = Mux(if4_prevHalfInstr.valid, if4_prevHalfInstr, if3_prevHalfInstr) 128 129 val if3_hasPrevHalfInstr = prevHalfInstr.valid && (prevHalfInstr.pc + 2.U) === if3_pc 130 if3_redirect := if3_fire && bpu.io.out(1).valid && (if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.redirect/* && !if3_bp.saveHalfRVI*/ ) 131 when (if3_redirect) { 132 if1_npc := Mux(if3_hasPrevHalfInstr && prevHalfInstr.taken, prevHalfInstr.target, if3_bp.target) 133 } 134 135 when (if3_fire && if3_redirect) { 136 shiftPtr := true.B 137 newPtr := Mux(if3_hasPrevHalfInstr && prevHalfInstr.takenOnBr || if3_bp.takenOnBr || if3_bp.hasNotTakenBrs, if3_histPtr - 1.U, if3_histPtr) 138 hist(0) := Mux(if3_hasPrevHalfInstr && prevHalfInstr.takenOnBr || if3_bp.takenOnBr || if3_bp.hasNotTakenBrs, 139 (if3_hasPrevHalfInstr && prevHalfInstr.takenOnBr || if3_bp.takenOnBr).asUInt, 140 extHist(if3_histPtr)) 141 extHist(newPtr) := Mux(if3_hasPrevHalfInstr && prevHalfInstr.takenOnBr || if3_bp.takenOnBr || if3_bp.hasNotTakenBrs, 142 (if3_hasPrevHalfInstr && prevHalfInstr.takenOnBr || if3_bp.takenOnBr).asUInt, 143 extHist(if3_histPtr)) 144 } 145 146 147 148 // val prev_half_valid = RegInit(false.B) 149 // val prev_half_redirect = RegInit(false.B) 150 // val prev_half_fetchpc = Reg(UInt(VAddrBits.W)) 151 // val prev_half_idx = Reg(UInt(log2Up(PredictWidth).W)) 152 // val prev_half_tgt = Reg(UInt(VAddrBits.W)) 153 // val prev_half_taken = RegInit(false.B) 154 // val prev_half_instr = Reg(UInt(16.W)) 155 // when (if3_flush) { 156 // prev_half_valid := false.B 157 // prev_half_redirect := false.B 158 // }.elsewhen (if3_fire && if3_bp.saveHalfRVI) { 159 // prev_half_valid := true.B 160 // prev_half_redirect := if3_bp.redirect && bpu.io.out(1).valid 161 // prev_half_fetchpc := if3_pc 162 // val idx = Mux(if3_bp.redirect && bpu.io.out(1).valid, if3_bp.jmpIdx, PopCount(mask(if3_pc)) - 1.U) 163 // prev_half_idx := idx 164 // prev_half_tgt := if3_bp.target 165 // prev_half_taken := if3_bp.taken 166 // prev_half_instr := pd.io.out.instrs(idx)(15, 0) 167 // }.elsewhen (if3_fire) { 168 // prev_half_valid := false.B 169 // prev_half_redirect := false.B 170 // } 171 172 // when (bpu.io.out(1).valid && if3_fire) { 173 // when (prev_half_valid && prev_half_taken) { 174 // if3_redirect := true.B 175 // if1_npc := prev_half_tgt 176 // shiftPtr := true.B 177 // newPtr := if3_histPtr - 1.U 178 // hist(0) := 1.U 179 // extHist(newPtr) := 1.U 180 // }.elsewhen (if3_bp.redirect && !if3_bp.saveHalfRVI) { 181 // if3_redirect := true.B 182 // if1_npc := if3_bp.target 183 // shiftPtr := true.B 184 // newPtr := Mux(if3_bp.taken || if3_bp.hasNotTakenBrs, if3_histPtr - 1.U, if3_histPtr) 185 // hist(0) := Mux(if3_bp.taken || if3_bp.hasNotTakenBrs, if3_bp.taken.asUInt, extHist(if3_histPtr)) 186 // extHist(newPtr) := Mux(if3_bp.taken || if3_bp.hasNotTakenBrs, if3_bp.taken.asUInt, extHist(if3_histPtr)) 187 // }.elsewhen (if3_bp.saveHalfRVI) { 188 // if3_redirect := true.B 189 // if1_npc := snpc(if3_pc) 190 // shiftPtr := true.B 191 // newPtr := Mux(if3_bp.hasNotTakenBrs, if3_histPtr - 1.U, if3_histPtr) 192 // hist(0) := Mux(if3_bp.hasNotTakenBrs, 0.U, extHist(if3_histPtr)) 193 // extHist(newPtr) := Mux(if3_bp.hasNotTakenBrs, 0.U, extHist(if3_histPtr)) 194 // }.otherwise { 195 // if3_redirect := false.B 196 // } 197 // }.otherwise { 198 // if3_redirect := false.B 199 // } 200 201 202 //********************** IF4 ****************************// 203 val if4_pd = RegEnable(pd.io.out, if3_fire) 204 val if4_valid = RegInit(false.B) 205 val if4_fire = if4_valid && io.fetchPacket.ready 206 val if4_pc = RegEnable(if3_pc, if3_fire) 207 val if4_histPtr = RegEnable(if3_histPtr, if3_fire) 208 if4_ready := (if4_fire || !if4_valid || if4_flush) && GTimer() > 500.U 209 when (if4_flush) { if4_valid := false.B } 210 .elsewhen (if3_fire) { if4_valid := if3_valid } 211 .elsewhen(if4_fire) { if4_valid := false.B } 212 213 val if4_bp = Wire(new BranchPrediction) 214 if4_bp := bpu.io.out(2).bits 215 216 val if4_cfi_jal = if4_pd.instrs(if4_bp.jmpIdx) 217 val if4_cfi_jal_tgt = if4_pd.pc(if4_bp.jmpIdx) + Mux(if4_pd.pd(if4_bp.jmpIdx).isRVC, 218 SignExt(Cat(if4_cfi_jal(12), if4_cfi_jal(8), if4_cfi_jal(10, 9), if4_cfi_jal(6), if4_cfi_jal(7), if4_cfi_jal(2), if4_cfi_jal(11), if4_cfi_jal(5, 3), 0.U(1.W)), XLEN), 219 SignExt(Cat(if4_cfi_jal(31), if4_cfi_jal(19, 12), if4_cfi_jal(20), if4_cfi_jal(30, 21), 0.U(1.W)), XLEN)) 220 if4_bp.target := Mux(if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken, if4_cfi_jal_tgt, bpu.io.out(2).bits.target) 221 if4_bp.redirect := bpu.io.out(2).bits.redirect || if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken && if4_cfi_jal_tgt =/= bpu.io.out(2).bits.target 222 223 if4_prevHalfInstr := 0.U.asTypeOf(new PrevHalfInstr) 224 when (bpu.io.out(2).valid && if4_fire && if4_bp.saveHalfRVI) { 225 if4_prevHalfInstr.valid := true.B 226 if4_prevHalfInstr.taken := if4_bp.taken 227 if4_prevHalfInstr.takenOnBr := if4_bp.takenOnBr 228 if4_prevHalfInstr.fetchpc := if4_pc 229 if4_prevHalfInstr.idx := PopCount(mask(if4_pc)) - 1.U 230 if4_prevHalfInstr.pc := if4_pd.pc(if4_prevHalfInstr.idx) 231 if4_prevHalfInstr.target := if4_bp.target 232 if4_prevHalfInstr.instr := if4_pd.instrs(if4_prevHalfInstr.idx)(15, 0) 233 } 234 235 when (bpu.io.out(2).valid && if4_fire && if4_bp.redirect) { 236 if4_redirect := true.B 237 shiftPtr := true.B 238 newPtr := Mux(if4_bp.takenOnBr || if4_bp.hasNotTakenBrs, if4_histPtr - 1.U, if4_histPtr) 239 hist(0) := Mux(if4_bp.takenOnBr || if4_bp.hasNotTakenBrs, if4_bp.takenOnBr.asUInt, extHist(if4_histPtr)) 240 extHist(newPtr) := Mux(if4_bp.takenOnBr || if4_bp.hasNotTakenBrs, if4_bp.takenOnBr.asUInt, extHist(if4_histPtr)) 241 when (if4_bp.saveHalfRVI) { 242 if1_npc := snpc(if4_pc) 243 }.otherwise { 244 if1_npc := if4_bp.target 245 } 246 }.elsewhen (bpu.io.out(2).valid && if4_fire/* && !if4_bp.redirect*/) { 247 when (if4_bp.saveHalfRVI && if4_bp.takenOnBr) { 248 if4_redirect := true.B 249 if1_npc := snpc(if4_pc) 250 shiftPtr := true.B 251 newPtr := if4_histPtr - 1.U 252 hist(0) := 1.U 253 extHist(newPtr) := 1.U 254 }.elsewhen (if4_bp.saveHalfRVI && if4_bp.taken) { 255 if4_redirect := true.B 256 if1_npc := snpc(if4_pc) 257 shiftPtr := true.B 258 newPtr := if4_histPtr 259 hist(0) := extHist(if4_histPtr) 260 extHist(newPtr) := extHist(if4_histPtr) 261 }.otherwise { 262 if4_redirect := false.B 263 } 264 }.otherwise { 265 if4_redirect := false.B 266 } 267 268 269 270 // when (bpu.io.out(2).valid && if4_fire && if4_bp.redirect) { 271 // when (!if4_bp.saveHalfRVI) { 272 // if4_redirect := true.B 273 // // if1_npc := if4_bp.target 274 // if1_npc := Mux(if4_bp.taken, if4_bp.target, snpc(if4_pc)) 275 276 // shiftPtr := true.B 277 // newPtr := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_histPtr - 1.U, if4_histPtr) 278 // hist(0) := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_bp.taken.asUInt, extHist(if4_histPtr)) 279 // extHist(newPtr) := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_bp.taken.asUInt, extHist(if4_histPtr)) 280 281 // }.otherwise { 282 // if4_redirect := true.B 283 // if1_npc := snpc(if4_pc) 284 285 // prev_half_valid := true.B 286 // prev_half_redirect := true.B 287 // prev_half_fetchpc := if4_pc 288 // val idx = PopCount(mask(if4_pc)) - 1.U 289 // prev_half_idx := idx 290 // prev_half_tgt := if4_bp.target 291 // prev_half_taken := if4_bp.taken 292 // prev_half_instr := if4_pd.instrs(idx)(15, 0) 293 294 // shiftPtr := true.B 295 // newPtr := Mux(if4_bp.hasNotTakenBrs, if4_histPtr - 1.U, if4_histPtr) 296 // hist(0) := Mux(if4_bp.hasNotTakenBrs, 0.U, extHist(if4_histPtr)) 297 // extHist(newPtr) := Mux(if4_bp.hasNotTakenBrs, 0.U, extHist(if4_histPtr)) 298 // } 299 // }.otherwise { 300 // if4_redirect := false.B 301 // } 302 303 when (io.outOfOrderBrInfo.valid && io.outOfOrderBrInfo.bits.isMisPred) { 304 val b = io.outOfOrderBrInfo.bits 305 val oldPtr = b.brInfo.histPtr 306 shiftPtr := true.B 307 when (!b.pd.isBr && !b.brInfo.sawNotTakenBranch) { 308 // If mispredicted cfi is not a branch, 309 // and there wasn't any not taken branch before it, 310 // we should only recover the pointer to an unshifted state 311 newPtr := oldPtr 312 }.otherwise { 313 newPtr := oldPtr - 1.U 314 hist(0) := b.taken 315 extHist(newPtr) := b.taken 316 } 317 } 318 319 when (io.redirect.valid) { 320 if1_npc := io.redirect.bits.target 321 } 322 323 io.icacheReq.valid := if1_valid && if2_ready 324 io.icacheReq.bits.addr := if1_npc 325 io.icacheResp.ready := if3_ready 326 io.icacheFlush := Cat(if3_flush, if2_flush) 327 328 val inOrderBrHist = Wire(Vec(HistoryLength, UInt(1.W))) 329 (0 until HistoryLength).foreach(i => inOrderBrHist(i) := extHist(i.U + io.inOrderBrInfo.bits.brInfo.histPtr)) 330 bpu.io.inOrderBrInfo.valid := io.inOrderBrInfo.valid 331 bpu.io.inOrderBrInfo.bits := BranchUpdateInfoWithHist(io.inOrderBrInfo.bits, inOrderBrHist.asUInt) 332 bpu.io.outOfOrderBrInfo.valid := io.outOfOrderBrInfo.valid 333 bpu.io.outOfOrderBrInfo.bits := BranchUpdateInfoWithHist(io.outOfOrderBrInfo.bits, inOrderBrHist.asUInt) // Dont care about hist 334 335 // bpu.io.flush := Cat(if4_flush, if3_flush, if2_flush) 336 bpu.io.flush := VecInit(if2_flush, if3_flush, if4_flush) 337 bpu.io.in.valid := if1_fire 338 bpu.io.in.bits.pc := if1_npc 339 bpu.io.in.bits.hist := hist.asUInt 340 bpu.io.in.bits.inMask := mask(if1_npc) 341 bpu.io.out(0).ready := if2_fire 342 bpu.io.out(1).ready := if3_fire 343 bpu.io.out(2).ready := if4_fire 344 bpu.io.predecode.valid := if4_valid 345 bpu.io.predecode.bits.mask := if4_pd.mask 346 bpu.io.predecode.bits.pd := if4_pd.pd 347 bpu.io.predecode.bits.isFetchpcEqualFirstpc := if4_pc === if4_pd.pc(0) 348 bpu.io.branchInfo.ready := if4_fire 349 350 pd.io.in := io.icacheResp.bits 351 pd.io.prev.valid := if3_hasPrevHalfInstr 352 pd.io.prev.bits := prevHalfInstr.instr 353 354 io.fetchPacket.valid := if4_valid && !io.redirect.valid 355 io.fetchPacket.bits.instrs := if4_pd.instrs 356 io.fetchPacket.bits.mask := if4_pd.mask & (Fill(PredictWidth, !if4_bp.taken) | (Fill(PredictWidth, 1.U(1.W)) >> (~if4_bp.jmpIdx))) 357 io.fetchPacket.bits.pc := if4_pd.pc 358 (0 until PredictWidth).foreach(i => io.fetchPacket.bits.pnpc(i) := if4_pd.pc(i) + Mux(if4_pd.pd(i).isRVC, 2.U, 4.U)) 359 when (if4_bp.taken) { 360 io.fetchPacket.bits.pnpc(if4_bp.jmpIdx) := if4_bp.target 361 } 362 io.fetchPacket.bits.brInfo := bpu.io.branchInfo.bits 363 (0 until PredictWidth).foreach(i => io.fetchPacket.bits.brInfo(i).histPtr := if4_histPtr) 364 io.fetchPacket.bits.pd := if4_pd.pd 365 366 // debug info 367 XSDebug(RegNext(reset.asBool) && !reset.asBool, "Reseting...\n") 368 XSDebug(io.icacheFlush(0).asBool, "Flush icache stage2...\n") 369 XSDebug(io.icacheFlush(1).asBool, "Flush icache stage3...\n") 370 XSDebug(io.redirect.valid, "Redirect from backend! isExcp=%d isMisPred=%d isReplay=%d pc=%x\n", 371 io.redirect.bits.isException, io.redirect.bits.isMisPred, io.redirect.bits.isReplay, io.redirect.bits.pc) 372 XSDebug(io.redirect.valid, p"Redirect from backend! target=${Hexadecimal(io.redirect.bits.target)} brTag=${io.redirect.bits.brTag}\n") 373 374 XSDebug("[IF1] v=%d fire=%d flush=%d pc=%x ptr=%d mask=%b\n", if1_valid, if1_fire, if1_flush, if1_npc, ptr, mask(if1_npc)) 375 XSDebug("[IF2] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d snpc=%x\n", if2_valid, if2_ready, if2_fire, if2_redirect, if2_flush, if2_pc, if2_histPtr, if2_snpc) 376 XSDebug("[IF3] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d\n", if3_valid, if3_ready, if3_fire, if3_redirect, if3_flush, if3_pc, if3_histPtr) 377 XSDebug("[IF4] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d\n", if4_valid, if4_ready, if4_fire, if4_redirect, if4_flush, if4_pc, if4_histPtr) 378 379 XSDebug("[IF1][icacheReq] v=%d r=%d addr=%x\n", io.icacheReq.valid, io.icacheReq.ready, io.icacheReq.bits.addr) 380 XSDebug("[IF1][ghr] headPtr=%d shiftPtr=%d newPtr=%d ptr=%d\n", headPtr, shiftPtr, newPtr, ptr) 381 XSDebug("[IF1][ghr] hist=%b\n", hist.asUInt) 382 XSDebug("[IF1][ghr] extHist=%b\n\n", extHist.asUInt) 383 384 XSDebug("[IF2][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n\n", if2_bp.redirect, if2_bp.taken, if2_bp.jmpIdx, if2_bp.hasNotTakenBrs, if2_bp.target, if2_bp.saveHalfRVI) 385 386 XSDebug("[IF3][icacheResp] v=%d r=%d pc=%x mask=%b\n", io.icacheResp.valid, io.icacheResp.ready, io.icacheResp.bits.pc, io.icacheResp.bits.mask) 387 XSDebug("[IF3][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if3_bp.redirect, if3_bp.taken, if3_bp.jmpIdx, if3_bp.hasNotTakenBrs, if3_bp.target, if3_bp.saveHalfRVI) 388 // XSDebug("[IF3][prevHalfInstr] v=%d redirect=%d fetchpc=%x idx=%d tgt=%x taken=%d instr=%x\n\n", 389 // prev_half_valid, prev_half_redirect, prev_half_fetchpc, prev_half_idx, prev_half_tgt, prev_half_taken, prev_half_instr) 390 XSDebug("[IF3][ prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x\n", 391 prevHalfInstr.valid, prevHalfInstr.taken, prevHalfInstr.fetchpc, prevHalfInstr.idx, prevHalfInstr.pc, prevHalfInstr.target, prevHalfInstr.instr) 392 XSDebug("[IF3][if3_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x\n\n", 393 if3_prevHalfInstr.valid, if3_prevHalfInstr.taken, if3_prevHalfInstr.fetchpc, if3_prevHalfInstr.idx, if3_prevHalfInstr.pc, if3_prevHalfInstr.target, if3_prevHalfInstr.instr) 394 395 396 XSDebug("[IF4][predecode] mask=%b\n", if4_pd.mask) 397 XSDebug("[IF4][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if4_bp.redirect, if4_bp.taken, if4_bp.jmpIdx, if4_bp.hasNotTakenBrs, if4_bp.target, if4_bp.saveHalfRVI) 398 XSDebug(if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken, "[IF4] cfi is jal! instr=%x target=%x\n", if4_cfi_jal, if4_cfi_jal_tgt) 399 XSDebug("[IF4][if4_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x\n", 400 if4_prevHalfInstr.valid, if4_prevHalfInstr.taken, if4_prevHalfInstr.fetchpc, if4_prevHalfInstr.idx, if4_prevHalfInstr.pc, if4_prevHalfInstr.target, if4_prevHalfInstr.instr) 401 XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] v=%d r=%d mask=%b\n", io.fetchPacket.valid, io.fetchPacket.ready, io.fetchPacket.bits.mask) 402 for (i <- 0 until PredictWidth) { 403 XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] %b %x pc=%x pnpc=%x pd: rvc=%d brType=%b call=%d ret=%d\n", 404 io.fetchPacket.bits.mask(i), 405 io.fetchPacket.bits.instrs(i), 406 io.fetchPacket.bits.pc(i), 407 io.fetchPacket.bits.pnpc(i), 408 io.fetchPacket.bits.pd(i).isRVC, 409 io.fetchPacket.bits.pd(i).brType, 410 io.fetchPacket.bits.pd(i).isCall, 411 io.fetchPacket.bits.pd(i).isRet 412 ) 413 } 414}