1package xiangshan.frontend 2 3import chisel3._ 4import chisel3.util._ 5import device.RAMHelper 6import xiangshan._ 7import xiangshan.utils._ 8 9trait HasIFUConst { this: XSModule => 10 val resetVector = 0x80000000L//TODO: set reset vec 11 12 val groupAlign = log2Up(FetchWidth * 4) 13 def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W)) 14 15} 16 17class IFUIO extends XSBundle 18{ 19 val fetchPacket = DecoupledIO(new FetchPacket) 20 val redirectInfo = Input(new RedirectInfo) 21 val icacheReq = DecoupledIO(new FakeIcacheReq) 22 val icacheResp = Flipped(DecoupledIO(new FakeIcacheResp)) 23} 24 25/* 26class FakeBPU extends XSModule{ 27 val io = IO(new Bundle() { 28 val in = new Bundle { val pc = Flipped(Valid(UInt(VAddrBits.W))) } 29 val btbOut = ValidIO(new BranchPrediction) 30 val tageOut = ValidIO(new BranchPrediction) 31 val predecode = Flipped(ValidIO(new Predecode)) 32 }) 33 34 io.btbOut.valid := false.B 35 io.btbOut.bits <> DontCare 36 io.tageOut.valid := false.B 37 io.tageOut.bits <> DontCare 38} 39*/ 40 41 42class IFU extends XSModule with HasIFUConst 43{ 44 val io = IO(new IFUIO) 45 val bpu = Module(new BPU) 46 //val bpu = Module(new FakeBPU) 47 48 //------------------------- 49 // IF1 PC update 50 //------------------------- 51 //local 52 val if1_npc = WireInit(0.U(VAddrBits.W)) 53 val if1_valid = !reset.asBool //TODO:this is ugly 54 val if1_pc = RegInit(resetVector.U(VAddrBits.W)) 55 //next 56 val if2_ready = WireInit(false.B) 57 val if2_snpc = Cat(if1_pc(VAddrBits-1, groupAlign) + 1.U, 0.U(groupAlign.W)) 58 val if1_ready = if2_ready 59 60 //pipe fire 61 val if1_fire = if1_valid && if1_ready 62 val if1_pcUpdate = io.redirectInfo.flush() || if1_fire 63 64 when(RegNext(reset.asBool) && !reset.asBool){ 65 //when((GTimer() === 501.U)){ //TODO:this is ugly 66 XSDebug("RESET....\n") 67 if1_npc := resetVector.U(VAddrBits.W) 68 } .otherwise{ 69 if1_npc := if2_snpc 70 } 71 72 when(if1_pcUpdate) 73 { 74 if1_pc := if1_npc 75 } 76 77 bpu.io.in.pc.valid := if1_fire 78 bpu.io.in.pc.bits := if1_npc 79 80 XSDebug("[IF1]if1_valid:%d || if1_npc:0x%x || if1_pcUpdate:%d if1_pc:0x%x || if2_ready:%d",if1_valid,if1_npc,if1_pcUpdate,if1_pc,if2_ready) 81 XSDebug(false,if1_fire,"------IF1->fire!!!") 82 XSDebug(false,true.B,"\n") 83 84 //------------------------- 85 // IF2 btb response 86 // icache visit 87 //------------------------- 88 //local 89 val if2_valid = RegEnable(next=if1_valid,init=false.B,enable=if1_fire) 90 val if2_pc = if1_pc 91 val if2_btb_taken = bpu.io.btbOut.valid && bpu.io.btbOut.bits.redirect 92 val if2_btb_insMask = bpu.io.btbOut.bits.instrValid 93 val if2_btb_target = bpu.io.btbOut.bits.target 94 95 //next 96 val if3_ready = WireInit(false.B) 97 98 //pipe fire 99 val if2_fire = if2_valid && if3_ready && io.icacheReq.fire() 100 if2_ready := (if2_fire) || !if2_valid 101 102 io.icacheReq.valid := if2_valid 103 io.icacheReq.bits.addr := groupPC(if2_pc) 104 io.icacheReq.bits.flush := io.redirectInfo.flush() 105 106 when(if2_valid && if2_btb_taken) 107 { 108 if1_npc := if2_btb_target 109 } 110 111 XSDebug("[IF2]if2_valid:%d || if2_pc:0x%x || if3_ready:%d ",if2_valid,if2_pc,if3_ready) 112 //XSDebug("[IF2-BPU-out]if2_btbTaken:%d || if2_btb_insMask:%b || if2_btb_target:0x%x \n",if2_btb_taken,if2_btb_insMask.asUInt,if2_btb_target) 113 XSDebug(false,if2_fire,"------IF2->fire!!!") 114 XSDebug(false,true.B,"\n") 115 XSDebug("[IF2-Icache-Req] icache_in_valid:%d icache_in_ready:%d\n",io.icacheReq.valid,io.icacheReq.ready) 116 117 //------------------------- 118 // IF3 icache hit check 119 //------------------------- 120 //local 121 val if3_valid = RegEnable(next=if2_valid,init=false.B,enable=if2_fire) 122 val if3_pc = RegEnable(if2_pc,if2_fire) 123 val if3_btb_target = RegEnable(if2_btb_target,if2_fire) 124 val if3_btb_taken = RegEnable(if2_btb_taken,if2_fire) 125 126 //next 127 val if4_ready = WireInit(false.B) 128 129 //pipe fire 130 val if3_fire = if3_valid && if4_ready 131 if3_ready := if3_fire || !if3_valid 132 133 134 XSDebug("[IF3]if3_valid:%d || if3_pc:0x%x || if4_ready:%d ",if3_valid,if3_pc,if4_ready) 135 XSDebug(false,if3_fire,"------IF3->fire!!!") 136 XSDebug(false,true.B,"\n") 137 138 //------------------------- 139 // IF4 icache response 140 // RAS result 141 // taget generate 142 //------------------------- 143 val if4_valid = RegEnable(next=if3_valid,init=false.B,enable=if3_fire) 144 val if4_pc = RegEnable(if3_pc,if3_fire) 145 val if4_btb_target = RegEnable(if3_btb_target,if3_fire) 146 val if4_btb_taken = RegEnable(if3_btb_taken,if3_fire) 147 val if4_tage_target = bpu.io.tageOut.bits.target 148 val if4_tage_taken = bpu.io.tageOut.valid && bpu.io.tageOut.bits.redirect 149 val if4_tage_insMask = bpu.io.tageOut.bits.instrValid 150 XSDebug("[IF4]if4_valid:%d || if4_pc:0x%x \n",if4_valid,if4_pc) 151 //XSDebug("[IF4-TAGE-out]if4_tage_taken:%d || if4_btb_insMask:%b || if4_tage_target:0x%x \n",if4_tage_taken,if4_tage_insMask.asUInt,if4_tage_target) 152 XSDebug("[IF4-ICACHE-RESP]icacheResp.valid:%d icacheResp.ready:%d\n",io.icacheResp.valid,io.icacheResp.ready) 153 154 when(if4_valid && io.icacheResp.fire() && if4_tage_taken) 155 { 156 if1_npc := if4_tage_target 157 } 158 159 160 //redirect: miss predict 161 when(io.redirectInfo.flush()){ 162 if1_npc := io.redirectInfo.redirect.target 163 if3_valid := false.B 164 if4_valid := false.B 165 } 166 XSDebug(io.redirectInfo.flush(),"[IFU-REDIRECT] target:0x%x \n",io.redirectInfo.redirect.target.asUInt) 167 168 //Output -> iBuffer 169 //io.fetchPacket <> DontCare 170 if4_ready := io.fetchPacket.ready && (io.icacheResp.valid || !if4_valid) && (GTimer() > 500.U) 171 io.fetchPacket.valid := if4_valid && !io.redirectInfo.flush() 172 io.fetchPacket.bits.instrs := io.icacheResp.bits.icacheOut 173 io.fetchPacket.bits.mask := (Fill(FetchWidth*2, 1.U(1.W)) & Cat(if4_tage_insMask.map(m => Fill(2, m.asUInt))).asUInt) << if4_pc(2+log2Up(FetchWidth)-1, 1) 174 io.fetchPacket.bits.pc := if4_pc 175 176 XSDebug(io.fetchPacket.fire,"[IFU-Out-FetchPacket] starPC:0x%x GroupPC:0x%xn\n",if4_pc.asUInt,groupPC(if4_pc).asUInt) 177 XSDebug(io.fetchPacket.fire,"[IFU-Out-FetchPacket] instrmask %b\n",io.fetchPacket.bits.mask.asUInt) 178 for(i <- 0 until FetchWidth){ 179 //io.fetchPacket.bits.pnpc(i) := if1_npc 180 when (if4_tage_taken && i.U === OHToUInt(HighestBit(if4_tage_insMask.asUInt, FetchWidth))) { 181 io.fetchPacket.bits.pnpc(i) := if1_npc 182 }.otherwise { 183 io.fetchPacket.bits.pnpc(i) := if4_pc + (i + 1).U << 2.U // TODO: consider rvc 184 } 185 XSDebug(io.fetchPacket.fire,"[IFU-Out-FetchPacket] instruction %x pnpc:0x%x\n",io.fetchPacket.bits.instrs(i).asUInt,if1_npc.asUInt) 186 } 187 io.fetchPacket.bits.hist := bpu.io.tageOut.bits.hist 188 io.fetchPacket.bits.btbVictimWay := bpu.io.tageOut.bits.btbVictimWay 189 io.fetchPacket.bits.predCtr := bpu.io.tageOut.bits.predCtr 190 io.fetchPacket.bits.btbHitWay := bpu.io.tageOut.bits.btbHitWay 191 io.fetchPacket.bits.tageMeta := bpu.io.tageOut.bits.tageMeta 192 io.fetchPacket.bits.rasSp := bpu.io.tageOut.bits.rasSp 193 io.fetchPacket.bits.rasTopCtr := bpu.io.tageOut.bits.rasTopCtr 194 195 //to BPU 196 bpu.io.predecode.valid := io.icacheResp.fire() && if4_valid 197 bpu.io.predecode.bits <> io.icacheResp.bits.predecode 198 bpu.io.predecode.bits.mask := Fill(FetchWidth, 1.U(1.W)) << if4_pc(2+log2Up(FetchWidth)-1, 2) //TODO: consider RVC 199 200 io.icacheResp.ready := io.fetchPacket.ready && (GTimer() > 500.U) 201 202} 203 204