1package xiangshan.frontend 2 3import chisel3._ 4import chisel3.util._ 5import device.RAMHelper 6import xiangshan._ 7import utils._ 8 9trait HasIFUConst { this: XSModule => 10 val resetVector = 0x80000000L//TODO: set reset vec 11 val groupAlign = log2Up(FetchWidth * 4 * 2) 12 def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W)) 13 // each 1 bit in mask stands for 2 Bytes 14 def mask(pc: UInt): UInt = (Fill(PredictWidth * 2, 1.U(1.W)) >> pc(groupAlign - 1, 1))(PredictWidth - 1, 0) 15 def snpc(pc: UInt): UInt = pc + (PopCount(mask(pc)) << 1) 16} 17 18class IFUIO extends XSBundle 19{ 20 val fetchPacket = DecoupledIO(new FetchPacket) 21 val redirect = Flipped(ValidIO(new Redirect)) 22 val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 23 val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 24 val icacheReq = DecoupledIO(new FakeIcacheReq) 25 val icacheResp = Flipped(DecoupledIO(new FakeIcacheResp)) 26 val icacheFlush = Output(UInt(2.W)) 27} 28 29 30class IFU extends XSModule with HasIFUConst 31{ 32 val io = IO(new IFUIO) 33 val bpu = if (EnableBPD) Module(new BPU) else Module(new FakeBPU) 34 val pd = Module(new PreDecode) 35 36 val if2_redirect, if3_redirect, if4_redirect = WireInit(false.B) 37 val if1_flush, if2_flush, if3_flush, if4_flush = WireInit(false.B) 38 39 if4_flush := io.redirect.valid 40 if3_flush := if4_flush || if4_redirect 41 if2_flush := if3_flush || if3_redirect 42 if1_flush := if2_flush || if2_redirect 43 44 //********************** IF1 ****************************// 45 val if1_valid = !reset.asBool 46 val if1_npc = WireInit(0.U(VAddrBits.W)) 47 val if2_ready = WireInit(false.B) 48 val if1_fire = if1_valid && (if2_ready || if1_flush) && io.icacheReq.ready 49 50 val extHist = RegInit(Vec(ExtHistoryLength, 0.U(1.W))) 51 val headPtr = RegInit(0.U(log2Up(ExtHistoryLength).W)) 52 val updateHist = io.outOfOrderBrInfo.valid 53 val newPtr = Wire(UInt(log2Up(ExtHistoryLength).W)) 54 val ptr = Mux(updateHist, newPtr, headPtr) 55 when (updateHist) { headPtr := newPtr } 56 val hist = Wire(Vec(HistoryLength, UInt(1.W))) 57 for (i <- 0 until HistoryLength) { 58 hist(i) := extHist(ptr + i.U) 59 } 60 61 //********************** IF2 ****************************// 62 val if2_valid = RegEnable(next = if1_valid, init = false.B, enable = if1_fire) 63 val if3_ready = WireInit(false.B) 64 val if2_fire = if2_valid && if3_ready 65 val if2_pc = RegEnable(next = if1_npc, init = resetVector.U, enable = if1_fire) 66 val if2_snpc = snpc(if2_pc) 67 val if2_histPtr = RegEnable(ptr, if1_fire) 68 if2_ready := if2_fire || !if2_valid 69 when (if2_flush) { if2_valid := if1_fire } 70 71 when (RegNext(reset.asBool) && !reset.asBool) { 72 if1_npc := resetVector.U(VAddrBits.W) 73 }.elsewhen (if2_fire) { 74 if1_npc := if2_snpc 75 }.otherwise { 76 if1_npc := RegNext(if1_npc) 77 } 78 79 val if2_bp = bpu.io.out(0).bits 80 if2_redirect := if2_fire && bpu.io.out(0).valid && if2_bp.redirect && !if2_bp.saveHalfRVI 81 when (if2_redirect) { 82 if1_npc := if2_bp.target 83 } 84 85 //********************** IF3 ****************************// 86 val if3_valid = RegEnable(next = if2_valid, init = false.B, enable = if2_fire) 87 val if4_ready = WireInit(false.B) 88 val if3_fire = if3_valid && if4_ready && io.icacheResp.valid 89 val if3_pc = RegEnable(if2_pc, if2_fire) 90 val if3_histPtr = RegEnable(if2_histPtr, if2_fire) 91 if3_ready := if3_fire || !if3_valid 92 when (if3_flush) { if3_valid := false.B } 93 94 val if3_bp = bpu.io.out(1).bits 95 val prev_half_valid = RegInit(false.B) 96 val prev_half_redirect = RegInit(false.B) 97 val prev_half_fetchpc = Reg(UInt(VAddrBits.W)) 98 val prev_half_idx = Reg(UInt(log2Up(PredictWidth).W)) 99 val prev_half_tgt = Reg(UInt(VAddrBits.W)) 100 val prev_half_taken = RegInit(false.B) 101 val prev_half_instr = Reg(UInt(16.W)) 102 when (if3_flush) { 103 prev_half_valid := false.B 104 prev_half_redirect := false.B 105 }.elsewhen (if3_fire && if3_bp.saveHalfRVI) { 106 prev_half_valid := true.B 107 prev_half_redirect := if3_bp.redirect && bpu.io.out(1).valid 108 prev_half_fetchpc := if3_pc 109 val idx = Mux(if3_bp.redirect && bpu.io.out(1).valid, if3_bp.jmpIdx, PopCount(mask(if3_pc)) - 1.U) 110 prev_half_idx := idx 111 prev_half_tgt := if3_bp.target 112 prev_half_taken := if3_bp.taken 113 prev_half_instr := pd.io.out.instrs(idx)(15, 0) 114 }.elsewhen (if3_fire) { 115 prev_half_valid := false.B 116 prev_half_redirect := false.B 117 } 118 119 // if3_redirect := if3_fire && (prev_half_valid && prev_half_taken || bpu.io.out(1).valid && if3_bp.redirect && !if3_bp.saveHalfRVI) 120 // when (if3_redirect) { 121 // if1_npc := Mux(prev_half_valid && prev_half_redirect, prev_half_tgt, if3_bp.target) 122 // } 123 124 when (bpu.io.out(1).valid && if3_fire) { 125 when (prev_half_valid && prev_half_taken) { 126 if3_redirect := true.B 127 if1_npc := prev_half_tgt 128 }.elsewhen (if3_bp.redirect && !if3_bp.saveHalfRVI) { 129 if3_redirect := true.B 130 if1_npc := if3_bp.target 131 }.elsewhen (if3_bp.saveHalfRVI) { 132 if3_redirect := true.B 133 if1_npc := snpc(if3_pc) 134 }.otherwise { 135 if3_redirect := false.B 136 } 137 }.otherwise { 138 if3_redirect := false.B 139 } 140 141 //********************** IF4 ****************************// 142 val if4_pd = RegEnable(pd.io.out, if3_fire) 143 // val if4_icacheResp = RegEnable(io.icacheResp.bits, if3_fire) 144 val if4_valid = RegEnable(next = if3_valid, init = false.B, enable = if3_fire) 145 val if4_fire = if4_valid && io.fetchPacket.ready 146 val if4_pc = RegEnable(if3_pc, if3_fire) 147 val if4_histPtr = RegEnable(if3_histPtr, if3_fire) 148 if4_ready := if4_fire || !if4_valid 149 when (if4_flush) { if4_valid := false.B } 150 151 val if4_bp = bpu.io.out(2).bits 152 153 when (bpu.io.out(2).valid && if4_fire && if4_pd.redirect) { 154 when (!if4_bp.saveHalfRVI) { 155 if4_redirect := true.B 156 if1_npc := if4_bp.target 157 }.otherwise { 158 if4_redirect := true.B 159 if1_npc := snpc(if4_pc) 160 161 prev_half_valid := true.B 162 prev_half_redirect := true.B 163 prev_half_fetchpc := if4_pc 164 val idx = PopCount(mask(if4_pc)) - 1.U 165 prev_half_idx := idx 166 prev_half_tgt := if4_bp.target 167 prev_half_taken := if4_bp.taken 168 prev_half_instr := if4_pd.io.out.instrs(idx)(15, 0) 169 } 170 }.otherwise { 171 if4_redirect := false.B 172 } 173 174 175 176 177 178 io.icacheReq.valid := if1_valid && if2_ready 179 io.icacheReq.bits.addr := if1_npc 180 io.icacheResp.ready := if3_valid && if4_ready 181 io.icacheFlush := Cat(if3_flush, if2_flush) 182 183 bpu.io.inOrderBrInfo <> io.inOrderBrInfo 184 bpu.io.flush := Cat(if4_flush, if3_flush, if2_flush) 185 bpu.io.in.valid := if1_fire 186 bpu.io.in.bits.pc := if1_npc 187 bpu.io.in.bits.hist := hist.asUInt 188 bpu.io.in.bits.inMask := mask(if1_npc) 189 bpu.io.out(0).ready := if2_fire 190 bpu.io.out(1).ready := if3_fire 191 bpu.io.out(2).ready := if4_fire 192 bpu.io.predecode.valid := if4_valid 193 bpu.io.predecode.bits.mask := if4_pd.mask 194 bpu.io.predecode.bits.pd := if4_pd.pd 195 bpu.io.branchInfo.ready := if4_fire 196 197 pd.io.in := io.icacheResp.bits 198 pd.io.prev.valid := prev_half_valid 199 pd.io.prev.bits := prev_half_instr 200 201 io.fetchPacket.valid := if4_valid && !io.redirect.valid 202 io.fetchPacket.bits.instrs := if4_pd.instrs 203 io.fetchPacket.bits.mask := if4_pd.mask & (Fill(PredictWidth, !if4_bp.taken) | (Fill(PredictWidth, 1.U(1.W)) >> (~if4_bp.jmpIdx))) 204 io.fetchPacket.bits.pc := if4_pd.pc 205 (0 until PredictWidth).foreach(i => io.fetchPacket.bits.pnpc(i) := if4_pd.pc(i) + Mux(if4_pd.pd(i).isRVC, 2.U, 4.U)) 206 when (if4_bp.taken) { 207 io.fetchPacket.bits.pnpc(if4_bp.jmpIdx) := if4_bp.target 208 } 209 io.fetchPacket.bits.brInfo := bpu.io.branchInfo.bits 210 (0 until PredictWidth).foreach(i => io.fetchPacket.bits.brInfo(i).histPtr := if4_histPtr) 211 io.fetchPacket.bits.pd := if4_pd.pd 212}