1 package xiangshan.frontend 2 3import chisel3._ 4import chisel3.util._ 5import device.RAMHelper 6import xiangshan._ 7import utils._ 8 9trait HasIFUConst { this: XSModule => 10 val resetVector = 0x80000000L//TODO: set reset vec 11 val groupAlign = log2Up(FetchWidth * 4) 12 def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W)) 13 def snpc(pc: UInt): UInt = pc + (1 << groupAlign).U 14 15} 16 17class IFUIO extends XSBundle 18{ 19 val fetchPacket = DecoupledIO(new FetchPacket) 20 val redirectInfo = Input(new RedirectInfo) 21 val icacheReq = DecoupledIO(new FakeIcacheReq) 22 val icacheResp = Flipped(DecoupledIO(new FakeIcacheResp)) 23} 24 25class FakeBPU extends XSModule{ 26 val io = IO(new Bundle() { 27 val redirectInfo = Input(new RedirectInfo) 28 val in = new Bundle { val pc = Flipped(Valid(UInt(VAddrBits.W))) } 29 val btbOut = ValidIO(new BranchPrediction) 30 val tageOut = ValidIO(new BranchPrediction) 31 val predecode = Flipped(ValidIO(new Predecode)) 32 }) 33 34 io.btbOut.valid := true.B 35 io.btbOut.bits <> DontCare 36 io.btbOut.bits.redirect := GTimer() === 1.U 37 io.btbOut.bits.target := "h080001234".U 38 io.tageOut.valid := false.B 39 io.tageOut.bits <> DontCare 40} 41 42 43class IFU extends XSModule with HasIFUConst 44{ 45 val io = IO(new IFUIO) 46 val bpu = if(EnableBPU) Module(new BPU) else Module(new FakeBPU) 47 48 //------------------------- 49 // IF1 PC update 50 //------------------------- 51 //local 52 val if1_npc = WireInit(0.U(VAddrBits.W)) 53 val if1_valid = !reset.asBool 54 val if1_pc = RegInit(resetVector.U(VAddrBits.W)) 55 //next 56 val if2_ready = WireInit(false.B) 57 val if2_snpc = snpc(if1_pc) //TODO: calculate snpc according to mask of current fetch packet 58 val needflush = WireInit(false.B) 59 // when an RVI instruction is predicted as taken and it crosses over two fetch packets, 60 // IFU should not take this branch but fetch the latter half of the instruction sequentially, 61 // and take the jump target in the next fetch cycle 62 val if2_lateJumpLatch = WireInit(false.B) 63 val if2_lateJumpTarget = RegInit(0.U(VAddrBits.W)) 64 val if4_lateJumpLatch = WireInit(false.B) 65 val if4_lateJumpTarget = RegInit(0.U(VAddrBits.W)) 66 67 //pipe fire 68 val if1_fire = if1_valid && if2_ready 69 val if1_pcUpdate = if1_fire || needflush 70 71 when(RegNext(reset.asBool) && !reset.asBool){ 72 //when((GTimer() === 501.U)){ //TODO:this is ugly 73 XSDebug("RESET....\n") 74 if1_npc := resetVector.U(VAddrBits.W) 75 } .otherwise{ 76 if1_npc := Mux(if4_lateJumpLatch, if4_lateJumpTarget, Mux(if2_lateJumpLatch, if2_lateJumpTarget, if2_snpc)) 77 } 78 79 when(if1_pcUpdate) 80 { 81 if1_pc := if1_npc 82 } 83 84 bpu.io.in.pc.valid := if1_fire 85 bpu.io.in.pc.bits := if1_npc 86 bpu.io.redirectInfo := io.redirectInfo 87 88 XSDebug("[IF1]if1_valid:%d || if1_npc:0x%x || if1_pcUpdate:%d if1_pc:0x%x || if2_ready:%d",if1_valid,if1_npc,if1_pcUpdate,if1_pc,if2_ready) 89 XSDebug(false,if1_fire,"------IF1->fire!!!") 90 XSDebug(false,true.B,"\n") 91 92 //------------------------- 93 // IF2 btb response 94 // icache visit 95 //------------------------- 96 //local 97 val if2_valid = RegEnable(next=if1_valid,init=false.B,enable=if1_fire) 98 val if2_pc = if1_pc 99 val if2_btb_taken = bpu.io.btbOut.valid && bpu.io.btbOut.bits.redirect 100 val if2_btb_lateJump = WireInit(false.B) 101 val if2_btb_insMask = Mux(if2_btb_taken, bpu.io.btbOut.bits.instrValid.asUInt, Fill(FetchWidth*2, 1.U(1.W))) // TODO: FIX THIS 102 val if2_btb_target = Mux(if2_btb_lateJump, if2_snpc, bpu.io.btbOut.bits.target) 103 104 if2_lateJumpLatch := BoolStopWatch(if2_btb_lateJump, if1_fire, startHighPriority = true) 105 // since late jump target should be taken after the latter half of late jump instr is fetched, we need to latch this target 106 when (if2_btb_lateJump) { 107 if2_lateJumpTarget := bpu.io.btbOut.bits.target 108 } 109 110 //next 111 val if3_ready = WireInit(false.B) 112 113 //pipe fire 114 val if2_fire = if2_valid && if3_ready && io.icacheReq.fire() 115 if2_ready := (if2_fire) || !if2_valid 116 117 io.icacheReq.valid := if2_valid 118 io.icacheReq.bits.addr := if2_pc 119 120 when(if2_valid && if2_btb_taken) 121 { 122 if1_npc := if2_btb_target 123 } 124 125 bpu.io.in.pc.valid := if1_fire && !if2_btb_lateJump 126 127 XSDebug("[IF2]if2_valid:%d || if2_pc:0x%x || if3_ready:%d ",if2_valid,if2_pc,if3_ready) 128 XSDebug(false,if2_fire,"------IF2->fire!!!") 129 XSDebug(false,true.B,"\n") 130 XSDebug("[IF2-Icache-Req] icache_in_valid:%d icache_in_ready:%d\n",io.icacheReq.valid,io.icacheReq.ready) 131 XSDebug("[IF2-BPU-out]if2_btbTaken:%d || if2_btb_insMask:%b || if2_btb_target:0x%x \n",if2_btb_taken,if2_btb_insMask.asUInt,if2_btb_target) 132 //------------------------- 133 // IF3 icache hit check 134 //------------------------- 135 //local 136 val if3_valid = RegEnable(next=if2_valid,init=false.B,enable=if2_fire) 137 val if3_pc = RegEnable(if2_pc,if2_fire) 138 val if3_npc = RegEnable(if1_npc, if2_fire) 139 val if3_btb_target = RegEnable(Mux(if2_lateJumpLatch, if2_lateJumpTarget, Mux(if2_btb_lateJump, bpu.io.btbOut.bits.target, if2_btb_target)), if2_fire) 140 val if3_btb_taken = RegEnable(Mux(if2_lateJumpLatch, true.B, if2_btb_taken), if2_fire) 141 val if3_btb_insMask = RegEnable(Mux(if2_lateJumpLatch, 1.U((FetchWidth*2).W), if2_btb_insMask), if2_fire) 142 143 //next 144 val if4_ready = WireInit(false.B) 145 146 //pipe fire 147 val if3_fire = if3_valid && if4_ready 148 if3_ready := if3_fire || !if3_valid 149 150 151 XSDebug("[IF3]if3_valid:%d || if3_pc:0x%x if3_npc:0x%x || if4_ready:%d ",if3_valid,if3_pc,if3_npc,if4_ready) 152 XSDebug(false,if3_fire,"------IF3->fire!!!") 153 XSDebug(false,true.B,"\n") 154 155 //------------------------- 156 // IF4 icache response 157 // RAS result 158 // taget generate 159 //------------------------- 160 val if4_valid = RegEnable(next=if3_valid,init=false.B,enable=if3_fire) 161 val if4_pc = RegEnable(if3_pc,if3_fire) 162 val if4_npc = RegEnable(if3_npc,if3_fire) 163 val if4_btb_target = RegEnable(if3_btb_target,if3_fire) 164 val if4_btb_taken = RegEnable(if3_btb_taken,if3_fire) 165 val if4_btb_insMask = RegEnable(if3_btb_insMask, if3_fire) 166 val if4_tage_taken = bpu.io.tageOut.valid && bpu.io.tageOut.bits.redirect 167 val if4_tage_lateJump = if4_tage_taken && bpu.io.tageOut.bits.lateJump && !io.redirectInfo.flush() 168 val if4_tage_insMask = bpu.io.tageOut.bits.instrValid 169 val if4_snpc = if4_pc + (PopCount(if4_tage_insMask) << 1.U) 170 val if4_tage_target = Mux(if4_tage_lateJump, if4_snpc, bpu.io.tageOut.bits.target) 171 172 if2_btb_lateJump := if2_btb_taken && bpu.io.btbOut.bits.lateJump && !io.redirectInfo.flush() && !if4_tage_taken 173 174 if4_lateJumpLatch := BoolStopWatch(if4_tage_lateJump, if1_fire, startHighPriority = true) 175 when (if4_tage_lateJump) { 176 if4_lateJumpTarget := bpu.io.tageOut.bits.target 177 } 178 179 bpu.io.in.pc.valid := if1_fire && !if2_btb_lateJump && !if4_tage_lateJump 180 181 XSDebug("[IF4]if4_valid:%d || if4_pc:0x%x if4_npc:0x%x\n",if4_valid,if4_pc,if4_npc) 182 XSDebug("[IF4-TAGE-out]if4_tage_taken:%d || if4_btb_insMask:%b || if4_tage_target:0x%x \n",if4_tage_taken,if4_tage_insMask.asUInt,if4_tage_target) 183 XSDebug("[IF4-ICACHE-RESP]icacheResp.valid:%d icacheResp.ready:%d\n",io.icacheResp.valid,io.icacheResp.ready) 184 185 when(io.icacheResp.fire() && if4_tage_taken &&if4_valid) 186 { 187 if1_npc := if4_tage_target 188 } 189 190 //redirect: miss predict 191 when(io.redirectInfo.flush()){ 192 if1_npc := io.redirectInfo.redirect.target 193 } 194 XSDebug(io.redirectInfo.flush(),"[IFU-REDIRECT] target:0x%x \n",io.redirectInfo.redirect.target.asUInt) 195 196 197 //flush pipline 198 // if(EnableBPD){needflush := (if4_valid && if4_tage_taken) || io.redirectInfo.flush() } 199 // else {needflush := io.redirectInfo.flush()} 200 needflush := (if4_valid && if4_tage_taken) || io.redirectInfo.flush() 201 when(needflush){ 202 if3_valid := false.B 203 if4_valid := false.B 204 } 205 //flush ICache 206 io.icacheReq.bits.flush := needflush 207 208 //Output -> iBuffer 209 //io.fetchPacket <> DontCare 210 if4_ready := io.fetchPacket.ready && (io.icacheResp.valid || !if4_valid) && (GTimer() > 500.U) 211 io.fetchPacket.valid := if4_valid && !io.redirectInfo.flush() 212 io.fetchPacket.bits.instrs := io.icacheResp.bits.icacheOut 213 /* 214 if(EnableBPU){ 215 io.fetchPacket.bits.mask := Mux(if4_tage_taken, Fill(FetchWidth*2, 1.U(1.W)) & if4_tage_insMask.asUInt, 216 Mux(if4_btb_taken, Fill(FetchWidth*2, 1.U(1.W)) & if4_btb_insMask.asUInt, 217 Fill(FetchWidth*2, 1.U(1.W))) 218 ) 219 } 220 else{ 221 io.fetchPacket.bits.mask := Fill(FetchWidth*2, 1.U(1.W)) //TODO : consider cross cacheline fetch 222 } 223 */ 224 io.fetchPacket.bits.mask := Mux(if4_lateJumpLatch, 1.U((FetchWidth*2).W), 225 Mux(if4_tage_taken, Fill(FetchWidth*2, 1.U(1.W)) & if4_tage_insMask.asUInt, 226 Fill(FetchWidth*2, 1.U(1.W)) & if4_btb_insMask.asUInt)) 227 io.fetchPacket.bits.pc := if4_pc 228 229 XSDebug(io.fetchPacket.fire,"[IFU-Out-FetchPacket] starPC:0x%x GroupPC:0x%xn\n",if4_pc.asUInt,groupPC(if4_pc).asUInt) 230 XSDebug(io.fetchPacket.fire,"[IFU-Out-FetchPacket] instrmask %b\n",io.fetchPacket.bits.mask.asUInt) 231 for(i <- 0 until (FetchWidth*2)){ 232 when (if4_btb_taken && !if4_tage_taken && i.U === OHToUInt(HighestBit(if4_btb_insMask.asUInt, FetchWidth*2))) { 233 io.fetchPacket.bits.pnpc(i) := if4_btb_target 234 }.elsewhen (if4_tage_taken && i.U === OHToUInt(HighestBit(if4_tage_insMask.asUInt, FetchWidth*2))) { 235 io.fetchPacket.bits.pnpc(i) := Mux(if4_tage_lateJump, bpu.io.tageOut.bits.target, if4_tage_target) 236 }.otherwise { 237 io.fetchPacket.bits.pnpc(i) := if4_pc + ((i + 1).U << Mux(io.icacheResp.bits.predecode.isRVC(i), 1.U, 2.U)) 238 } 239 XSDebug(io.fetchPacket.fire,"[IFU-Out-FetchPacket] instruction %x pnpc:0x%x\n", 240 Mux((i.U)(0), io.fetchPacket.bits.instrs(i>>1)(31,16), io.fetchPacket.bits.instrs(i>>1)(15,0)), 241 io.fetchPacket.bits.pnpc(i)) 242 } 243 io.fetchPacket.bits.hist := bpu.io.tageOut.bits.hist 244 // io.fetchPacket.bits.btbVictimWay := bpu.io.tageOut.bits.btbVictimWay 245 io.fetchPacket.bits.predCtr := bpu.io.tageOut.bits.predCtr 246 io.fetchPacket.bits.btbHit := bpu.io.tageOut.bits.btbHit 247 io.fetchPacket.bits.tageMeta := bpu.io.tageOut.bits.tageMeta 248 io.fetchPacket.bits.rasSp := bpu.io.tageOut.bits.rasSp 249 io.fetchPacket.bits.rasTopCtr := bpu.io.tageOut.bits.rasTopCtr 250 251 //to BPU 252 bpu.io.predecode.valid := io.icacheResp.fire() && if4_valid 253 bpu.io.predecode.bits <> io.icacheResp.bits.predecode 254 //TODO: consider RVC && consider cross cacheline fetch 255 bpu.io.predecode.bits.mask := Fill(FetchWidth, 1.U(1.W)) 256 bpu.io.predecode.bits.isRVC := 0.U.asTypeOf(Vec(FetchWidth*2, Bool())) 257 bpu.io.redirectInfo := io.redirectInfo 258 io.icacheResp.ready := io.fetchPacket.ready && (GTimer() > 500.U) 259 260} 261 262