1package xiangshan.frontend 2 3import chisel3._ 4import chisel3.util._ 5import chisel3.util.experimental.BoringUtils 6import device.RAMHelper 7import xiangshan._ 8import utils._ 9import xiangshan.cache._ 10 11trait HasIFUConst { this: XSModule => 12 val resetVector = 0x80000000L//TODO: set reset vec 13 val groupAlign = log2Up(FetchWidth * 4 * 2) 14 def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W)) 15 // each 1 bit in mask stands for 2 Bytes 16 def mask(pc: UInt): UInt = (Fill(PredictWidth * 2, 1.U(1.W)) >> pc(groupAlign - 1, 1))(PredictWidth - 1, 0) 17 def snpc(pc: UInt): UInt = pc + (PopCount(mask(pc)) << 1) 18} 19 20class IFUIO extends XSBundle 21{ 22 val fetchPacket = DecoupledIO(new FetchPacket) 23 val redirect = Flipped(ValidIO(new Redirect)) 24 val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 25 val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 26 val icacheReq = DecoupledIO(new ICacheReq) 27 val icacheResp = Flipped(DecoupledIO(new ICacheResp)) 28 val icacheFlush = Output(UInt(2.W)) 29 val LBFetch = Flipped(new IFUFetchIO) 30 val LBredirect = Flipped(ValidIO(UInt(VAddrBits.W))) 31 val tgtpc = Output(UInt(VAddrBits.W)) 32 val inLoop = Input(Bool()) 33} 34 35class IFU extends XSModule with HasIFUConst 36{ 37 val io = IO(new IFUIO) 38 val bpu = BPU(EnableBPU) 39 val pd = Module(new PreDecode) 40 41 val if2_redirect, if3_redirect, if4_redirect = WireInit(false.B) 42 val if1_flush, if2_flush, if3_flush, if4_flush = WireInit(false.B) 43 44 val icacheResp = WireInit(Mux(io.inLoop, io.LBFetch.LBResp, io.icacheResp.bits)) 45 46 if4_flush := io.redirect.valid || io.LBredirect.valid 47 if3_flush := if4_flush || if4_redirect 48 if2_flush := if3_flush || if3_redirect 49 if1_flush := if2_flush || if2_redirect 50 51 //********************** IF1 ****************************// 52 val if1_valid = !reset.asBool && GTimer() > 500.U 53 val if1_npc = WireInit(0.U(VAddrBits.W)) 54 val if2_ready = WireInit(false.B) 55 val if1_fire = if1_valid && (if2_ready || if1_flush) && (io.inLoop || io.icacheReq.ready) 56 57 // val extHist = VecInit(Fill(ExtHistoryLength, RegInit(0.U(1.W)))) 58 val extHist = RegInit(VecInit(Seq.fill(ExtHistoryLength)(0.U(1.W)))) 59 val headPtr = RegInit(0.U(log2Up(ExtHistoryLength).W)) 60 val shiftPtr = WireInit(false.B) 61 val newPtr = Wire(UInt(log2Up(ExtHistoryLength).W)) 62 val ptr = Mux(shiftPtr, newPtr, headPtr) 63 when (shiftPtr) { headPtr := newPtr } 64 val hist = Wire(Vec(HistoryLength, UInt(1.W))) 65 for (i <- 0 until HistoryLength) { 66 hist(i) := extHist(ptr + i.U) 67 } 68 69 newPtr := headPtr 70 shiftPtr := false.B 71 72 //********************** IF2 ****************************// 73 val if2_valid = RegEnable(next = if1_valid, init = false.B, enable = if1_fire) 74 val if3_ready = WireInit(false.B) 75 val if2_fire = if2_valid && if3_ready && !if2_flush 76 val if2_pc = RegEnable(next = if1_npc, init = resetVector.U, enable = if1_fire) 77 val if2_snpc = snpc(if2_pc) 78 val if2_histPtr = RegEnable(ptr, if1_fire) 79 if2_ready := if2_fire || !if2_valid || if2_flush 80 when (if2_flush) { if2_valid := if1_fire } 81 .elsewhen (if1_fire) { if2_valid := if1_valid } 82 .elsewhen (if2_fire) { if2_valid := false.B } 83 84 when (RegNext(reset.asBool) && !reset.asBool) { 85 if1_npc := resetVector.U(VAddrBits.W) 86 }.elsewhen (if2_fire) { 87 if1_npc := if2_snpc 88 }.otherwise { 89 if1_npc := RegNext(if1_npc) 90 } 91 92 val if2_bp = bpu.io.out(0).bits 93 if2_redirect := if2_fire && bpu.io.out(0).valid && if2_bp.redirect// && !if2_bp.saveHalfRVI 94 when (if2_redirect) { 95 if1_npc := if2_bp.target 96 } 97 98 when (if2_fire && (if2_bp.taken || if2_bp.hasNotTakenBrs)) { 99 shiftPtr := true.B 100 newPtr := headPtr - 1.U 101 hist(0) := if2_bp.taken.asUInt 102 extHist(newPtr) := if2_bp.taken.asUInt 103 } 104 105 //********************** IF3 ****************************// 106 val if3_valid = RegEnable(next = if2_valid, init = false.B, enable = if2_fire) 107 val if4_ready = WireInit(false.B) 108 val if3_fire = if3_valid && if4_ready && (io.inLoop || io.icacheResp.valid) && !if3_flush 109 val if3_pc = RegEnable(if2_pc, if2_fire) 110 val if3_histPtr = RegEnable(if2_histPtr, if2_fire) 111 if3_ready := if3_fire || !if3_valid || if3_flush 112 when (if3_flush) { if3_valid := false.B } 113 .elsewhen (if2_fire) { if3_valid := if2_valid } 114 .elsewhen (if3_fire) { if3_valid := false.B } 115 116 val if3_bp = bpu.io.out(1).bits 117 118 class PrevHalfInstr extends Bundle { 119 val valid = Bool() 120 val taken = Bool() 121 val fetchpc = UInt(VAddrBits.W) // only for debug 122 val idx = UInt(VAddrBits.W) // only for debug 123 val pc = UInt(VAddrBits.W) 124 val target = UInt(VAddrBits.W) 125 val instr = UInt(16.W) 126 val ipf = Bool() 127 } 128 129 val if3_prevHalfInstr = RegInit(0.U.asTypeOf(new PrevHalfInstr)) 130 val if4_prevHalfInstr = Wire(new PrevHalfInstr) 131 // 32-bit instr crosses 2 pages, and the higher 16-bit triggers page fault 132 val crossPageIPF = WireInit(false.B) 133 when (if4_prevHalfInstr.valid) { 134 if3_prevHalfInstr := if4_prevHalfInstr 135 } 136 val prevHalfInstr = Mux(if4_prevHalfInstr.valid, if4_prevHalfInstr, if3_prevHalfInstr) 137 138 val if3_hasPrevHalfInstr = prevHalfInstr.valid && (prevHalfInstr.pc + 2.U) === if3_pc 139 if3_redirect := if3_fire && bpu.io.out(1).valid && (if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.redirect/* && !if3_bp.saveHalfRVI*/ ) 140 when (if3_redirect) { 141 if1_npc := Mux(if3_hasPrevHalfInstr && prevHalfInstr.taken, prevHalfInstr.target, if3_bp.target) 142 } 143 144 when (if3_fire && if3_redirect) { 145 shiftPtr := true.B 146 newPtr := Mux(if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.taken || if3_bp.hasNotTakenBrs, if3_histPtr - 1.U, if3_histPtr) 147 hist(0) := Mux(if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.taken || if3_bp.hasNotTakenBrs, 148 (if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.taken).asUInt, 149 extHist(if3_histPtr)) 150 extHist(newPtr) := Mux(if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.taken || if3_bp.hasNotTakenBrs, 151 (if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.taken).asUInt, 152 extHist(if3_histPtr)) 153 } 154 155 156 //********************** IF4 ****************************// 157 val if4_pd = RegEnable(pd.io.out, if3_fire) 158 val if4_ipf = RegEnable(icacheResp.ipf || if3_hasPrevHalfInstr && prevHalfInstr.ipf, if3_fire) 159 val if4_crossPageIPF = RegEnable(crossPageIPF, if3_fire) 160 val if4_valid = RegInit(false.B) 161 val if4_fire = if4_valid && io.fetchPacket.ready 162 val if4_pc = RegEnable(if3_pc, if3_fire) 163 val if4_histPtr = RegEnable(if3_histPtr, if3_fire) 164 if4_ready := (if4_fire || !if4_valid || if4_flush) && GTimer() > 500.U 165 when (if4_flush) { if4_valid := false.B } 166 .elsewhen (if3_fire) { if4_valid := if3_valid } 167 .elsewhen(if4_fire) { if4_valid := false.B } 168 169 val if4_bp = Wire(new BranchPrediction) 170 if4_bp := bpu.io.out(2).bits 171 172 val if4_cfi_jal = if4_pd.instrs(if4_bp.jmpIdx) 173 val if4_cfi_jal_tgt = if4_pd.pc(if4_bp.jmpIdx) + Mux(if4_pd.pd(if4_bp.jmpIdx).isRVC, 174 SignExt(Cat(if4_cfi_jal(12), if4_cfi_jal(8), if4_cfi_jal(10, 9), if4_cfi_jal(6), if4_cfi_jal(7), if4_cfi_jal(2), if4_cfi_jal(11), if4_cfi_jal(5, 3), 0.U(1.W)), XLEN), 175 SignExt(Cat(if4_cfi_jal(31), if4_cfi_jal(19, 12), if4_cfi_jal(20), if4_cfi_jal(30, 21), 0.U(1.W)), XLEN)) 176 if4_bp.target := Mux(if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken, if4_cfi_jal_tgt, bpu.io.out(2).bits.target) 177 if4_bp.redirect := bpu.io.out(2).bits.redirect || if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken && if4_cfi_jal_tgt =/= bpu.io.out(2).bits.target 178 179 if4_prevHalfInstr := 0.U.asTypeOf(new PrevHalfInstr) 180 when (bpu.io.out(2).valid && if4_fire && if4_bp.saveHalfRVI) { 181 if4_prevHalfInstr.valid := true.B 182 if4_prevHalfInstr.taken := if4_bp.taken 183 if4_prevHalfInstr.fetchpc := if4_pc 184 if4_prevHalfInstr.idx := PopCount(mask(if4_pc)) - 1.U 185 if4_prevHalfInstr.pc := if4_pd.pc(if4_prevHalfInstr.idx) 186 if4_prevHalfInstr.target := if4_bp.target 187 if4_prevHalfInstr.instr := if4_pd.instrs(if4_prevHalfInstr.idx)(15, 0) 188 if4_prevHalfInstr.ipf := if4_ipf 189 } 190 191 when (bpu.io.out(2).valid && if4_fire && if4_bp.redirect) { 192 if4_redirect := true.B 193 shiftPtr := true.B 194 newPtr := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_histPtr - 1.U, if4_histPtr) 195 hist(0) := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_bp.taken.asUInt, extHist(if4_histPtr)) 196 extHist(newPtr) := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_bp.taken.asUInt, extHist(if4_histPtr)) 197 when (if4_bp.saveHalfRVI) { 198 if1_npc := snpc(if4_pc) 199 }.otherwise { 200 if1_npc := if4_bp.target 201 } 202 }.elsewhen (bpu.io.out(2).valid && if4_fire/* && !if4_bp.redirect*/) { 203 when (if4_bp.saveHalfRVI && if4_bp.taken) { 204 if4_redirect := true.B 205 if1_npc := snpc(if4_pc) 206 shiftPtr := true.B 207 newPtr := if4_histPtr - 1.U 208 hist(0) := 1.U 209 extHist(newPtr) := 1.U 210 }.otherwise { 211 if4_redirect := false.B 212 } 213 }.otherwise { 214 if4_redirect := false.B 215 } 216 217 218 when (io.outOfOrderBrInfo.valid && io.outOfOrderBrInfo.bits.isMisPred) { 219 shiftPtr := true.B 220 newPtr := io.outOfOrderBrInfo.bits.brInfo.histPtr - 1.U 221 hist(0) := io.outOfOrderBrInfo.bits.taken 222 extHist(newPtr) := io.outOfOrderBrInfo.bits.taken 223 } 224 225 when (io.LBredirect.valid) { 226 if1_npc := io.LBredirect.bits 227 } 228 229 when (io.redirect.valid) { 230 if1_npc := io.redirect.bits.target 231 } 232 233 when(io.inLoop) { 234 io.icacheReq.valid := if4_flush 235 io.icacheResp.ready := false.B 236 }.otherwise { 237 io.icacheReq.valid := if1_valid && if2_ready 238 // io.icacheResp.ready := if3_ready 239 io.icacheResp.ready := if4_ready 240 //io.icacheResp.ready := if3_valid 241 } 242 io.icacheReq.bits.addr := if1_npc 243 244 // when(if4_bp.taken) { 245 // when(if4_bp.saveHalfRVI) { 246 // io.LBFetch.LBReq := snpc(if4_pc) 247 // }.otherwise { 248 // io.LBFetch.LBReq := if4_bp.target 249 // } 250 // }.otherwise { 251 // io.LBFetch.LBReq := snpc(if4_pc) 252 // XSDebug(p"snpc(if4_pc)=${Hexadecimal(snpc(if4_pc))}\n") 253 // } 254 io.LBFetch.LBReq := if3_pc 255 io.tgtpc := if4_bp.target 256 257 io.icacheReq.bits.mask := mask(if1_npc) 258 259 io.icacheFlush := Cat(if3_flush, if2_flush) 260 261 val inOrderBrHist = Wire(Vec(HistoryLength, UInt(1.W))) 262 (0 until HistoryLength).foreach(i => inOrderBrHist(i) := extHist(i.U + io.inOrderBrInfo.bits.brInfo.histPtr)) 263 bpu.io.inOrderBrInfo.valid := io.inOrderBrInfo.valid 264 bpu.io.inOrderBrInfo.bits := BranchUpdateInfoWithHist(io.inOrderBrInfo.bits, inOrderBrHist.asUInt) 265 bpu.io.outOfOrderBrInfo.valid := io.outOfOrderBrInfo.valid 266 bpu.io.outOfOrderBrInfo.bits := BranchUpdateInfoWithHist(io.outOfOrderBrInfo.bits, inOrderBrHist.asUInt) // Dont care about hist 267 268 // bpu.io.flush := Cat(if4_flush, if3_flush, if2_flush) 269 bpu.io.flush := VecInit(if2_flush, if3_flush, if4_flush) 270 bpu.io.cacheValid := (io.inLoop || io.icacheResp.valid) 271 bpu.io.in.valid := if1_fire 272 bpu.io.in.bits.pc := if1_npc 273 bpu.io.in.bits.hist := hist.asUInt 274 bpu.io.in.bits.inMask := mask(if1_npc) 275 bpu.io.out(0).ready := if2_fire 276 bpu.io.out(1).ready := if3_fire 277 bpu.io.out(2).ready := if4_fire 278 bpu.io.predecode.valid := if4_valid 279 bpu.io.predecode.bits.mask := if4_pd.mask 280 bpu.io.predecode.bits.pd := if4_pd.pd 281 bpu.io.predecode.bits.isFetchpcEqualFirstpc := if4_pc === if4_pd.pc(0) 282 bpu.io.branchInfo.ready := if4_fire 283 284 when(io.inLoop) { 285 pd.io.in := io.LBFetch.LBResp 286 pd.io.in.mask := io.LBFetch.LBResp.mask & mask(io.LBFetch.LBResp.pc) 287 XSDebug("Fetch from LB\n") 288 XSDebug(p"pc=${Hexadecimal(io.LBFetch.LBResp.pc)}\n") 289 XSDebug(p"data=${Hexadecimal(io.LBFetch.LBResp.data)}\n") 290 XSDebug(p"mask=${Hexadecimal(io.LBFetch.LBResp.mask)}\n") 291 }.otherwise { 292 pd.io.in := icacheResp 293 } 294 pd.io.prev.valid := if3_hasPrevHalfInstr 295 pd.io.prev.bits := prevHalfInstr.instr 296 // if a fetch packet triggers page fault, set the pf instruction to nop 297 when (!if3_hasPrevHalfInstr && icacheResp.ipf) { 298 val instrs = Wire(Vec(FetchWidth, UInt(32.W))) 299 (0 until FetchWidth).foreach(i => instrs(i) := ZeroExt("b0010011".U, 32)) // nop 300 pd.io.in.data := instrs.asUInt 301 }.elsewhen (if3_hasPrevHalfInstr && (prevHalfInstr.ipf || icacheResp.ipf)) { 302 pd.io.prev.bits := ZeroExt("b0010011".U, 16) 303 val instrs = Wire(Vec(FetchWidth, UInt(32.W))) 304 (0 until FetchWidth).foreach(i => instrs(i) := Cat(ZeroExt("b0010011".U, 16), Fill(16, 0.U(1.W)))) 305 pd.io.in.data := instrs.asUInt 306 307 when (icacheResp.ipf && !prevHalfInstr.ipf) { crossPageIPF := true.B } // higher 16 bits page fault 308 } 309 310 io.fetchPacket.valid := if4_valid && !io.redirect.valid 311 io.fetchPacket.bits.instrs := if4_pd.instrs 312 io.fetchPacket.bits.mask := if4_pd.mask & (Fill(PredictWidth, !if4_bp.taken) | (Fill(PredictWidth, 1.U(1.W)) >> (~if4_bp.jmpIdx))) 313 io.fetchPacket.bits.pc := if4_pd.pc 314 (0 until PredictWidth).foreach(i => io.fetchPacket.bits.pnpc(i) := if4_pd.pc(i) + Mux(if4_pd.pd(i).isRVC, 2.U, 4.U)) 315 when (if4_bp.taken) { 316 io.fetchPacket.bits.pnpc(if4_bp.jmpIdx) := if4_bp.target 317 } 318 io.fetchPacket.bits.brInfo := bpu.io.branchInfo.bits 319 (0 until PredictWidth).foreach(i => io.fetchPacket.bits.brInfo(i).histPtr := if4_histPtr) 320 io.fetchPacket.bits.pd := if4_pd.pd 321 io.fetchPacket.bits.ipf := if4_ipf 322 io.fetchPacket.bits.crossPageIPFFix := if4_crossPageIPF 323 324 // predTaken Vec 325 io.fetchPacket.bits.predTaken := if4_bp.taken 326 327 // debug info 328 XSDebug(RegNext(reset.asBool) && !reset.asBool, "Reseting...\n") 329 XSDebug(io.icacheFlush(0).asBool, "Flush icache stage2...\n") 330 XSDebug(io.icacheFlush(1).asBool, "Flush icache stage3...\n") 331 XSDebug(io.redirect.valid, "Redirect from backend! isExcp=%d isFpp:%d isMisPred=%d isReplay=%d pc=%x\n", 332 io.redirect.bits.isException, io.redirect.bits.isFlushPipe, io.redirect.bits.isMisPred, io.redirect.bits.isReplay, io.redirect.bits.pc) 333 XSDebug(io.redirect.valid, p"Redirect from backend! target=${Hexadecimal(io.redirect.bits.target)} brTag=${io.redirect.bits.brTag}\n") 334 335 XSDebug("[IF1] v=%d fire=%d flush=%d pc=%x ptr=%d mask=%b\n", if1_valid, if1_fire, if1_flush, if1_npc, ptr, mask(if1_npc)) 336 XSDebug("[IF2] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d snpc=%x\n", if2_valid, if2_ready, if2_fire, if2_redirect, if2_flush, if2_pc, if2_histPtr, if2_snpc) 337 XSDebug("[IF3] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d crossPageIPF=%d\n", if3_valid, if3_ready, if3_fire, if3_redirect, if3_flush, if3_pc, if3_histPtr, crossPageIPF) 338 XSDebug("[IF4] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d crossPageIPF=%d\n", if4_valid, if4_ready, if4_fire, if4_redirect, if4_flush, if4_pc, if4_histPtr, if4_crossPageIPF) 339 340 XSDebug("[IF1][icacheReq] v=%d r=%d addr=%x\n", io.icacheReq.valid, io.icacheReq.ready, io.icacheReq.bits.addr) 341 XSDebug("[IF1][ghr] headPtr=%d shiftPtr=%d newPtr=%d ptr=%d\n", headPtr, shiftPtr, newPtr, ptr) 342 XSDebug("[IF1][ghr] hist=%b\n", hist.asUInt) 343 XSDebug("[IF1][ghr] extHist=%b\n\n", extHist.asUInt) 344 345 XSDebug("[IF2][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n\n", if2_bp.redirect, if2_bp.taken, if2_bp.jmpIdx, if2_bp.hasNotTakenBrs, if2_bp.target, if2_bp.saveHalfRVI) 346 347 XSDebug("[IF3][icacheResp] v=%d r=%d pc=%x mask=%b\n", io.icacheResp.valid, io.icacheResp.ready, io.icacheResp.bits.pc, io.icacheResp.bits.mask) 348 XSDebug("[IF3][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if3_bp.redirect, if3_bp.taken, if3_bp.jmpIdx, if3_bp.hasNotTakenBrs, if3_bp.target, if3_bp.saveHalfRVI) 349 // XSDebug("[IF3][prevHalfInstr] v=%d redirect=%d fetchpc=%x idx=%d tgt=%x taken=%d instr=%x\n\n", 350 // prev_half_valid, prev_half_redirect, prev_half_fetchpc, prev_half_idx, prev_half_tgt, prev_half_taken, prev_half_instr) 351 XSDebug("[IF3][ prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x ipf=%d\n", 352 prevHalfInstr.valid, prevHalfInstr.taken, prevHalfInstr.fetchpc, prevHalfInstr.idx, prevHalfInstr.pc, prevHalfInstr.target, prevHalfInstr.instr, prevHalfInstr.ipf) 353 XSDebug("[IF3][if3_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x ipf=%d\n\n", 354 if3_prevHalfInstr.valid, if3_prevHalfInstr.taken, if3_prevHalfInstr.fetchpc, if3_prevHalfInstr.idx, if3_prevHalfInstr.pc, if3_prevHalfInstr.target, if3_prevHalfInstr.instr, if3_prevHalfInstr.ipf) 355 356 357 XSDebug("[IF4][predecode] mask=%b\n", if4_pd.mask) 358 XSDebug("[IF4][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if4_bp.redirect, if4_bp.taken, if4_bp.jmpIdx, if4_bp.hasNotTakenBrs, if4_bp.target, if4_bp.saveHalfRVI) 359 XSDebug(if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken, "[IF4] cfi is jal! instr=%x target=%x\n", if4_cfi_jal, if4_cfi_jal_tgt) 360 XSDebug("[IF4][if4_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x ipf=%d\n", 361 if4_prevHalfInstr.valid, if4_prevHalfInstr.taken, if4_prevHalfInstr.fetchpc, if4_prevHalfInstr.idx, if4_prevHalfInstr.pc, if4_prevHalfInstr.target, if4_prevHalfInstr.instr, if4_prevHalfInstr.ipf) 362 XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] v=%d r=%d mask=%b ipf=%d crossPageIPF=%d\n", 363 io.fetchPacket.valid, io.fetchPacket.ready, io.fetchPacket.bits.mask, io.fetchPacket.bits.ipf, io.fetchPacket.bits.crossPageIPFFix) 364 for (i <- 0 until PredictWidth) { 365 XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] %b %x pc=%x pnpc=%x pd: rvc=%d brType=%b call=%d ret=%d\n", 366 io.fetchPacket.bits.mask(i), 367 io.fetchPacket.bits.instrs(i), 368 io.fetchPacket.bits.pc(i), 369 io.fetchPacket.bits.pnpc(i), 370 io.fetchPacket.bits.pd(i).isRVC, 371 io.fetchPacket.bits.pd(i).brType, 372 io.fetchPacket.bits.pd(i).isCall, 373 io.fetchPacket.bits.pd(i).isRet 374 ) 375 } 376}