1package xiangshan.frontend 2 3import chisel3._ 4import chisel3.util._ 5import chisel3.util.experimental.BoringUtils 6import device.RAMHelper 7import xiangshan._ 8import utils._ 9import xiangshan.cache._ 10 11trait HasIFUConst { this: XSModule => 12 val resetVector = 0x80000000L//TODO: set reset vec 13 val groupAlign = log2Up(FetchWidth * 4 * 2) 14 def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W)) 15 // each 1 bit in mask stands for 2 Bytes 16 def mask(pc: UInt): UInt = (Fill(PredictWidth * 2, 1.U(1.W)) >> pc(groupAlign - 1, 1))(PredictWidth - 1, 0) 17 def snpc(pc: UInt): UInt = pc + (PopCount(mask(pc)) << 1) 18 19 val IFUDebug = true 20} 21 22class GlobalHistoryInfo() extends XSBundle { 23 val sawNTBr = Bool() 24 val takenOnBr = Bool() 25 val saveHalfRVI = Bool() 26 def shifted = takenOnBr || sawNTBr 27 def newPtr(ptr: UInt) = Mux(shifted, ptr - 1.U, ptr) 28 implicit val name = "IFU" 29 def debug = XSDebug("[GHInfo] sawNTBr=%d, takenOnBr=%d, saveHalfRVI=%d\n", sawNTBr, takenOnBr, saveHalfRVI) 30 // override def toString(): String = "histPtr=%d, sawNTBr=%d, takenOnBr=%d, saveHalfRVI=%d".format(histPtr, sawNTBr, takenOnBr, saveHalfRVI) 31} 32 33class IFUIO extends XSBundle 34{ 35 val fetchPacket = DecoupledIO(new FetchPacket) 36 val redirect = Flipped(ValidIO(new Redirect)) 37 val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 38 val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 39 val icacheReq = DecoupledIO(new ICacheReq) 40 val icacheResp = Flipped(DecoupledIO(new ICacheResp)) 41 val icacheFlush = Output(UInt(2.W)) 42 val loopBufPar = Flipped(new LoopBufferParameters) 43} 44 45class IFU extends XSModule with HasIFUConst 46{ 47 val io = IO(new IFUIO) 48 val bpu = BPU(EnableBPU) 49 val pd = Module(new PreDecode) 50 51 val if2_redirect, if3_redirect, if4_redirect = WireInit(false.B) 52 val if1_flush, if2_flush, if3_flush, if4_flush = WireInit(false.B) 53 54 val icacheResp = WireInit(Mux(io.loopBufPar.inLoop, io.loopBufPar.LBResp, io.icacheResp.bits)) 55 56 if4_flush := io.redirect.valid || io.loopBufPar.LBredirect.valid 57 if3_flush := if4_flush || if4_redirect 58 if2_flush := if3_flush || if3_redirect 59 if1_flush := if2_flush || if2_redirect 60 61 //********************** IF1 ****************************// 62 val if1_valid = !reset.asBool && GTimer() > 500.U 63 val if1_npc = WireInit(0.U(VAddrBits.W)) 64 val if2_ready = WireInit(false.B) 65 val if1_fire = if1_valid && (if2_ready || if1_flush) && (io.loopBufPar.inLoop || io.icacheReq.ready) 66 67 68 val if1_histPtr, if2_histPtr, if3_histPtr, if4_histPtr = Wire(UInt(log2Up(ExtHistoryLength).W)) 69 val if2_newPtr, if3_newPtr, if4_newPtr = Wire(UInt(log2Up(ExtHistoryLength).W)) 70 71 val extHist = RegInit(VecInit(Seq.fill(ExtHistoryLength)(0.U(1.W)))) 72 val shiftPtr = WireInit(false.B) 73 val newPtr = Wire(UInt(log2Up(ExtHistoryLength).W)) 74 val ptr = Mux(shiftPtr, newPtr, if1_histPtr) 75 val hist = Wire(Vec(HistoryLength, UInt(1.W))) 76 for (i <- 0 until HistoryLength) { 77 hist(i) := extHist(ptr + i.U) 78 } 79 80 shiftPtr := false.B 81 newPtr := if1_histPtr 82 83 84 85 val if1_GHInfo = Wire(new GlobalHistoryInfo()) 86 if1_GHInfo := 0.U.asTypeOf(new GlobalHistoryInfo) 87 88 //********************** IF2 ****************************// 89 val if2_valid = RegEnable(next = if1_valid, init = false.B, enable = if1_fire) 90 val if3_ready = WireInit(false.B) 91 val if2_fire = if2_valid && if3_ready && !if2_flush 92 val if2_pc = RegEnable(next = if1_npc, init = resetVector.U, enable = if1_fire) 93 val if2_snpc = snpc(if2_pc) 94 val if2_GHInfo = RegEnable(if1_GHInfo, if1_fire) 95 val if2_predHistPtr = RegEnable(ptr, enable=if1_fire) 96 if2_ready := if2_fire || !if2_valid || if2_flush 97 when (if2_flush) { if2_valid := if1_fire } 98 .elsewhen (if1_fire) { if2_valid := if1_valid } 99 .elsewhen (if2_fire) { if2_valid := false.B } 100 101 when (RegNext(reset.asBool) && !reset.asBool) { 102 if1_npc := resetVector.U(VAddrBits.W) 103 }.elsewhen (if2_fire) { 104 if1_npc := if2_snpc 105 }.otherwise { 106 if1_npc := RegNext(if1_npc) 107 } 108 109 val if2_bp = bpu.io.out(0).bits 110 // if taken, bp_redirect should be true 111 // when taken on half RVI, we suppress this redirect signal 112 if2_redirect := if2_fire && bpu.io.out(0).valid && if2_bp.redirect && !if2_bp.saveHalfRVI 113 when (if2_redirect) { 114 if1_npc := if2_bp.target 115 } 116 117 val if2_realGHInfo = Wire(new GlobalHistoryInfo()) 118 if2_realGHInfo.sawNTBr := if2_bp.hasNotTakenBrs 119 if2_realGHInfo.takenOnBr := if2_bp.takenOnBr 120 if2_realGHInfo.saveHalfRVI := if2_bp.saveHalfRVI 121 122 when (if2_fire && if2_realGHInfo.shifted) { 123 shiftPtr := true.B 124 newPtr := if2_newPtr 125 } 126 when (if2_realGHInfo.shifted && if2_newPtr >= ptr) { 127 hist(if2_newPtr-ptr) := if2_realGHInfo.takenOnBr.asUInt 128 } 129 130 131 132 //********************** IF3 ****************************// 133 val if3_valid = RegEnable(next = if2_valid, init = false.B, enable = if2_fire) 134 val if4_ready = WireInit(false.B) 135 val if3_fire = if3_valid && if4_ready && (io.loopBufPar.inLoop || io.icacheResp.valid) && !if3_flush 136 val if3_pc = RegEnable(if2_pc, if2_fire) 137 val if3_GHInfo = RegEnable(if2_realGHInfo, if2_fire) 138 val if3_predHistPtr = RegEnable(if2_predHistPtr, enable=if2_fire) 139 if3_ready := if3_fire || !if3_valid || if3_flush 140 when (if3_flush) { if3_valid := false.B } 141 .elsewhen (if2_fire) { if3_valid := if2_valid } 142 .elsewhen (if3_fire) { if3_valid := false.B } 143 144 val if3_bp = bpu.io.out(1).bits 145 146 val if3_realGHInfo = Wire(new GlobalHistoryInfo()) 147 if3_realGHInfo.sawNTBr := if3_bp.hasNotTakenBrs 148 if3_realGHInfo.takenOnBr := if3_bp.takenOnBr 149 if3_realGHInfo.saveHalfRVI := if3_bp.saveHalfRVI 150 151 class PrevHalfInstr extends Bundle { 152 val valid = Bool() 153 val taken = Bool() 154 val ghInfo = new GlobalHistoryInfo() 155 val fetchpc = UInt(VAddrBits.W) // only for debug 156 val idx = UInt(VAddrBits.W) // only for debug 157 val pc = UInt(VAddrBits.W) 158 val target = UInt(VAddrBits.W) 159 val instr = UInt(16.W) 160 val ipf = Bool() 161 val newPtr = UInt(log2Up(ExtHistoryLength).W) 162 } 163 164 val if3_prevHalfInstr = RegInit(0.U.asTypeOf(new PrevHalfInstr)) 165 val if4_prevHalfInstr = Wire(new PrevHalfInstr) 166 // 32-bit instr crosses 2 pages, and the higher 16-bit triggers page fault 167 val crossPageIPF = WireInit(false.B) 168 when (if4_prevHalfInstr.valid) { 169 if3_prevHalfInstr := if4_prevHalfInstr 170 } 171 val prevHalfInstr = Mux(if4_prevHalfInstr.valid, if4_prevHalfInstr, if3_prevHalfInstr) 172 173 // the previous half of RVI instruction waits until it meets its last half 174 val if3_hasPrevHalfInstr = prevHalfInstr.valid && (prevHalfInstr.pc + 2.U) === if3_pc 175 // set to invalid once consumed or redirect from backend 176 val prevHalfConsumed = if3_hasPrevHalfInstr && if3_fire || if4_flush 177 when (prevHalfConsumed) { 178 if3_prevHalfInstr.valid := false.B 179 } 180 181 // when bp signal a redirect, we distinguish between taken and not taken 182 // if taken and saveHalfRVI is true, we do not redirect to the target 183 if3_redirect := if3_fire && bpu.io.out(1).valid && (if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.redirect && (if3_bp.taken && !if3_bp.saveHalfRVI || !if3_bp.taken) ) 184 185 when (if3_redirect) { 186 when (!(if3_hasPrevHalfInstr && prevHalfInstr.taken)) { 187 if1_npc := if3_bp.target 188 when (if3_realGHInfo.shifted){ 189 shiftPtr := true.B 190 newPtr := if3_newPtr 191 } 192 } 193 } 194 195 // when it does not redirect, we still need to modify hist(wire) 196 when(if3_realGHInfo.shifted && if3_newPtr >= ptr) { 197 hist(if3_newPtr-ptr) := if3_realGHInfo.takenOnBr 198 } 199 when (if3_hasPrevHalfInstr && prevHalfInstr.ghInfo.shifted && prevHalfInstr.newPtr >= ptr) { 200 hist(prevHalfInstr.newPtr-ptr) := prevHalfInstr.ghInfo.takenOnBr 201 } 202 203 //********************** IF4 ****************************// 204 val if4_pd = RegEnable(pd.io.out, if3_fire) 205 val if4_ipf = RegEnable(icacheResp.ipf || if3_hasPrevHalfInstr && prevHalfInstr.ipf, if3_fire) 206 val if4_crossPageIPF = RegEnable(crossPageIPF, if3_fire) 207 val if4_valid = RegInit(false.B) 208 val if4_fire = if4_valid && io.fetchPacket.ready 209 val if4_pc = RegEnable(if3_pc, if3_fire) 210 211 val if4_GHInfo = RegEnable(if3_realGHInfo, if3_fire) 212 val if4_predHistPtr = RegEnable(if3_predHistPtr, enable=if3_fire) 213 if4_ready := (if4_fire || !if4_valid || if4_flush) && GTimer() > 500.U 214 when (if4_flush) { if4_valid := false.B } 215 .elsewhen (if3_fire) { if4_valid := if3_valid } 216 .elsewhen(if4_fire) { if4_valid := false.B } 217 218 val if4_bp = Wire(new BranchPrediction) 219 if4_bp := bpu.io.out(2).bits 220 221 val if4_realGHInfo = Wire(new GlobalHistoryInfo()) 222 if4_realGHInfo.sawNTBr := if4_bp.hasNotTakenBrs 223 if4_realGHInfo.takenOnBr := if4_bp.takenOnBr 224 if4_realGHInfo.saveHalfRVI := if4_bp.saveHalfRVI 225 226 227 val if4_cfi_jal = if4_pd.instrs(if4_bp.jmpIdx) 228 val if4_cfi_jal_tgt = if4_pd.pc(if4_bp.jmpIdx) + Mux(if4_pd.pd(if4_bp.jmpIdx).isRVC, 229 SignExt(Cat(if4_cfi_jal(12), if4_cfi_jal(8), if4_cfi_jal(10, 9), if4_cfi_jal(6), if4_cfi_jal(7), if4_cfi_jal(2), if4_cfi_jal(11), if4_cfi_jal(5, 3), 0.U(1.W)), XLEN), 230 SignExt(Cat(if4_cfi_jal(31), if4_cfi_jal(19, 12), if4_cfi_jal(20), if4_cfi_jal(30, 21), 0.U(1.W)), XLEN)) 231 if4_bp.target := Mux(if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken, if4_cfi_jal_tgt, bpu.io.out(2).bits.target) 232 if4_bp.redirect := bpu.io.out(2).bits.redirect || if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken && if4_cfi_jal_tgt =/= bpu.io.out(2).bits.target 233 234 if4_prevHalfInstr := 0.U.asTypeOf(new PrevHalfInstr) 235 when (bpu.io.out(2).valid && if4_fire && if4_bp.saveHalfRVI) { 236 if4_prevHalfInstr.valid := true.B 237 if4_prevHalfInstr.taken := if4_bp.taken 238 if4_prevHalfInstr.ghInfo := if4_realGHInfo 239 // Make sure shifted can work 240 if4_prevHalfInstr.ghInfo.saveHalfRVI := false.B 241 if4_prevHalfInstr.newPtr := if4_newPtr 242 if4_prevHalfInstr.fetchpc := if4_pc 243 if4_prevHalfInstr.idx := PopCount(mask(if4_pc)) - 1.U 244 if4_prevHalfInstr.pc := if4_pd.pc(if4_prevHalfInstr.idx) 245 if4_prevHalfInstr.target := if4_bp.target 246 if4_prevHalfInstr.instr := if4_pd.instrs(if4_prevHalfInstr.idx)(15, 0) 247 if4_prevHalfInstr.ipf := if4_ipf 248 } 249 250 // Redirect and npc logic for if4 251 when (bpu.io.out(2).valid && if4_fire && if4_bp.redirect) { 252 if4_redirect := true.B 253 when (if4_bp.saveHalfRVI) { 254 if1_npc := snpc(if4_pc) 255 }.otherwise { 256 if1_npc := if4_bp.target 257 } 258 } 259 // }.elsewhen (bpu.io.out(2).valid && if4_fire/* && !if4_bp.redirect*/) { 260 // // We redirect the pipeline to the next fetch packet, 261 // // which contains the last half of the RVI instruction 262 // when (if4_bp.saveHalfRVI && if4_bp.taken) { 263 // if4_redirect := true.B 264 // if1_npc := snpc(if4_pc) 265 // } 266 // } 267 268 // This should cover the if4 redirect to snpc when saveHalfRVI 269 when (if3_redirect) { 270 when (if3_hasPrevHalfInstr && prevHalfInstr.taken) { 271 if1_npc := prevHalfInstr.target 272 } 273 } 274 275 // history logic for if4 276 when (bpu.io.out(2).valid && if4_fire && if4_bp.redirect) { 277 shiftPtr := true.B 278 newPtr := if4_newPtr 279 // }.elsewhen (bpu.io.out(2).valid && if4_fire/* && !if4_bp.redirect*/) { 280 // // only if we hasn't seen not taken branches and 281 // // see a not taken branch in if4 should we tell 282 // // if3 and if4 to update histptr 283 // // We do not shift global history pointer unless we have the full 284 // // RVI instruction 285 // when (if4_newSawNTBrs && !if4_bp.takenOnBr) { 286 // shiftPtr := true.B 287 // // newPtr := if4_realGHInfo.newPtr 288 // } 289 } 290 291 when (if4_realGHInfo.shifted && if4_newPtr >= ptr) { 292 hist(if4_newPtr-ptr) := if4_realGHInfo.takenOnBr 293 } 294 295 when (if3_redirect) { 296 // when redirect and if3_hasPrevHalfInstr, this prevHalfInstr should only be taken 297 when (if3_hasPrevHalfInstr && prevHalfInstr.ghInfo.shifted) { 298 shiftPtr := true.B 299 newPtr := prevHalfInstr.newPtr 300 extHist(prevHalfInstr.newPtr) := prevHalfInstr.ghInfo.takenOnBr 301 } 302 } 303 304 // modify GHR at the end of a prediction lifetime 305 when (if4_fire && if4_realGHInfo.shifted) { 306 extHist(if4_newPtr) := if4_realGHInfo.takenOnBr 307 } 308 309 // This is a histPtr which is only modified when a prediction 310 // is sent, so that it can get the final prediction info 311 val finalPredHistPtr = RegInit(0.U(log2Up(ExtHistoryLength).W)) 312 if4_histPtr := finalPredHistPtr 313 if4_newPtr := if3_histPtr 314 when (if4_fire && if4_realGHInfo.shifted) { 315 finalPredHistPtr := if4_newPtr 316 } 317 318 if3_histPtr := Mux(if4_realGHInfo.shifted && if4_valid && !if4_flush, if4_histPtr - 1.U, if4_histPtr) 319 if3_newPtr := if2_histPtr 320 321 if2_histPtr := Mux(if3_realGHInfo.shifted && if3_valid && !if3_flush, if3_histPtr - 1.U, if3_histPtr) 322 if2_newPtr := if1_histPtr 323 324 if1_histPtr := Mux(if2_realGHInfo.shifted && if2_valid && !if2_flush, if2_histPtr - 1.U, if2_histPtr) 325 326 327 328 329 when (io.outOfOrderBrInfo.valid && io.outOfOrderBrInfo.bits.isMisPred) { 330 val b = io.outOfOrderBrInfo.bits 331 val oldPtr = b.brInfo.histPtr 332 shiftPtr := true.B 333 when (!b.pd.isBr && !b.brInfo.sawNotTakenBranch) { 334 // If mispredicted cfi is not a branch, 335 // and there wasn't any not taken branch before it, 336 // we should only recover the pointer to an unshifted state 337 newPtr := oldPtr 338 finalPredHistPtr := oldPtr 339 }.otherwise { 340 newPtr := oldPtr - 1.U 341 finalPredHistPtr := oldPtr - 1.U 342 hist(0) := Mux(b.pd.isBr, b.taken, 0.U) 343 extHist(newPtr) := Mux(b.pd.isBr, b.taken, 0.U) 344 } 345 } 346 347 when (io.loopBufPar.LBredirect.valid) { 348 if1_npc := io.loopBufPar.LBredirect.bits 349 } 350 351 when (io.redirect.valid) { 352 if1_npc := io.redirect.bits.target 353 } 354 355 when(io.loopBufPar.inLoop) { 356 io.icacheReq.valid := if2_flush 357 }.otherwise { 358 io.icacheReq.valid := if1_valid && if2_ready 359 // io.icacheResp.ready := if3_ready 360 //io.icacheResp.ready := if3_valid 361 } 362 io.icacheResp.ready := if4_ready 363 io.icacheReq.bits.addr := if1_npc 364 365 // when(if4_bp.taken) { 366 // when(if4_bp.saveHalfRVI) { 367 // io.loopBufPar.LBReq := snpc(if4_pc) 368 // }.otherwise { 369 // io.loopBufPar.LBReq := if4_bp.target 370 // } 371 // }.otherwise { 372 // io.loopBufPar.LBReq := snpc(if4_pc) 373 // XSDebug(p"snpc(if4_pc)=${Hexadecimal(snpc(if4_pc))}\n") 374 // } 375 io.loopBufPar.LBReq := if3_pc 376 io.loopBufPar.tgtpc := if4_bp.target 377 378 io.icacheReq.bits.mask := mask(if1_npc) 379 380 io.icacheFlush := Cat(if3_flush, if2_flush) 381 382 val inOrderBrHist = Wire(Vec(HistoryLength, UInt(1.W))) 383 (0 until HistoryLength).foreach(i => inOrderBrHist(i) := extHist(i.U + io.inOrderBrInfo.bits.brInfo.predHistPtr)) 384 bpu.io.inOrderBrInfo.valid := io.inOrderBrInfo.valid 385 bpu.io.inOrderBrInfo.bits := BranchUpdateInfoWithHist(io.inOrderBrInfo.bits, inOrderBrHist.asUInt) 386 bpu.io.outOfOrderBrInfo.valid := io.outOfOrderBrInfo.valid 387 bpu.io.outOfOrderBrInfo.bits := BranchUpdateInfoWithHist(io.outOfOrderBrInfo.bits, inOrderBrHist.asUInt) // Dont care about hist 388 389 // bpu.io.flush := Cat(if4_flush, if3_flush, if2_flush) 390 bpu.io.flush := VecInit(if2_flush, if3_flush, if4_flush) 391 bpu.io.cacheValid := (io.loopBufPar.inLoop || io.icacheResp.valid) 392 bpu.io.in.valid := if1_fire 393 bpu.io.in.bits.pc := if1_npc 394 bpu.io.in.bits.hist := hist.asUInt 395 bpu.io.in.bits.histPtr := ptr 396 bpu.io.in.bits.inMask := mask(if1_npc) 397 bpu.io.out(0).ready := if2_fire 398 bpu.io.out(1).ready := if3_fire 399 bpu.io.out(2).ready := if4_fire 400 bpu.io.predecode.valid := if4_valid 401 bpu.io.predecode.bits.mask := if4_pd.mask 402 bpu.io.predecode.bits.pd := if4_pd.pd 403 bpu.io.predecode.bits.isFetchpcEqualFirstpc := if4_pc === if4_pd.pc(0) 404 bpu.io.branchInfo.ready := if4_fire 405 406 when(io.loopBufPar.inLoop) { 407 pd.io.in := io.loopBufPar.LBResp 408 pd.io.in.mask := io.loopBufPar.LBResp.mask & mask(io.loopBufPar.LBResp.pc) 409 XSDebug("Fetch from LB\n") 410 XSDebug(p"pc=${Hexadecimal(io.loopBufPar.LBResp.pc)}\n") 411 XSDebug(p"data=${Hexadecimal(io.loopBufPar.LBResp.data)}\n") 412 XSDebug(p"mask=${Hexadecimal(io.loopBufPar.LBResp.mask)}\n") 413 }.otherwise { 414 pd.io.in := icacheResp 415 } 416 pd.io.prev.valid := if3_hasPrevHalfInstr 417 pd.io.prev.bits := prevHalfInstr.instr 418 // if a fetch packet triggers page fault, set the pf instruction to nop 419 when (!if3_hasPrevHalfInstr && icacheResp.ipf) { 420 val instrs = Wire(Vec(FetchWidth, UInt(32.W))) 421 (0 until FetchWidth).foreach(i => instrs(i) := ZeroExt("b0010011".U, 32)) // nop 422 pd.io.in.data := instrs.asUInt 423 }.elsewhen (if3_hasPrevHalfInstr && (prevHalfInstr.ipf || icacheResp.ipf)) { 424 pd.io.prev.bits := ZeroExt("b0010011".U, 16) 425 val instrs = Wire(Vec(FetchWidth, UInt(32.W))) 426 (0 until FetchWidth).foreach(i => instrs(i) := Cat(ZeroExt("b0010011".U, 16), Fill(16, 0.U(1.W)))) 427 pd.io.in.data := instrs.asUInt 428 429 when (icacheResp.ipf && !prevHalfInstr.ipf) { crossPageIPF := true.B } // higher 16 bits page fault 430 } 431 432 io.fetchPacket.valid := if4_valid && !io.redirect.valid 433 io.fetchPacket.bits.instrs := if4_pd.instrs 434 io.fetchPacket.bits.mask := if4_pd.mask & (Fill(PredictWidth, !if4_bp.taken) | (Fill(PredictWidth, 1.U(1.W)) >> (~if4_bp.jmpIdx))) 435 io.fetchPacket.bits.pc := if4_pd.pc 436 (0 until PredictWidth).foreach(i => io.fetchPacket.bits.pnpc(i) := if4_pd.pc(i) + Mux(if4_pd.pd(i).isRVC, 2.U, 4.U)) 437 when (if4_bp.taken) { 438 io.fetchPacket.bits.pnpc(if4_bp.jmpIdx) := if4_bp.target 439 } 440 io.fetchPacket.bits.brInfo := bpu.io.branchInfo.bits 441 (0 until PredictWidth).foreach(i => io.fetchPacket.bits.brInfo(i).histPtr := finalPredHistPtr) 442 (0 until PredictWidth).foreach(i => io.fetchPacket.bits.brInfo(i).predHistPtr := if4_predHistPtr) 443 io.fetchPacket.bits.pd := if4_pd.pd 444 io.fetchPacket.bits.ipf := if4_ipf 445 io.fetchPacket.bits.crossPageIPFFix := if4_crossPageIPF 446 447 // predTaken Vec 448 io.fetchPacket.bits.predTaken := if4_bp.taken 449 450 // debug info 451 if (IFUDebug) { 452 XSDebug(RegNext(reset.asBool) && !reset.asBool, "Reseting...\n") 453 XSDebug(io.icacheFlush(0).asBool, "Flush icache stage2...\n") 454 XSDebug(io.icacheFlush(1).asBool, "Flush icache stage3...\n") 455 XSDebug(io.redirect.valid, "Redirect from backend! isExcp=%d isFpp:%d isMisPred=%d isReplay=%d pc=%x\n", 456 io.redirect.bits.isException, io.redirect.bits.isFlushPipe, io.redirect.bits.isMisPred, io.redirect.bits.isReplay, io.redirect.bits.pc) 457 XSDebug(io.redirect.valid, p"Redirect from backend! target=${Hexadecimal(io.redirect.bits.target)} brTag=${io.redirect.bits.brTag}\n") 458 459 XSDebug("[IF1] v=%d fire=%d flush=%d pc=%x ptr=%d mask=%b\n", if1_valid, if1_fire, if1_flush, if1_npc, ptr, mask(if1_npc)) 460 XSDebug("[IF2] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d snpc=%x\n", if2_valid, if2_ready, if2_fire, if2_redirect, if2_flush, if2_pc, if2_histPtr, if2_snpc) 461 XSDebug("[IF3] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d crossPageIPF=%d sawNTBrs=%d\n", if3_valid, if3_ready, if3_fire, if3_redirect, if3_flush, if3_pc, if3_histPtr, crossPageIPF, if3_realGHInfo.sawNTBr) 462 XSDebug("[IF4] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d crossPageIPF=%d sawNTBrs=%d\n", if4_valid, if4_ready, if4_fire, if4_redirect, if4_flush, if4_pc, if4_histPtr, if4_crossPageIPF, if4_realGHInfo.sawNTBr) 463 XSDebug("[IF1][icacheReq] v=%d r=%d addr=%x\n", io.icacheReq.valid, io.icacheReq.ready, io.icacheReq.bits.addr) 464 XSDebug("[IF1][ghr] headPtr=%d shiftPtr=%d newPtr=%d ptr=%d\n", if1_histPtr, shiftPtr, newPtr, ptr) 465 XSDebug("[IF1][ghr] hist=%b\n", hist.asUInt) 466 XSDebug("[IF1][ghr] extHist=%b\n\n", extHist.asUInt) 467 468 XSDebug("[IF2][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n\n", if2_bp.redirect, if2_bp.taken, if2_bp.jmpIdx, if2_bp.hasNotTakenBrs, if2_bp.target, if2_bp.saveHalfRVI) 469 // XSDebug("[IF2][GHInfo]: %s\n", if2_realGHInfo) 470 if2_realGHInfo.debug 471 472 XSDebug("[IF3][icacheResp] v=%d r=%d pc=%x mask=%b\n", io.icacheResp.valid, io.icacheResp.ready, io.icacheResp.bits.pc, io.icacheResp.bits.mask) 473 XSDebug("[IF3][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if3_bp.redirect, if3_bp.taken, if3_bp.jmpIdx, if3_bp.hasNotTakenBrs, if3_bp.target, if3_bp.saveHalfRVI) 474 // XSDebug("[IF3][prevHalfInstr] v=%d redirect=%d fetchpc=%x idx=%d tgt=%x taken=%d instr=%x\n\n", 475 // prev_half_valid, prev_half_redirect, prev_half_fetchpc, prev_half_idx, prev_half_tgt, prev_half_taken, prev_half_instr) 476 XSDebug("[IF3][ prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x ipf=%d\n", 477 prevHalfInstr.valid, prevHalfInstr.taken, prevHalfInstr.fetchpc, prevHalfInstr.idx, prevHalfInstr.pc, prevHalfInstr.target, prevHalfInstr.instr, prevHalfInstr.ipf) 478 XSDebug("[IF3][if3_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x ipf=%d\n\n", 479 if3_prevHalfInstr.valid, if3_prevHalfInstr.taken, if3_prevHalfInstr.fetchpc, if3_prevHalfInstr.idx, if3_prevHalfInstr.pc, if3_prevHalfInstr.target, if3_prevHalfInstr.instr, if3_prevHalfInstr.ipf) 480 // XSDebug("[IF3][GHInfo]: %s\n", if3_realGHInfo) 481 if3_realGHInfo.debug 482 483 XSDebug("[IF4][predecode] mask=%b\n", if4_pd.mask) 484 XSDebug("[IF4][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if4_bp.redirect, if4_bp.taken, if4_bp.jmpIdx, if4_bp.hasNotTakenBrs, if4_bp.target, if4_bp.saveHalfRVI) 485 XSDebug(if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken, "[IF4] cfi is jal! instr=%x target=%x\n", if4_cfi_jal, if4_cfi_jal_tgt) 486 XSDebug("[IF4][if4_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x ipf=%d\n", 487 if4_prevHalfInstr.valid, if4_prevHalfInstr.taken, if4_prevHalfInstr.fetchpc, if4_prevHalfInstr.idx, if4_prevHalfInstr.pc, if4_prevHalfInstr.target, if4_prevHalfInstr.instr, if4_prevHalfInstr.ipf) 488 // XSDebug("[IF4][GHInfo]: %s\n", if4_realGHInfo) 489 if4_realGHInfo.debug 490 XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] v=%d r=%d mask=%b ipf=%d crossPageIPF=%d\n", 491 io.fetchPacket.valid, io.fetchPacket.ready, io.fetchPacket.bits.mask, io.fetchPacket.bits.ipf, io.fetchPacket.bits.crossPageIPFFix) 492 for (i <- 0 until PredictWidth) { 493 XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] %b %x pc=%x pnpc=%x pd: rvc=%d brType=%b call=%d ret=%d\n", 494 io.fetchPacket.bits.mask(i), 495 io.fetchPacket.bits.instrs(i), 496 io.fetchPacket.bits.pc(i), 497 io.fetchPacket.bits.pnpc(i), 498 io.fetchPacket.bits.pd(i).isRVC, 499 io.fetchPacket.bits.pd(i).brType, 500 io.fetchPacket.bits.pd(i).isCall, 501 io.fetchPacket.bits.pd(i).isRet 502 ) 503 } 504 } 505}