1package xiangshan.frontend 2 3import chisel3._ 4import chisel3.util._ 5import device.RAMHelper 6import xiangshan._ 7import utils._ 8import xiangshan.cache._ 9 10trait HasIFUConst { this: XSModule => 11 val resetVector = 0x80000000L//TODO: set reset vec 12 val groupAlign = log2Up(FetchWidth * 4 * 2) 13 def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W)) 14 // each 1 bit in mask stands for 2 Bytes 15 def mask(pc: UInt): UInt = (Fill(PredictWidth * 2, 1.U(1.W)) >> pc(groupAlign - 1, 1))(PredictWidth - 1, 0) 16 def snpc(pc: UInt): UInt = pc + (PopCount(mask(pc)) << 1) 17 18 val IFUDebug = true 19} 20 21class IFUIO extends XSBundle 22{ 23 val fetchPacket = DecoupledIO(new FetchPacket) 24 val redirect = Flipped(ValidIO(new Redirect)) 25 val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 26 val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 27 val icacheReq = DecoupledIO(new ICacheReq) 28 val icacheResp = Flipped(DecoupledIO(new ICacheResp)) 29 val icacheFlush = Output(UInt(2.W)) 30} 31 32 33class IFU extends XSModule with HasIFUConst 34{ 35 val io = IO(new IFUIO) 36 val bpu = BPU(EnableBPU) 37 val pd = Module(new PreDecode) 38 39 val if2_redirect, if3_redirect, if4_redirect = WireInit(false.B) 40 val if1_flush, if2_flush, if3_flush, if4_flush = WireInit(false.B) 41 42 if4_flush := io.redirect.valid 43 if3_flush := if4_flush || if4_redirect 44 if2_flush := if3_flush || if3_redirect 45 if1_flush := if2_flush || if2_redirect 46 47 //********************** IF1 ****************************// 48 val if1_valid = !reset.asBool && GTimer() > 500.U 49 val if1_npc = WireInit(0.U(VAddrBits.W)) 50 val if2_ready = WireInit(false.B) 51 val if1_fire = if1_valid && (if2_ready || if1_flush) && io.icacheReq.ready 52 53 // val extHist = VecInit(Fill(ExtHistoryLength, RegInit(0.U(1.W)))) 54 val extHist = RegInit(VecInit(Seq.fill(ExtHistoryLength)(0.U(1.W)))) 55 val headPtr = RegInit(0.U(log2Up(ExtHistoryLength).W)) 56 val shiftPtr = WireInit(false.B) 57 val newPtr = Wire(UInt(log2Up(ExtHistoryLength).W)) 58 val ptr = Mux(shiftPtr, newPtr, headPtr) 59 when (shiftPtr) { headPtr := newPtr } 60 val hist = Wire(Vec(HistoryLength, UInt(1.W))) 61 for (i <- 0 until HistoryLength) { 62 hist(i) := extHist(ptr + i.U) 63 } 64 65 newPtr := headPtr 66 shiftPtr := false.B 67 68 //********************** IF2 ****************************// 69 val if2_valid = RegEnable(next = if1_valid, init = false.B, enable = if1_fire) 70 val if3_ready = WireInit(false.B) 71 val if2_fire = if2_valid && if3_ready && !if2_flush 72 val if2_pc = RegEnable(next = if1_npc, init = resetVector.U, enable = if1_fire) 73 val if2_snpc = snpc(if2_pc) 74 val if2_histPtr = RegEnable(ptr, if1_fire) 75 if2_ready := if2_fire || !if2_valid || if2_flush 76 when (if2_flush) { if2_valid := if1_fire } 77 .elsewhen (if1_fire) { if2_valid := if1_valid } 78 .elsewhen (if2_fire) { if2_valid := false.B } 79 80 when (RegNext(reset.asBool) && !reset.asBool) { 81 if1_npc := resetVector.U(VAddrBits.W) 82 }.elsewhen (if2_fire) { 83 if1_npc := if2_snpc 84 }.otherwise { 85 if1_npc := RegNext(if1_npc) 86 } 87 88 val if2_bp = bpu.io.out(0).bits 89 if2_redirect := if2_fire && bpu.io.out(0).valid && if2_bp.redirect// && !if2_bp.saveHalfRVI 90 when (if2_redirect) { 91 if1_npc := if2_bp.target 92 } 93 94 when (if2_fire && (if2_bp.takenOnBr || if2_bp.hasNotTakenBrs)) { 95 shiftPtr := true.B 96 newPtr := headPtr - 1.U 97 hist(0) := if2_bp.takenOnBr.asUInt 98 extHist(newPtr) := if2_bp.takenOnBr.asUInt 99 } 100 101 // repair histptr when if4 finds a not taken branch which is 102 // not recorded in uBTB or BTB 103 val if4_shiftWithoutRedirect = WireInit(false.B) 104 105 //********************** IF3 ****************************// 106 val if3_valid = RegEnable(next = if2_valid, init = false.B, enable = if2_fire) 107 val if4_ready = WireInit(false.B) 108 val if3_fire = if3_valid && if4_ready && io.icacheResp.valid && !if3_flush 109 val if3_pc = RegEnable(if2_pc, if2_fire) 110 val if3_histPtr = RegEnable(if2_histPtr - if4_shiftWithoutRedirect.asUInt, if2_fire) 111 if3_ready := if3_fire || !if3_valid || if3_flush 112 when (if3_flush) { if3_valid := false.B } 113 .elsewhen (if2_fire) { if3_valid := if2_valid } 114 .elsewhen (if3_fire) { if3_valid := false.B } 115 116 val if3_bp = bpu.io.out(1).bits 117 118 class PrevHalfInstr extends Bundle { 119 val valid = Bool() 120 val taken = Bool() 121 val fetchpc = UInt(VAddrBits.W) // only for debug 122 val idx = UInt(VAddrBits.W) // only for debug 123 val pc = UInt(VAddrBits.W) 124 val target = UInt(VAddrBits.W) 125 val instr = UInt(16.W) 126 val takenOnBr = Bool() 127 val ipf = Bool() 128 } 129 130 val if3_prevHalfInstr = RegInit(0.U.asTypeOf(new PrevHalfInstr)) 131 val if4_prevHalfInstr = Wire(new PrevHalfInstr) 132 // 32-bit instr crosses 2 pages, and the higher 16-bit triggers page fault 133 val crossPageIPF = WireInit(false.B) 134 when (if4_prevHalfInstr.valid) { 135 if3_prevHalfInstr := if4_prevHalfInstr 136 } 137 val prevHalfInstr = Mux(if4_prevHalfInstr.valid, if4_prevHalfInstr, if3_prevHalfInstr) 138 139 val if3_hasPrevHalfInstr = prevHalfInstr.valid && (prevHalfInstr.pc + 2.U) === if3_pc 140 if3_redirect := if3_fire && bpu.io.out(1).valid && (if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.redirect/* && !if3_bp.saveHalfRVI*/ ) 141 when (if3_redirect) { 142 if1_npc := Mux(if3_hasPrevHalfInstr && prevHalfInstr.taken, prevHalfInstr.target, if3_bp.target) 143 } 144 145 when (if3_fire && if3_redirect) { 146 shiftPtr := true.B 147 newPtr := Mux(if3_hasPrevHalfInstr && prevHalfInstr.takenOnBr || if3_bp.takenOnBr || if3_bp.hasNotTakenBrs, if3_histPtr - 1.U, if3_histPtr) 148 hist(0) := Mux(if3_hasPrevHalfInstr && prevHalfInstr.takenOnBr || if3_bp.takenOnBr || if3_bp.hasNotTakenBrs, 149 (if3_hasPrevHalfInstr && prevHalfInstr.takenOnBr || if3_bp.takenOnBr).asUInt, 150 extHist(if3_histPtr)) 151 extHist(newPtr) := Mux(if3_hasPrevHalfInstr && prevHalfInstr.takenOnBr || if3_bp.takenOnBr || if3_bp.hasNotTakenBrs, 152 (if3_hasPrevHalfInstr && prevHalfInstr.takenOnBr || if3_bp.takenOnBr).asUInt, 153 extHist(if3_histPtr)) 154 } 155 156 157 //********************** IF4 ****************************// 158 val if4_pd = RegEnable(pd.io.out, if3_fire) 159 val if4_ipf = RegEnable(io.icacheResp.bits.ipf || if3_hasPrevHalfInstr && prevHalfInstr.ipf, if3_fire) 160 val if4_crossPageIPF = RegEnable(crossPageIPF, if3_fire) 161 val if4_valid = RegInit(false.B) 162 val if4_fire = if4_valid && io.fetchPacket.ready 163 val if4_pc = RegEnable(if3_pc, if3_fire) 164 val if4_histPtr = RegEnable(if3_histPtr - if4_shiftWithoutRedirect.asUInt, if3_fire) 165 if4_ready := (if4_fire || !if4_valid || if4_flush) && GTimer() > 500.U 166 when (if4_flush) { if4_valid := false.B } 167 .elsewhen (if3_fire) { if4_valid := if3_valid } 168 .elsewhen(if4_fire) { if4_valid := false.B } 169 170 val if4_bp = Wire(new BranchPrediction) 171 if4_bp := bpu.io.out(2).bits 172 173 val if4_cfi_jal = if4_pd.instrs(if4_bp.jmpIdx) 174 val if4_cfi_jal_tgt = if4_pd.pc(if4_bp.jmpIdx) + Mux(if4_pd.pd(if4_bp.jmpIdx).isRVC, 175 SignExt(Cat(if4_cfi_jal(12), if4_cfi_jal(8), if4_cfi_jal(10, 9), if4_cfi_jal(6), if4_cfi_jal(7), if4_cfi_jal(2), if4_cfi_jal(11), if4_cfi_jal(5, 3), 0.U(1.W)), XLEN), 176 SignExt(Cat(if4_cfi_jal(31), if4_cfi_jal(19, 12), if4_cfi_jal(20), if4_cfi_jal(30, 21), 0.U(1.W)), XLEN)) 177 if4_bp.target := Mux(if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken, if4_cfi_jal_tgt, bpu.io.out(2).bits.target) 178 if4_bp.redirect := bpu.io.out(2).bits.redirect || if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken && if4_cfi_jal_tgt =/= bpu.io.out(2).bits.target 179 180 if4_prevHalfInstr := 0.U.asTypeOf(new PrevHalfInstr) 181 when (bpu.io.out(2).valid && if4_fire && if4_bp.saveHalfRVI) { 182 if4_prevHalfInstr.valid := true.B 183 if4_prevHalfInstr.taken := if4_bp.taken 184 if4_prevHalfInstr.takenOnBr := if4_bp.takenOnBr 185 if4_prevHalfInstr.fetchpc := if4_pc 186 if4_prevHalfInstr.idx := PopCount(mask(if4_pc)) - 1.U 187 if4_prevHalfInstr.pc := if4_pd.pc(if4_prevHalfInstr.idx) 188 if4_prevHalfInstr.target := if4_bp.target 189 if4_prevHalfInstr.instr := if4_pd.instrs(if4_prevHalfInstr.idx)(15, 0) 190 if4_prevHalfInstr.ipf := if4_ipf 191 } 192 193 when (bpu.io.out(2).valid && if4_fire && if4_bp.redirect) { 194 if4_redirect := true.B 195 shiftPtr := true.B 196 newPtr := Mux(if4_bp.takenOnBr || if4_bp.hasNotTakenBrs, if4_histPtr - 1.U, if4_histPtr) 197 hist(0) := Mux(if4_bp.takenOnBr || if4_bp.hasNotTakenBrs, if4_bp.takenOnBr.asUInt, extHist(if4_histPtr)) 198 extHist(newPtr) := Mux(if4_bp.takenOnBr || if4_bp.hasNotTakenBrs, if4_bp.takenOnBr.asUInt, extHist(if4_histPtr)) 199 when (if4_bp.saveHalfRVI) { 200 if1_npc := snpc(if4_pc) 201 }.otherwise { 202 if1_npc := if4_bp.target 203 } 204 }.elsewhen (bpu.io.out(2).valid && if4_fire/* && !if4_bp.redirect*/) { 205 when (if4_bp.saveHalfRVI && if4_bp.takenOnBr) { 206 if4_redirect := true.B 207 if1_npc := snpc(if4_pc) 208 shiftPtr := true.B 209 newPtr := if4_histPtr - 1.U 210 hist(0) := 1.U 211 extHist(newPtr) := 1.U 212 }.elsewhen (if4_bp.saveHalfRVI && if4_bp.taken) { 213 if4_redirect := true.B 214 if1_npc := snpc(if4_pc) 215 shiftPtr := true.B 216 newPtr := if4_histPtr 217 hist(0) := extHist(if4_histPtr) 218 extHist(newPtr) := extHist(if4_histPtr) 219 }.otherwise { 220 if4_redirect := false.B 221 when (if4_bp.takenOnBr || if4_bp.hasNotTakenBrs) { 222 shiftPtr := true.B 223 if4_shiftWithoutRedirect := true.B 224 newPtr := if4_histPtr - 1.U 225 hist(0) := if4_bp.takenOnBr.asUInt 226 extHist(newPtr) := if4_bp.takenOnBr.asUInt 227 } 228 } 229 }.otherwise { 230 if4_redirect := false.B 231 } 232 233 234 when (io.outOfOrderBrInfo.valid && io.outOfOrderBrInfo.bits.isMisPred) { 235 val b = io.outOfOrderBrInfo.bits 236 val oldPtr = b.brInfo.histPtr 237 shiftPtr := true.B 238 when (!b.pd.isBr && !b.brInfo.sawNotTakenBranch) { 239 // If mispredicted cfi is not a branch, 240 // and there wasn't any not taken branch before it, 241 // we should only recover the pointer to an unshifted state 242 newPtr := oldPtr 243 }.otherwise { 244 newPtr := oldPtr - 1.U 245 hist(0) := Mux(b.pd.isBr, b.taken, 0.U) 246 extHist(newPtr) := Mux(b.pd.isBr, b.taken, 0.U) 247 } 248 } 249 250 when (io.redirect.valid) { 251 if1_npc := io.redirect.bits.target 252 } 253 254 io.icacheReq.valid := if1_valid && if2_ready 255 io.icacheReq.bits.addr := if1_npc 256 io.icacheReq.bits.mask := mask(if1_npc) 257 io.icacheResp.ready := if4_ready 258 //io.icacheResp.ready := if3_valid 259 io.icacheFlush := Cat(if3_flush, if2_flush) 260 261 val inOrderBrHist = Wire(Vec(HistoryLength, UInt(1.W))) 262 (0 until HistoryLength).foreach(i => inOrderBrHist(i) := extHist(i.U + io.inOrderBrInfo.bits.brInfo.histPtr)) 263 bpu.io.inOrderBrInfo.valid := io.inOrderBrInfo.valid 264 bpu.io.inOrderBrInfo.bits := BranchUpdateInfoWithHist(io.inOrderBrInfo.bits, inOrderBrHist.asUInt) 265 bpu.io.outOfOrderBrInfo.valid := io.outOfOrderBrInfo.valid 266 bpu.io.outOfOrderBrInfo.bits := BranchUpdateInfoWithHist(io.outOfOrderBrInfo.bits, inOrderBrHist.asUInt) // Dont care about hist 267 268 // bpu.io.flush := Cat(if4_flush, if3_flush, if2_flush) 269 bpu.io.flush := VecInit(if2_flush, if3_flush, if4_flush) 270 bpu.io.cacheValid := io.icacheResp.valid 271 bpu.io.in.valid := if1_fire 272 bpu.io.in.bits.pc := if1_npc 273 bpu.io.in.bits.hist := hist.asUInt 274 bpu.io.in.bits.inMask := mask(if1_npc) 275 bpu.io.out(0).ready := if2_fire 276 bpu.io.out(1).ready := if3_fire 277 bpu.io.out(2).ready := if4_fire 278 bpu.io.predecode.valid := if4_valid 279 bpu.io.predecode.bits.mask := if4_pd.mask 280 bpu.io.predecode.bits.pd := if4_pd.pd 281 bpu.io.predecode.bits.isFetchpcEqualFirstpc := if4_pc === if4_pd.pc(0) 282 bpu.io.branchInfo.ready := if4_fire 283 284 pd.io.in := io.icacheResp.bits 285 pd.io.prev.valid := if3_hasPrevHalfInstr 286 pd.io.prev.bits := prevHalfInstr.instr 287 // if a fetch packet triggers page fault, set the pf instruction to nop 288 when (!if3_hasPrevHalfInstr && io.icacheResp.bits.ipf) { 289 val instrs = Wire(Vec(FetchWidth, UInt(32.W))) 290 (0 until FetchWidth).foreach(i => instrs(i) := ZeroExt("b0010011".U, 32)) // nop 291 pd.io.in.data := instrs.asUInt 292 }.elsewhen (if3_hasPrevHalfInstr && (prevHalfInstr.ipf || io.icacheResp.bits.ipf)) { 293 pd.io.prev.bits := ZeroExt("b0010011".U, 16) 294 val instrs = Wire(Vec(FetchWidth, UInt(32.W))) 295 (0 until FetchWidth).foreach(i => instrs(i) := Cat(ZeroExt("b0010011".U, 16), Fill(16, 0.U(1.W)))) 296 pd.io.in.data := instrs.asUInt 297 298 when (io.icacheResp.bits.ipf && !prevHalfInstr.ipf) { crossPageIPF := true.B } // higher 16 bits page fault 299 } 300 301 io.fetchPacket.valid := if4_valid && !io.redirect.valid 302 io.fetchPacket.bits.instrs := if4_pd.instrs 303 io.fetchPacket.bits.mask := if4_pd.mask & (Fill(PredictWidth, !if4_bp.taken) | (Fill(PredictWidth, 1.U(1.W)) >> (~if4_bp.jmpIdx))) 304 io.fetchPacket.bits.pc := if4_pd.pc 305 (0 until PredictWidth).foreach(i => io.fetchPacket.bits.pnpc(i) := if4_pd.pc(i) + Mux(if4_pd.pd(i).isRVC, 2.U, 4.U)) 306 when (if4_bp.taken) { 307 io.fetchPacket.bits.pnpc(if4_bp.jmpIdx) := if4_bp.target 308 } 309 io.fetchPacket.bits.brInfo := bpu.io.branchInfo.bits 310 (0 until PredictWidth).foreach(i => io.fetchPacket.bits.brInfo(i).histPtr := if4_histPtr) 311 io.fetchPacket.bits.pd := if4_pd.pd 312 io.fetchPacket.bits.ipf := if4_ipf 313 io.fetchPacket.bits.crossPageIPFFix := if4_crossPageIPF 314 315 // debug info 316 if (IFUDebug) { 317 XSDebug(RegNext(reset.asBool) && !reset.asBool, "Reseting...\n") 318 XSDebug(io.icacheFlush(0).asBool, "Flush icache stage2...\n") 319 XSDebug(io.icacheFlush(1).asBool, "Flush icache stage3...\n") 320 XSDebug(io.redirect.valid, "Redirect from backend! isExcp=%d isFpp:%d isMisPred=%d isReplay=%d pc=%x\n", 321 io.redirect.bits.isException, io.redirect.bits.isFlushPipe, io.redirect.bits.isMisPred, io.redirect.bits.isReplay, io.redirect.bits.pc) 322 XSDebug(io.redirect.valid, p"Redirect from backend! target=${Hexadecimal(io.redirect.bits.target)} brTag=${io.redirect.bits.brTag}\n") 323 324 XSDebug("[IF1] v=%d fire=%d flush=%d pc=%x ptr=%d mask=%b\n", if1_valid, if1_fire, if1_flush, if1_npc, ptr, mask(if1_npc)) 325 XSDebug("[IF2] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d snpc=%x\n", if2_valid, if2_ready, if2_fire, if2_redirect, if2_flush, if2_pc, if2_histPtr, if2_snpc) 326 XSDebug("[IF3] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d crossPageIPF=%d\n", if3_valid, if3_ready, if3_fire, if3_redirect, if3_flush, if3_pc, if3_histPtr, crossPageIPF) 327 XSDebug("[IF4] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d crossPageIPF=%d\n", if4_valid, if4_ready, if4_fire, if4_redirect, if4_flush, if4_pc, if4_histPtr, if4_crossPageIPF) 328 329 XSDebug("[IF1][icacheReq] v=%d r=%d addr=%x\n", io.icacheReq.valid, io.icacheReq.ready, io.icacheReq.bits.addr) 330 XSDebug("[IF1][ghr] headPtr=%d shiftPtr=%d newPtr=%d ptr=%d\n", headPtr, shiftPtr, newPtr, ptr) 331 XSDebug("[IF1][ghr] hist=%b\n", hist.asUInt) 332 XSDebug("[IF1][ghr] extHist=%b\n\n", extHist.asUInt) 333 334 XSDebug("[IF2][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n\n", if2_bp.redirect, if2_bp.taken, if2_bp.jmpIdx, if2_bp.hasNotTakenBrs, if2_bp.target, if2_bp.saveHalfRVI) 335 336 XSDebug("[IF3][icacheResp] v=%d r=%d pc=%x mask=%b\n", io.icacheResp.valid, io.icacheResp.ready, io.icacheResp.bits.pc, io.icacheResp.bits.mask) 337 XSDebug("[IF3][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if3_bp.redirect, if3_bp.taken, if3_bp.jmpIdx, if3_bp.hasNotTakenBrs, if3_bp.target, if3_bp.saveHalfRVI) 338 // XSDebug("[IF3][prevHalfInstr] v=%d redirect=%d fetchpc=%x idx=%d tgt=%x taken=%d instr=%x\n\n", 339 // prev_half_valid, prev_half_redirect, prev_half_fetchpc, prev_half_idx, prev_half_tgt, prev_half_taken, prev_half_instr) 340 XSDebug("[IF3][ prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x ipf=%d\n", 341 prevHalfInstr.valid, prevHalfInstr.taken, prevHalfInstr.fetchpc, prevHalfInstr.idx, prevHalfInstr.pc, prevHalfInstr.target, prevHalfInstr.instr, prevHalfInstr.ipf) 342 XSDebug("[IF3][if3_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x ipf=%d\n\n", 343 if3_prevHalfInstr.valid, if3_prevHalfInstr.taken, if3_prevHalfInstr.fetchpc, if3_prevHalfInstr.idx, if3_prevHalfInstr.pc, if3_prevHalfInstr.target, if3_prevHalfInstr.instr, if3_prevHalfInstr.ipf) 344 345 346 XSDebug("[IF4][predecode] mask=%b\n", if4_pd.mask) 347 XSDebug("[IF4][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if4_bp.redirect, if4_bp.taken, if4_bp.jmpIdx, if4_bp.hasNotTakenBrs, if4_bp.target, if4_bp.saveHalfRVI) 348 XSDebug(if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken, "[IF4] cfi is jal! instr=%x target=%x\n", if4_cfi_jal, if4_cfi_jal_tgt) 349 XSDebug("[IF4][if4_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x ipf=%d\n", 350 if4_prevHalfInstr.valid, if4_prevHalfInstr.taken, if4_prevHalfInstr.fetchpc, if4_prevHalfInstr.idx, if4_prevHalfInstr.pc, if4_prevHalfInstr.target, if4_prevHalfInstr.instr, if4_prevHalfInstr.ipf) 351 XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] v=%d r=%d mask=%b ipf=%d crossPageIPF=%d\n", 352 io.fetchPacket.valid, io.fetchPacket.ready, io.fetchPacket.bits.mask, io.fetchPacket.bits.ipf, io.fetchPacket.bits.crossPageIPFFix) 353 for (i <- 0 until PredictWidth) { 354 XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] %b %x pc=%x pnpc=%x pd: rvc=%d brType=%b call=%d ret=%d\n", 355 io.fetchPacket.bits.mask(i), 356 io.fetchPacket.bits.instrs(i), 357 io.fetchPacket.bits.pc(i), 358 io.fetchPacket.bits.pnpc(i), 359 io.fetchPacket.bits.pd(i).isRVC, 360 io.fetchPacket.bits.pd(i).brType, 361 io.fetchPacket.bits.pd(i).isCall, 362 io.fetchPacket.bits.pd(i).isRet 363 ) 364 } 365 } 366}