109c6f1ddSLingrui98/*************************************************************************************** 2e3da8badSTang Haojin* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3e3da8badSTang Haojin* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 409c6f1ddSLingrui98* Copyright (c) 2020-2021 Peng Cheng Laboratory 509c6f1ddSLingrui98* 609c6f1ddSLingrui98* XiangShan is licensed under Mulan PSL v2. 709c6f1ddSLingrui98* You can use this software according to the terms and conditions of the Mulan PSL v2. 809c6f1ddSLingrui98* You may obtain a copy of Mulan PSL v2 at: 909c6f1ddSLingrui98* http://license.coscl.org.cn/MulanPSL2 1009c6f1ddSLingrui98* 1109c6f1ddSLingrui98* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 1209c6f1ddSLingrui98* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 1309c6f1ddSLingrui98* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 1409c6f1ddSLingrui98* 1509c6f1ddSLingrui98* See the Mulan PSL v2 for more details. 1609c6f1ddSLingrui98***************************************************************************************/ 1709c6f1ddSLingrui98package xiangshan.frontend 1809c6f1ddSLingrui98 1909c6f1ddSLingrui98import chisel3._ 2009c6f1ddSLingrui98import chisel3.util._ 21d2b20d1aSTang Haojinimport java.util.ResourceBundle.Control 22*cf7d6b7aSMuziimport org.chipsalliance.cde.config.Parameters 23*cf7d6b7aSMuziimport scala.math._ 24*cf7d6b7aSMuziimport utility._ 25*cf7d6b7aSMuziimport utils._ 26*cf7d6b7aSMuziimport xiangshan._ 27*cf7d6b7aSMuziimport xiangshan.backend.fu.PMPRespBundle 28*cf7d6b7aSMuziimport xiangshan.cache.mmu.TlbResp 29*cf7d6b7aSMuziimport xiangshan.frontend.icache._ 30d2b20d1aSTang Haojin 31d2b20d1aSTang Haojinclass FrontendTopDownBundle(implicit p: Parameters) extends XSBundle { 32d2b20d1aSTang Haojin val reasons = Vec(TopDownCounters.NumStallReasons.id, Bool()) 33d2b20d1aSTang Haojin val stallWidth = UInt(log2Ceil(PredictWidth).W) 34d2b20d1aSTang Haojin} 3509c6f1ddSLingrui98 36b37e4b45SLingrui98class FetchRequestBundle(implicit p: Parameters) extends XSBundle with HasICacheParameters { 37c5c5edaeSJenius 38c5c5edaeSJenius // fast path: Timing critical 3909c6f1ddSLingrui98 val startAddr = UInt(VAddrBits.W) 4034a88126SJinYue val nextlineStart = UInt(VAddrBits.W) 41c5c5edaeSJenius val nextStartAddr = UInt(VAddrBits.W) 42c5c5edaeSJenius // slow path 4309c6f1ddSLingrui98 val ftqIdx = new FtqPtr 4409c6f1ddSLingrui98 val ftqOffset = ValidUndirectioned(UInt(log2Ceil(PredictWidth).W)) 4509c6f1ddSLingrui98 46d2b20d1aSTang Haojin val topdown_info = new FrontendTopDownBundle 47d2b20d1aSTang Haojin 486ce52296SJinYue def crossCacheline = startAddr(blockOffBits - 1) === 1.U 496ce52296SJinYue 5009c6f1ddSLingrui98 def fromFtqPcBundle(b: Ftq_RF_Components) = { 5109c6f1ddSLingrui98 this.startAddr := b.startAddr 52b37e4b45SLingrui98 this.nextlineStart := b.nextLineAddr 539402431eSmy-mayfly // when (b.fallThruError) { 549402431eSmy-mayfly // val nextBlockHigherTemp = Mux(startAddr(log2Ceil(PredictWidth)+instOffsetBits), b.nextLineAddr, b.startAddr) 559402431eSmy-mayfly // val nextBlockHigher = nextBlockHigherTemp(VAddrBits-1, log2Ceil(PredictWidth)+instOffsetBits+1) 569402431eSmy-mayfly // this.nextStartAddr := 579402431eSmy-mayfly // Cat(nextBlockHigher, 589402431eSmy-mayfly // startAddr(log2Ceil(PredictWidth)+instOffsetBits) ^ 1.U(1.W), 599402431eSmy-mayfly // startAddr(log2Ceil(PredictWidth)+instOffsetBits-1, instOffsetBits), 609402431eSmy-mayfly // 0.U(instOffsetBits.W) 619402431eSmy-mayfly // ) 629402431eSmy-mayfly // } 6309c6f1ddSLingrui98 this 6409c6f1ddSLingrui98 } 65*cf7d6b7aSMuzi override def toPrintable: Printable = 66b37e4b45SLingrui98 p"[start] ${Hexadecimal(startAddr)} [next] ${Hexadecimal(nextlineStart)}" + 67b37e4b45SLingrui98 p"[tgt] ${Hexadecimal(nextStartAddr)} [ftqIdx] $ftqIdx [jmp] v:${ftqOffset.valid}" + 6809c6f1ddSLingrui98 p" offset: ${ftqOffset.bits}\n" 6909c6f1ddSLingrui98} 7009c6f1ddSLingrui98 71f22cf846SJeniusclass FtqICacheInfo(implicit p: Parameters) extends XSBundle with HasICacheParameters { 72c5c5edaeSJenius val startAddr = UInt(VAddrBits.W) 73c5c5edaeSJenius val nextlineStart = UInt(VAddrBits.W) 74b92f8445Sssszwic val ftqIdx = new FtqPtr 75c5c5edaeSJenius def crossCacheline = startAddr(blockOffBits - 1) === 1.U 76b004fa13SJenius def fromFtqPcBundle(b: Ftq_RF_Components) = { 77b004fa13SJenius this.startAddr := b.startAddr 78b004fa13SJenius this.nextlineStart := b.nextLineAddr 79b004fa13SJenius this 80b004fa13SJenius } 81f22cf846SJenius} 82f22cf846SJenius 8350780602SJeniusclass IFUICacheIO(implicit p: Parameters) extends XSBundle with HasICacheParameters { 8450780602SJenius val icacheReady = Output(Bool()) 8550780602SJenius val resp = Vec(PortNumber, ValidIO(new ICacheMainPipeResp)) 86d2b20d1aSTang Haojin val topdownIcacheMiss = Output(Bool()) 87d2b20d1aSTang Haojin val topdownItlbMiss = Output(Bool()) 8850780602SJenius} 8950780602SJenius 90f22cf846SJeniusclass FtqToICacheRequestBundle(implicit p: Parameters) extends XSBundle with HasICacheParameters { 91f56177cbSJenius val pcMemRead = Vec(5, new FtqICacheInfo) 92dc270d3bSJenius val readValid = Vec(5, Bool()) 93c1b28b66STang Haojin val backendIpf = Bool() 94c1b28b66STang Haojin val backendIgpf = Bool() 95c1b28b66STang Haojin val backendIaf = Bool() 96c5c5edaeSJenius} 97c5c5edaeSJenius 9809c6f1ddSLingrui98class PredecodeWritebackBundle(implicit p: Parameters) extends XSBundle { 9909c6f1ddSLingrui98 val pc = Vec(PredictWidth, UInt(VAddrBits.W)) 10009c6f1ddSLingrui98 val pd = Vec(PredictWidth, new PreDecodeInfo) // TODO: redefine Predecode 10109c6f1ddSLingrui98 val ftqIdx = new FtqPtr 10209c6f1ddSLingrui98 val ftqOffset = UInt(log2Ceil(PredictWidth).W) 10309c6f1ddSLingrui98 val misOffset = ValidUndirectioned(UInt(log2Ceil(PredictWidth).W)) 10409c6f1ddSLingrui98 val cfiOffset = ValidUndirectioned(UInt(log2Ceil(PredictWidth).W)) 10509c6f1ddSLingrui98 val target = UInt(VAddrBits.W) 10609c6f1ddSLingrui98 val jalTarget = UInt(VAddrBits.W) 10709c6f1ddSLingrui98 val instrRange = Vec(PredictWidth, Bool()) 10809c6f1ddSLingrui98} 10909c6f1ddSLingrui98 1101d1e6d4dSJeniusclass mmioCommitRead(implicit p: Parameters) extends XSBundle { 1111d1e6d4dSJenius val mmioFtqPtr = Output(new FtqPtr) 1121d1e6d4dSJenius val mmioLastCommit = Input(Bool()) 1131d1e6d4dSJenius} 1141d1e6d4dSJenius 1156b46af8dSMuziobject ExceptionType { 11688895b11Sxu_zh def none: UInt = "b00".U 11788895b11Sxu_zh def pf: UInt = "b01".U // instruction page fault 11888895b11Sxu_zh def gpf: UInt = "b10".U // instruction guest page fault 11988895b11Sxu_zh def af: UInt = "b11".U // instruction access fault 12088895b11Sxu_zh def width: Int = 2 12188895b11Sxu_zh 122c1b28b66STang Haojin def fromOH(has_pf: Bool, has_gpf: Bool, has_af: Bool): UInt = { 123c1b28b66STang Haojin assert( 124c1b28b66STang Haojin PopCount(VecInit(has_pf, has_gpf, has_af)) <= 1.U, 125c1b28b66STang Haojin "ExceptionType.fromOH receives input that is not one-hot: pf=%d, gpf=%d, af=%d", 126*cf7d6b7aSMuzi has_pf, 127*cf7d6b7aSMuzi has_gpf, 128*cf7d6b7aSMuzi has_af 129c1b28b66STang Haojin ) 130c1b28b66STang Haojin // input is at-most-one-hot encoded, so we don't worry about priority here. 131*cf7d6b7aSMuzi MuxCase( 132*cf7d6b7aSMuzi none, 133*cf7d6b7aSMuzi Seq( 134c1b28b66STang Haojin has_pf -> pf, 135c1b28b66STang Haojin has_gpf -> gpf, 136c1b28b66STang Haojin has_af -> af 137*cf7d6b7aSMuzi ) 138*cf7d6b7aSMuzi ) 139c1b28b66STang Haojin } 140c1b28b66STang Haojin 141c1b28b66STang Haojin // raise pf/gpf/af according to ftq(backend) request 142*cf7d6b7aSMuzi def fromFtq(req: FtqToICacheRequestBundle): UInt = 143c1b28b66STang Haojin fromOH( 144c1b28b66STang Haojin req.backendIpf, 145c1b28b66STang Haojin req.backendIgpf, 146c1b28b66STang Haojin req.backendIaf 147c1b28b66STang Haojin ) 148c1b28b66STang Haojin 14988895b11Sxu_zh // raise pf/gpf/af according to itlb response 15088895b11Sxu_zh def fromTlbResp(resp: TlbResp, useDup: Int = 0): UInt = { 15188895b11Sxu_zh require(useDup >= 0 && useDup < resp.excp.length) 152c1b28b66STang Haojin // itlb is guaranteed to respond at most one exception 153c1b28b66STang Haojin fromOH( 154c1b28b66STang Haojin resp.excp(useDup).pf.instr, 155c1b28b66STang Haojin resp.excp(useDup).gpf.instr, 156c1b28b66STang Haojin resp.excp(useDup).af.instr 15788895b11Sxu_zh ) 15888895b11Sxu_zh } 15988895b11Sxu_zh 16088895b11Sxu_zh // raise af if pmp check failed 161*cf7d6b7aSMuzi def fromPMPResp(resp: PMPRespBundle): UInt = 16288895b11Sxu_zh Mux(resp.instr, af, none) 16388895b11Sxu_zh 16488895b11Sxu_zh // raise af if meta/data array ecc check failed or l2 cache respond with tilelink corrupt 165f80535c3Sxu_zh /* FIXME: RISC-V Machine ISA v1.13 (draft) introduced a "hardware error" exception, described as: 166f80535c3Sxu_zh * > A Hardware Error exception is a synchronous exception triggered when corrupted or 167f80535c3Sxu_zh * > uncorrectable data is accessed explicitly or implicitly by an instruction. In this context, 168f80535c3Sxu_zh * > "data" encompasses all types of information used within a RISC-V hart. Upon a hardware 169f80535c3Sxu_zh * > error exception, the xepc register is set to the address of the instruction that attempted to 170f80535c3Sxu_zh * > access corrupted data, while the xtval register is set either to 0 or to the virtual address 171f80535c3Sxu_zh * > of an instruction fetch, load, or store that attempted to access corrupted data. The priority 172f80535c3Sxu_zh * > of Hardware Error exception is implementation-defined, but any given occurrence is 173f80535c3Sxu_zh * > generally expected to be recognized at the point in the overall priority order at which the 174f80535c3Sxu_zh * > hardware error is discovered. 175f80535c3Sxu_zh * Maybe it's better to raise hardware error instead of access fault when ECC check failed. 176f80535c3Sxu_zh * But it's draft and XiangShan backend does not implement this exception code yet, so we still raise af here. 177f80535c3Sxu_zh */ 178*cf7d6b7aSMuzi def fromECC(enable: Bool, corrupt: Bool): UInt = 179f80535c3Sxu_zh Mux(enable && corrupt, af, none) 18088895b11Sxu_zh 18188895b11Sxu_zh /**Generates exception mux tree 18288895b11Sxu_zh * 18388895b11Sxu_zh * Exceptions that are further to the left in the parameter list have higher priority 18488895b11Sxu_zh * @example 18588895b11Sxu_zh * {{{ 18688895b11Sxu_zh * val itlb_exception = ExceptionType.fromTlbResp(io.itlb.resp.bits) 18788895b11Sxu_zh * // so as pmp_exception, meta_corrupt 18888895b11Sxu_zh * // ExceptionType.merge(itlb_exception, pmp_exception, meta_corrupt) is equivalent to: 18988895b11Sxu_zh * Mux( 19088895b11Sxu_zh * itlb_exception =/= none, 19188895b11Sxu_zh * itlb_exception, 19288895b11Sxu_zh * Mux(pmp_exception =/= none, pmp_exception, meta_corrupt) 19388895b11Sxu_zh * ) 19488895b11Sxu_zh * }}} 19588895b11Sxu_zh */ 19688895b11Sxu_zh def merge(exceptions: UInt*): UInt = { 19788895b11Sxu_zh// // recursively generate mux tree 19888895b11Sxu_zh// if (exceptions.length == 1) { 19988895b11Sxu_zh// require(exceptions.head.getWidth == width) 20088895b11Sxu_zh// exceptions.head 20188895b11Sxu_zh// } else { 20288895b11Sxu_zh// Mux(exceptions.head =/= none, exceptions.head, merge(exceptions.tail: _*)) 20388895b11Sxu_zh// } 20488895b11Sxu_zh // use MuxCase with default 20588895b11Sxu_zh exceptions.foreach(e => require(e.getWidth == width)) 20688895b11Sxu_zh val mapping = exceptions.init.map(e => (e =/= none) -> e) 20788895b11Sxu_zh val default = exceptions.last 20888895b11Sxu_zh MuxCase(default, mapping) 20988895b11Sxu_zh } 21088895b11Sxu_zh 21188895b11Sxu_zh /**Generates exception mux tree for multi-port exception vectors 21288895b11Sxu_zh * 21388895b11Sxu_zh * Exceptions that are further to the left in the parameter list have higher priority 21488895b11Sxu_zh * @example 21588895b11Sxu_zh * {{{ 21688895b11Sxu_zh * val itlb_exception = VecInit((0 until PortNumber).map(i => ExceptionType.fromTlbResp(io.itlb(i).resp.bits))) 21788895b11Sxu_zh * // so as pmp_exception, meta_corrupt 21888895b11Sxu_zh * // ExceptionType.merge(itlb_exception, pmp_exception, meta_corrupt) is equivalent to: 21988895b11Sxu_zh * VecInit((0 until PortNumber).map(i => Mux( 22088895b11Sxu_zh * itlb_exception(i) =/= none, 22188895b11Sxu_zh * itlb_exception(i), 22288895b11Sxu_zh * Mux(pmp_exception(i) =/= none, pmp_exception(i), meta_corrupt(i)) 22388895b11Sxu_zh * )) 22488895b11Sxu_zh * }}} 22588895b11Sxu_zh */ 22688895b11Sxu_zh def merge(exceptionVecs: Vec[UInt]*): Vec[UInt] = { 22788895b11Sxu_zh// // recursively generate mux tree 22888895b11Sxu_zh// if (exceptionVecs.length == 1) { 22988895b11Sxu_zh// exceptionVecs.head.foreach(e => require(e.getWidth == width)) 23088895b11Sxu_zh// exceptionVecs.head 23188895b11Sxu_zh// } else { 23288895b11Sxu_zh// require(exceptionVecs.head.length == exceptionVecs.last.length) 23388895b11Sxu_zh// VecInit((exceptionVecs.head zip merge(exceptionVecs.tail: _*)).map{ case (high, low) => 23488895b11Sxu_zh// Mux(high =/= none, high, low) 23588895b11Sxu_zh// }) 23688895b11Sxu_zh// } 23788895b11Sxu_zh // merge port-by-port 23888895b11Sxu_zh val length = exceptionVecs.head.length 23988895b11Sxu_zh exceptionVecs.tail.foreach(vec => require(vec.length == length)) 240*cf7d6b7aSMuzi VecInit((0 until length).map(i => merge(exceptionVecs.map(_(i)): _*))) 24188895b11Sxu_zh } 2426b46af8dSMuzi} 2436b46af8dSMuzi 24409c6f1ddSLingrui98class FetchToIBuffer(implicit p: Parameters) extends XSBundle { 24509c6f1ddSLingrui98 val instrs = Vec(PredictWidth, UInt(32.W)) 24609c6f1ddSLingrui98 val valid = UInt(PredictWidth.W) 2472a3050c2SJay val enqEnable = UInt(PredictWidth.W) 24809c6f1ddSLingrui98 val pd = Vec(PredictWidth, new PreDecodeInfo) 24909c6f1ddSLingrui98 val foldpc = Vec(PredictWidth, UInt(MemPredPCWidth.W)) 25009c6f1ddSLingrui98 val ftqOffset = Vec(PredictWidth, ValidUndirectioned(UInt(log2Ceil(PredictWidth).W))) 251c1b28b66STang Haojin val exceptionFromBackend = Vec(PredictWidth, Bool()) 2526b46af8dSMuzi val exceptionType = Vec(PredictWidth, UInt(ExceptionType.width.W)) 25309c6f1ddSLingrui98 val crossPageIPFFix = Vec(PredictWidth, Bool()) 25492c61038SXuan Hu val illegalInstr = Vec(PredictWidth, Bool()) 2557e0f64b0SGuanghui Cheng val triggered = Vec(PredictWidth, TriggerAction()) 256948e8159SEaston Man val isLastInFtqEntry = Vec(PredictWidth, Bool()) 257948e8159SEaston Man 258948e8159SEaston Man val pc = Vec(PredictWidth, UInt(VAddrBits.W)) 259948e8159SEaston Man val ftqPtr = new FtqPtr 260d2b20d1aSTang Haojin val topdown_info = new FrontendTopDownBundle 26109c6f1ddSLingrui98} 26209c6f1ddSLingrui98 263c2ad24ebSLingrui98// class BitWiseUInt(val width: Int, val init: UInt) extends Module { 264c2ad24ebSLingrui98// val io = IO(new Bundle { 265c2ad24ebSLingrui98// val set 266c2ad24ebSLingrui98// }) 267c2ad24ebSLingrui98// } 26809c6f1ddSLingrui98// Move from BPU 269c2ad24ebSLingrui98abstract class GlobalHistory(implicit p: Parameters) extends XSBundle with HasBPUConst { 270c2ad24ebSLingrui98 def update(br_valids: Vec[Bool], real_taken_mask: Vec[Bool]): GlobalHistory 271c2ad24ebSLingrui98} 272c2ad24ebSLingrui98 273c2ad24ebSLingrui98class ShiftingGlobalHistory(implicit p: Parameters) extends GlobalHistory { 27409c6f1ddSLingrui98 val predHist = UInt(HistoryLength.W) 27509c6f1ddSLingrui98 276c2ad24ebSLingrui98 def update(shift: UInt, taken: Bool, hist: UInt = this.predHist): ShiftingGlobalHistory = { 277c2ad24ebSLingrui98 val g = Wire(new ShiftingGlobalHistory) 27809c6f1ddSLingrui98 g.predHist := (hist << shift) | taken 27909c6f1ddSLingrui98 g 28009c6f1ddSLingrui98 } 28109c6f1ddSLingrui98 282c2ad24ebSLingrui98 def update(br_valids: Vec[Bool], real_taken_mask: Vec[Bool]): ShiftingGlobalHistory = { 283eeb5ff92SLingrui98 require(br_valids.length == numBr) 284eeb5ff92SLingrui98 require(real_taken_mask.length == numBr) 285eeb5ff92SLingrui98 val last_valid_idx = PriorityMux( 286eeb5ff92SLingrui98 br_valids.reverse :+ true.B, 287eeb5ff92SLingrui98 (numBr to 0 by -1).map(_.U(log2Ceil(numBr + 1).W)) 288eeb5ff92SLingrui98 ) 289eeb5ff92SLingrui98 val first_taken_idx = PriorityEncoder(false.B +: real_taken_mask) 290*cf7d6b7aSMuzi val smaller = Mux(last_valid_idx < first_taken_idx, last_valid_idx, first_taken_idx) 291eeb5ff92SLingrui98 val shift = smaller 292eeb5ff92SLingrui98 val taken = real_taken_mask.reduce(_ || _) 293eeb5ff92SLingrui98 update(shift, taken, this.predHist) 294eeb5ff92SLingrui98 } 295eeb5ff92SLingrui98 296c2ad24ebSLingrui98 // static read 297935edac4STang Haojin def read(n: Int): Bool = predHist.asBools(n) 298c2ad24ebSLingrui98 299*cf7d6b7aSMuzi final def ===(that: ShiftingGlobalHistory): Bool = 30009c6f1ddSLingrui98 predHist === that.predHist 30109c6f1ddSLingrui98 302c2ad24ebSLingrui98 final def =/=(that: ShiftingGlobalHistory): Bool = !(this === that) 303c2ad24ebSLingrui98} 30409c6f1ddSLingrui98 305c2ad24ebSLingrui98// circular global history pointer 306*cf7d6b7aSMuziclass CGHPtr(implicit p: Parameters) extends CircularQueuePtr[CGHPtr](p => p(XSCoreParamsKey).HistoryLength) {} 307c7fabd05SSteve Gou 308c7fabd05SSteve Gouobject CGHPtr { 309c7fabd05SSteve Gou def apply(f: Bool, v: UInt)(implicit p: Parameters): CGHPtr = { 310c7fabd05SSteve Gou val ptr = Wire(new CGHPtr) 311c7fabd05SSteve Gou ptr.flag := f 312c7fabd05SSteve Gou ptr.value := v 313c7fabd05SSteve Gou ptr 314c7fabd05SSteve Gou } 315*cf7d6b7aSMuzi def inverse(ptr: CGHPtr)(implicit p: Parameters): CGHPtr = 316c7fabd05SSteve Gou apply(!ptr.flag, ptr.value) 317c7fabd05SSteve Gou} 318c7fabd05SSteve Gou 319c2ad24ebSLingrui98class CircularGlobalHistory(implicit p: Parameters) extends GlobalHistory { 320c2ad24ebSLingrui98 val buffer = Vec(HistoryLength, Bool()) 321c2ad24ebSLingrui98 type HistPtr = UInt 322*cf7d6b7aSMuzi def update(br_valids: Vec[Bool], real_taken_mask: Vec[Bool]): CircularGlobalHistory = 323c2ad24ebSLingrui98 this 324c2ad24ebSLingrui98} 325c2ad24ebSLingrui98 326dd6c0695SLingrui98class FoldedHistory(val len: Int, val compLen: Int, val max_update_num: Int)(implicit p: Parameters) 327c2ad24ebSLingrui98 extends XSBundle with HasBPUConst { 328dd6c0695SLingrui98 require(compLen >= 1) 329c2ad24ebSLingrui98 require(len > 0) 330c2ad24ebSLingrui98 // require(folded_len <= len) 331dd6c0695SLingrui98 require(compLen >= max_update_num) 332dd6c0695SLingrui98 val folded_hist = UInt(compLen.W) 333dd6c0695SLingrui98 33467402d75SLingrui98 def need_oldest_bits = len > compLen 335dd6c0695SLingrui98 def info = (len, compLen) 336c2ad24ebSLingrui98 def oldest_bit_to_get_from_ghr = (0 until max_update_num).map(len - _ - 1) 337c2ad24ebSLingrui98 def oldest_bit_pos_in_folded = oldest_bit_to_get_from_ghr map (_ % compLen) 338c2ad24ebSLingrui98 def oldest_bit_wrap_around = oldest_bit_to_get_from_ghr map (_ / compLen > 0) 339c2ad24ebSLingrui98 def oldest_bit_start = oldest_bit_pos_in_folded.head 340c2ad24ebSLingrui98 341*cf7d6b7aSMuzi def get_oldest_bits_from_ghr(ghr: Vec[Bool], histPtr: CGHPtr) = 342c2ad24ebSLingrui98 // TODO: wrap inc for histPtr value 343dd6c0695SLingrui98 oldest_bit_to_get_from_ghr.map(i => ghr((histPtr + (i + 1).U).value)) 344c2ad24ebSLingrui98 345ab890bfeSLingrui98 def circular_shift_left(src: UInt, shamt: Int) = { 346c2ad24ebSLingrui98 val srcLen = src.getWidth 347c2ad24ebSLingrui98 val src_doubled = Cat(src, src) 348ab890bfeSLingrui98 val shifted = src_doubled(srcLen * 2 - 1 - shamt, srcLen - shamt) 349ab890bfeSLingrui98 shifted 350c2ad24ebSLingrui98 } 351c2ad24ebSLingrui98 35267402d75SLingrui98 // slow path, read bits from ghr 353ab890bfeSLingrui98 def update(ghr: Vec[Bool], histPtr: CGHPtr, num: Int, taken: Bool): FoldedHistory = { 35467402d75SLingrui98 val oldest_bits = VecInit(get_oldest_bits_from_ghr(ghr, histPtr)) 35567402d75SLingrui98 update(oldest_bits, num, taken) 35667402d75SLingrui98 } 35767402d75SLingrui98 35867402d75SLingrui98 // fast path, use pre-read oldest bits 35967402d75SLingrui98 def update(ob: Vec[Bool], num: Int, taken: Bool): FoldedHistory = { 360c2ad24ebSLingrui98 // do xors for several bitsets at specified bits 361c2ad24ebSLingrui98 def bitsets_xor(len: Int, bitsets: Seq[Seq[Tuple2[Int, Bool]]]) = { 362c2ad24ebSLingrui98 val res = Wire(Vec(len, Bool())) 363c2ad24ebSLingrui98 // println(f"num bitsets: ${bitsets.length}") 364c2ad24ebSLingrui98 // println(f"bitsets $bitsets") 365c2ad24ebSLingrui98 val resArr = Array.fill(len)(List[Bool]()) 366c2ad24ebSLingrui98 for (bs <- bitsets) { 367c2ad24ebSLingrui98 for ((n, b) <- bs) { 368c2ad24ebSLingrui98 resArr(n) = b :: resArr(n) 369c2ad24ebSLingrui98 } 370c2ad24ebSLingrui98 } 371c2ad24ebSLingrui98 // println(f"${resArr.mkString}") 372c2ad24ebSLingrui98 // println(f"histLen: ${this.len}, foldedLen: $folded_len") 373c2ad24ebSLingrui98 for (i <- 0 until len) { 374c2ad24ebSLingrui98 // println(f"bit[$i], ${resArr(i).mkString}") 375c2ad24ebSLingrui98 if (resArr(i).length == 0) { 376dd6c0695SLingrui98 println(f"[error] bits $i is not assigned in folded hist update logic! histlen:${this.len}, compLen:$compLen") 377c2ad24ebSLingrui98 } 378c2ad24ebSLingrui98 res(i) := resArr(i).foldLeft(false.B)(_ ^ _) 379c2ad24ebSLingrui98 } 380c2ad24ebSLingrui98 res.asUInt 381c2ad24ebSLingrui98 } 382c2ad24ebSLingrui98 38367402d75SLingrui98 val new_folded_hist = if (need_oldest_bits) { 38467402d75SLingrui98 val oldest_bits = ob 38567402d75SLingrui98 require(oldest_bits.length == max_update_num) 386c2ad24ebSLingrui98 // mask off bits that do not update 387c2ad24ebSLingrui98 val oldest_bits_masked = oldest_bits.zipWithIndex.map { 388ab890bfeSLingrui98 case (ob, i) => ob && (i < num).B 389c2ad24ebSLingrui98 } 390c2ad24ebSLingrui98 // if a bit does not wrap around, it should not be xored when it exits 391*cf7d6b7aSMuzi val oldest_bits_set = (0 until max_update_num).filter(oldest_bit_wrap_around).map(i => 392*cf7d6b7aSMuzi (oldest_bit_pos_in_folded(i), oldest_bits_masked(i)) 393*cf7d6b7aSMuzi ) 394c2ad24ebSLingrui98 395c2ad24ebSLingrui98 // println(f"old bits pos ${oldest_bits_set.map(_._1)}") 396c2ad24ebSLingrui98 397c2ad24ebSLingrui98 // only the last bit could be 1, as we have at most one taken branch at a time 398ab890bfeSLingrui98 val newest_bits_masked = VecInit((0 until max_update_num).map(i => taken && ((i + 1) == num).B)).asUInt 399c2ad24ebSLingrui98 // if a bit does not wrap around, newest bits should not be xored onto it either 400e992912cSLingrui98 val newest_bits_set = (0 until max_update_num).map(i => (compLen - 1 - i, newest_bits_masked(i))) 401c2ad24ebSLingrui98 402c2ad24ebSLingrui98 // println(f"new bits set ${newest_bits_set.map(_._1)}") 403c2ad24ebSLingrui98 // 404c2ad24ebSLingrui98 val original_bits_masked = VecInit(folded_hist.asBools.zipWithIndex.map { 405ab890bfeSLingrui98 case (fb, i) => fb && !(num >= (len - i)).B 406c2ad24ebSLingrui98 }) 407c2ad24ebSLingrui98 val original_bits_set = (0 until compLen).map(i => (i, original_bits_masked(i))) 408c2ad24ebSLingrui98 409c2ad24ebSLingrui98 // do xor then shift 410c2ad24ebSLingrui98 val xored = bitsets_xor(compLen, Seq(original_bits_set, oldest_bits_set, newest_bits_set)) 411ab890bfeSLingrui98 circular_shift_left(xored, num) 41267402d75SLingrui98 } else { 41367402d75SLingrui98 // histLen too short to wrap around 41467402d75SLingrui98 ((folded_hist << num) | taken)(compLen - 1, 0) 415c2ad24ebSLingrui98 } 41667402d75SLingrui98 417c2ad24ebSLingrui98 val fh = WireInit(this) 418c2ad24ebSLingrui98 fh.folded_hist := new_folded_hist 419c2ad24ebSLingrui98 fh 420c2ad24ebSLingrui98 } 42109c6f1ddSLingrui98} 42209c6f1ddSLingrui98 42367402d75SLingrui98class AheadFoldedHistoryOldestBits(val len: Int, val max_update_num: Int)(implicit p: Parameters) extends XSBundle { 42467402d75SLingrui98 val bits = Vec(max_update_num * 2, Bool()) 42567402d75SLingrui98 // def info = (len, compLen) 42667402d75SLingrui98 def getRealOb(brNumOH: UInt): Vec[Bool] = { 42767402d75SLingrui98 val ob = Wire(Vec(max_update_num, Bool())) 42867402d75SLingrui98 for (i <- 0 until max_update_num) { 42967402d75SLingrui98 ob(i) := Mux1H(brNumOH, bits.drop(i).take(numBr + 1)) 43067402d75SLingrui98 } 43167402d75SLingrui98 ob 43267402d75SLingrui98 } 43367402d75SLingrui98} 43467402d75SLingrui98 435*cf7d6b7aSMuziclass AllAheadFoldedHistoryOldestBits(val gen: Seq[Tuple2[Int, Int]])(implicit p: Parameters) extends XSBundle 436*cf7d6b7aSMuzi with HasBPUConst { 437*cf7d6b7aSMuzi val afhob = MixedVec(gen.filter(t => t._1 > t._2).map(_._1) 43867402d75SLingrui98 .toSet.toList.map(l => new AheadFoldedHistoryOldestBits(l, numBr))) // remove duplicates 43967402d75SLingrui98 require(gen.toSet.toList.equals(gen)) 44067402d75SLingrui98 def getObWithInfo(info: Tuple2[Int, Int]) = { 44167402d75SLingrui98 val selected = afhob.filter(_.len == info._1) 44267402d75SLingrui98 require(selected.length == 1) 44367402d75SLingrui98 selected(0) 44467402d75SLingrui98 } 44567402d75SLingrui98 def read(ghv: Vec[Bool], ptr: CGHPtr) = { 44667402d75SLingrui98 val hisLens = afhob.map(_.len) 44767402d75SLingrui98 val bitsToRead = hisLens.flatMap(l => (0 until numBr * 2).map(i => l - i - 1)).toSet // remove duplicates 44867402d75SLingrui98 val bitsWithInfo = bitsToRead.map(pos => (pos, ghv((ptr + (pos + 1).U).value))) 44967402d75SLingrui98 for (ob <- afhob) { 45067402d75SLingrui98 for (i <- 0 until numBr * 2) { 45167402d75SLingrui98 val pos = ob.len - i - 1 45267402d75SLingrui98 val bit_found = bitsWithInfo.filter(_._1 == pos).toList 45367402d75SLingrui98 require(bit_found.length == 1) 45467402d75SLingrui98 ob.bits(i) := bit_found(0)._2 45567402d75SLingrui98 } 45667402d75SLingrui98 } 45767402d75SLingrui98 } 45867402d75SLingrui98} 45967402d75SLingrui98 46067402d75SLingrui98class AllFoldedHistories(val gen: Seq[Tuple2[Int, Int]])(implicit p: Parameters) extends XSBundle with HasBPUConst { 46167402d75SLingrui98 val hist = MixedVec(gen.map { case (l, cl) => new FoldedHistory(l, cl, numBr) }) 46267402d75SLingrui98 // println(gen.mkString) 46367402d75SLingrui98 require(gen.toSet.toList.equals(gen)) 46467402d75SLingrui98 def getHistWithInfo(info: Tuple2[Int, Int]) = { 46567402d75SLingrui98 val selected = hist.filter(_.info.equals(info)) 46667402d75SLingrui98 require(selected.length == 1) 46767402d75SLingrui98 selected(0) 46867402d75SLingrui98 } 46967402d75SLingrui98 def autoConnectFrom(that: AllFoldedHistories) = { 47067402d75SLingrui98 require(this.hist.length <= that.hist.length) 47167402d75SLingrui98 for (h <- this.hist) { 47267402d75SLingrui98 h := that.getHistWithInfo(h.info) 47367402d75SLingrui98 } 47467402d75SLingrui98 } 47567402d75SLingrui98 def update(ghv: Vec[Bool], ptr: CGHPtr, shift: Int, taken: Bool): AllFoldedHistories = { 47667402d75SLingrui98 val res = WireInit(this) 47767402d75SLingrui98 for (i <- 0 until this.hist.length) { 47867402d75SLingrui98 res.hist(i) := this.hist(i).update(ghv, ptr, shift, taken) 47967402d75SLingrui98 } 48067402d75SLingrui98 res 48167402d75SLingrui98 } 48267402d75SLingrui98 def update(afhob: AllAheadFoldedHistoryOldestBits, lastBrNumOH: UInt, shift: Int, taken: Bool): AllFoldedHistories = { 48367402d75SLingrui98 val res = WireInit(this) 48467402d75SLingrui98 for (i <- 0 until this.hist.length) { 48567402d75SLingrui98 val fh = this.hist(i) 48667402d75SLingrui98 if (fh.need_oldest_bits) { 48767402d75SLingrui98 val info = fh.info 48867402d75SLingrui98 val selectedAfhob = afhob.getObWithInfo(info) 48967402d75SLingrui98 val ob = selectedAfhob.getRealOb(lastBrNumOH) 49067402d75SLingrui98 res.hist(i) := this.hist(i).update(ob, shift, taken) 49167402d75SLingrui98 } else { 49267402d75SLingrui98 val dumb = Wire(Vec(numBr, Bool())) // not needed 49367402d75SLingrui98 dumb := DontCare 49467402d75SLingrui98 res.hist(i) := this.hist(i).update(dumb, shift, taken) 49567402d75SLingrui98 } 49667402d75SLingrui98 } 49767402d75SLingrui98 res 49867402d75SLingrui98 } 49967402d75SLingrui98 500*cf7d6b7aSMuzi def display(cond: Bool) = 50167402d75SLingrui98 for (h <- hist) { 50267402d75SLingrui98 XSDebug(cond, p"hist len ${h.len}, folded len ${h.compLen}, value ${Binary(h.folded_hist)}\n") 50367402d75SLingrui98 } 50467402d75SLingrui98} 50567402d75SLingrui98 50609c6f1ddSLingrui98class TableAddr(val idxBits: Int, val banks: Int)(implicit p: Parameters) extends XSBundle { 50709c6f1ddSLingrui98 def tagBits = VAddrBits - idxBits - instOffsetBits 50809c6f1ddSLingrui98 50909c6f1ddSLingrui98 val tag = UInt(tagBits.W) 51009c6f1ddSLingrui98 val idx = UInt(idxBits.W) 51109c6f1ddSLingrui98 val offset = UInt(instOffsetBits.W) 51209c6f1ddSLingrui98 51309c6f1ddSLingrui98 def fromUInt(x: UInt) = x.asTypeOf(UInt(VAddrBits.W)).asTypeOf(this) 51409c6f1ddSLingrui98 def getTag(x: UInt) = fromUInt(x).tag 51509c6f1ddSLingrui98 def getIdx(x: UInt) = fromUInt(x).idx 51609c6f1ddSLingrui98 def getBank(x: UInt) = if (banks > 1) getIdx(x)(log2Up(banks) - 1, 0) else 0.U 51709c6f1ddSLingrui98 def getBankIdx(x: UInt) = if (banks > 1) getIdx(x)(idxBits - 1, log2Up(banks)) else getIdx(x) 51809c6f1ddSLingrui98} 519eeb5ff92SLingrui98 520b37e4b45SLingrui98trait BasicPrediction extends HasXSParameter { 521b37e4b45SLingrui98 def cfiIndex: ValidUndirectioned[UInt] 522b37e4b45SLingrui98 def target(pc: UInt): UInt 523b37e4b45SLingrui98 def lastBrPosOH: Vec[Bool] 524b37e4b45SLingrui98 def brTaken: Bool 525b37e4b45SLingrui98 def shouldShiftVec: Vec[Bool] 526b37e4b45SLingrui98 def fallThruError: Bool 527b37e4b45SLingrui98} 528935edac4STang Haojin 529b166c0eaSEaston Man// selectByTaken selects some data according to takenMask 5302bf6e0ecSEaston Man// allTargets should be in a Vec, like [taken0, taken1, ..., not taken, not hit] 531b166c0eaSEaston Manobject selectByTaken { 532b166c0eaSEaston Man def apply[T <: Data](takenMask: Vec[Bool], hit: Bool, allTargets: Vec[T]): T = { 533b166c0eaSEaston Man val selVecOH = 534*cf7d6b7aSMuzi takenMask.zipWithIndex.map { case (t, i) => 535*cf7d6b7aSMuzi !takenMask.take(i).fold(false.B)(_ || _) && t && hit 536*cf7d6b7aSMuzi } :+ 537b166c0eaSEaston Man (!takenMask.asUInt.orR && hit) :+ !hit 538b166c0eaSEaston Man Mux1H(selVecOH, allTargets) 539b166c0eaSEaston Man } 540b166c0eaSEaston Man} 541b166c0eaSEaston Man 542*cf7d6b7aSMuziclass FullBranchPrediction(val isNotS3: Boolean)(implicit p: Parameters) extends XSBundle with HasBPUConst 543*cf7d6b7aSMuzi with BasicPrediction { 544eeb5ff92SLingrui98 val br_taken_mask = Vec(numBr, Bool()) 54509c6f1ddSLingrui98 546eeb5ff92SLingrui98 val slot_valids = Vec(totalSlot, Bool()) 54709c6f1ddSLingrui98 548eeb5ff92SLingrui98 val targets = Vec(totalSlot, UInt(VAddrBits.W)) 549b30c10d6SLingrui98 val jalr_target = UInt(VAddrBits.W) // special path for indirect predictors 550a229ab6cSLingrui98 val offsets = Vec(totalSlot, UInt(log2Ceil(PredictWidth).W)) 551a229ab6cSLingrui98 val fallThroughAddr = UInt(VAddrBits.W) 552b37e4b45SLingrui98 val fallThroughErr = Bool() 553fd3aa057SYuandongliang val multiHit = Bool() 55409c6f1ddSLingrui98 55509c6f1ddSLingrui98 val is_jal = Bool() 55609c6f1ddSLingrui98 val is_jalr = Bool() 55709c6f1ddSLingrui98 val is_call = Bool() 55809c6f1ddSLingrui98 val is_ret = Bool() 559f4ebc4b2SLingrui98 val last_may_be_rvi_call = Bool() 560eeb5ff92SLingrui98 val is_br_sharing = Bool() 56109c6f1ddSLingrui98 56209c6f1ddSLingrui98 // val call_is_rvc = Bool() 56309c6f1ddSLingrui98 val hit = Bool() 56409c6f1ddSLingrui98 565209a4cafSSteve Gou val predCycle = if (!env.FPGAPlatform) Some(UInt(64.W)) else None 566209a4cafSSteve Gou 567eeb5ff92SLingrui98 def br_slot_valids = slot_valids.init 568eeb5ff92SLingrui98 def tail_slot_valid = slot_valids.last 569eeb5ff92SLingrui98 570*cf7d6b7aSMuzi def br_valids = 571b37e4b45SLingrui98 VecInit(br_slot_valids :+ (tail_slot_valid && is_br_sharing)) 572eeb5ff92SLingrui98 573*cf7d6b7aSMuzi def taken_mask_on_slot = 574eeb5ff92SLingrui98 VecInit( 575eeb5ff92SLingrui98 (br_slot_valids zip br_taken_mask.init).map { case (t, v) => t && v } :+ ( 576b30c10d6SLingrui98 tail_slot_valid && ( 577b30c10d6SLingrui98 is_br_sharing && br_taken_mask.last || !is_br_sharing 578b30c10d6SLingrui98 ) 579eeb5ff92SLingrui98 ) 580eeb5ff92SLingrui98 ) 581eeb5ff92SLingrui98 582*cf7d6b7aSMuzi def real_slot_taken_mask(): Vec[Bool] = 583b37e4b45SLingrui98 VecInit(taken_mask_on_slot.map(_ && hit)) 584b37e4b45SLingrui98 585b37e4b45SLingrui98 // len numBr 586*cf7d6b7aSMuzi def real_br_taken_mask(): Vec[Bool] = 587b37e4b45SLingrui98 VecInit( 588b37e4b45SLingrui98 taken_mask_on_slot.map(_ && hit).init :+ 589b37e4b45SLingrui98 (br_taken_mask.last && tail_slot_valid && is_br_sharing && hit) 590b37e4b45SLingrui98 ) 591b37e4b45SLingrui98 592b37e4b45SLingrui98 // the vec indicating if ghr should shift on each branch 593b37e4b45SLingrui98 def shouldShiftVec = 594b37e4b45SLingrui98 VecInit(br_valids.zipWithIndex.map { case (v, i) => 595*cf7d6b7aSMuzi v && hit && !real_br_taken_mask().take(i).reduceOption(_ || _).getOrElse(false.B) 596*cf7d6b7aSMuzi }) 597b37e4b45SLingrui98 598b37e4b45SLingrui98 def lastBrPosOH = 599b37e4b45SLingrui98 VecInit((!hit || !br_valids.reduce(_ || _)) +: // not hit or no brs in entry 600b37e4b45SLingrui98 (0 until numBr).map(i => 601b37e4b45SLingrui98 br_valids(i) && 602e3da8badSTang Haojin !real_br_taken_mask().take(i).reduceOption(_ || _).getOrElse(false.B) && // no brs taken in front it 603*cf7d6b7aSMuzi (real_br_taken_mask()(i) || !br_valids.drop(i + 1).reduceOption(_ || _).getOrElse( 604*cf7d6b7aSMuzi false.B 605*cf7d6b7aSMuzi )) && // no brs behind it 606b37e4b45SLingrui98 hit 607*cf7d6b7aSMuzi )) 608b37e4b45SLingrui98 60986d9c530SLingrui98 def brTaken = (br_valids zip br_taken_mask).map { case (a, b) => a && b && hit }.reduce(_ || _) 610b37e4b45SLingrui98 611*cf7d6b7aSMuzi def target(pc: UInt): UInt = 612c6a44c35Smy-mayfly if (isNotS3) { 613b166c0eaSEaston Man selectByTaken(taken_mask_on_slot, hit, allTarget(pc)) 614c6a44c35Smy-mayfly } else { 615c6a44c35Smy-mayfly selectByTaken(taken_mask_on_slot, hit && !fallThroughErr, allTarget(pc)) 616c6a44c35Smy-mayfly } 617b166c0eaSEaston Man 6182bf6e0ecSEaston Man // allTarget return a Vec of all possible target of a BP stage 6192bf6e0ecSEaston Man // in the following order: [taken_target0, taken_target1, ..., fallThroughAddr, not hit (plus fetch width)] 620b166c0eaSEaston Man // 621b166c0eaSEaston Man // This exposes internal targets for timing optimization, 622b166c0eaSEaston Man // since usually targets are generated quicker than taken 623*cf7d6b7aSMuzi def allTarget(pc: UInt): Vec[UInt] = 624b166c0eaSEaston Man VecInit(targets :+ fallThroughAddr :+ (pc + (FetchWidth * 4).U)) 625b37e4b45SLingrui98 626b37e4b45SLingrui98 def fallThruError: Bool = hit && fallThroughErr 627fd3aa057SYuandongliang def ftbMultiHit: Bool = hit && multiHit 628b37e4b45SLingrui98 629b37e4b45SLingrui98 def hit_taken_on_jmp = 630b37e4b45SLingrui98 !real_slot_taken_mask().init.reduce(_ || _) && 631b37e4b45SLingrui98 real_slot_taken_mask().last && !is_br_sharing 632b37e4b45SLingrui98 def hit_taken_on_call = hit_taken_on_jmp && is_call 633b37e4b45SLingrui98 def hit_taken_on_ret = hit_taken_on_jmp && is_ret 634b37e4b45SLingrui98 def hit_taken_on_jalr = hit_taken_on_jmp && is_jalr 635b37e4b45SLingrui98 636b37e4b45SLingrui98 def cfiIndex = { 637b37e4b45SLingrui98 val cfiIndex = Wire(ValidUndirectioned(UInt(log2Ceil(PredictWidth).W))) 638b37e4b45SLingrui98 cfiIndex.valid := real_slot_taken_mask().asUInt.orR 639b37e4b45SLingrui98 // when no takens, set cfiIndex to PredictWidth-1 640b37e4b45SLingrui98 cfiIndex.bits := 641b37e4b45SLingrui98 ParallelPriorityMux(real_slot_taken_mask(), offsets) | 642b37e4b45SLingrui98 Fill(log2Ceil(PredictWidth), (!real_slot_taken_mask().asUInt.orR).asUInt) 643b37e4b45SLingrui98 cfiIndex 644b37e4b45SLingrui98 } 645b37e4b45SLingrui98 646eeb5ff92SLingrui98 def taken = br_taken_mask.reduce(_ || _) || slot_valids.last // || (is_jal || is_jalr) 64709c6f1ddSLingrui98 64847c003a9SEaston Man def fromFtbEntry( 64947c003a9SEaston Man entry: FTBEntry, 65047c003a9SEaston Man pc: UInt, 65147c003a9SEaston Man last_stage_pc: Option[Tuple2[UInt, Bool]] = None, 65247c003a9SEaston Man last_stage_entry: Option[Tuple2[FTBEntry, Bool]] = None 65347c003a9SEaston Man ) = { 654eeb5ff92SLingrui98 slot_valids := entry.brSlots.map(_.valid) :+ entry.tailSlot.valid 65547c003a9SEaston Man targets := entry.getTargetVec(pc, last_stage_pc) // Use previous stage pc for better timing 656b30c10d6SLingrui98 jalr_target := targets.last 657a229ab6cSLingrui98 offsets := entry.getOffsetVec 658eeb5ff92SLingrui98 is_jal := entry.tailSlot.valid && entry.isJal 659eeb5ff92SLingrui98 is_jalr := entry.tailSlot.valid && entry.isJalr 660eeb5ff92SLingrui98 is_call := entry.tailSlot.valid && entry.isCall 661eeb5ff92SLingrui98 is_ret := entry.tailSlot.valid && entry.isRet 662f4ebc4b2SLingrui98 last_may_be_rvi_call := entry.last_may_be_rvi_call 663eeb5ff92SLingrui98 is_br_sharing := entry.tailSlot.valid && entry.tailSlot.sharing 664209a4cafSSteve Gou predCycle.map(_ := GTimer()) 665a229ab6cSLingrui98 666a60a2901SLingrui98 val startLower = Cat(0.U(1.W), pc(instOffsetBits + log2Ceil(PredictWidth) - 1, instOffsetBits)) 667b37e4b45SLingrui98 val endLowerwithCarry = Cat(entry.carry, entry.pftAddr) 668*cf7d6b7aSMuzi fallThroughErr := startLower >= endLowerwithCarry || endLowerwithCarry > (startLower + PredictWidth.U) 66947c003a9SEaston Man fallThroughAddr := Mux(fallThroughErr, pc + (FetchWidth * 4).U, entry.getFallThrough(pc, last_stage_entry)) 670a229ab6cSLingrui98 } 67109c6f1ddSLingrui98 672*cf7d6b7aSMuzi def display(cond: Bool): Unit = 673eeb5ff92SLingrui98 XSDebug(cond, p"[taken_mask] ${Binary(br_taken_mask.asUInt)} [hit] $hit\n") 67409c6f1ddSLingrui98} 67509c6f1ddSLingrui98 676803124a6SLingrui98class SpeculativeInfo(implicit p: Parameters) extends XSBundle 677803124a6SLingrui98 with HasBPUConst with BPUUtils { 678803124a6SLingrui98 val histPtr = new CGHPtr 679c89b4642SGuokai Chen val ssp = UInt(log2Up(RasSize).W) 680deb3a97eSGao-Zeyu val sctr = UInt(RasCtrSize.W) 681c89b4642SGuokai Chen val TOSW = new RASPtr 682c89b4642SGuokai Chen val TOSR = new RASPtr 683c89b4642SGuokai Chen val NOS = new RASPtr 684c89b4642SGuokai Chen val topAddr = UInt(VAddrBits.W) 685803124a6SLingrui98} 686803124a6SLingrui98 687c6a44c35Smy-mayfly// 688c6a44c35Smy-mayflyclass BranchPredictionBundle(val isNotS3: Boolean)(implicit p: Parameters) extends XSBundle 689b37e4b45SLingrui98 with HasBPUConst with BPUUtils { 690adc0b8dfSGuokai Chen val pc = Vec(numDup, UInt(VAddrBits.W)) 691adc0b8dfSGuokai Chen val valid = Vec(numDup, Bool()) 692adc0b8dfSGuokai Chen val hasRedirect = Vec(numDup, Bool()) 69309c6f1ddSLingrui98 val ftq_idx = new FtqPtr 694c6a44c35Smy-mayfly val full_pred = Vec(numDup, new FullBranchPrediction(isNotS3)) 695b37e4b45SLingrui98 696adc0b8dfSGuokai Chen def target(pc: UInt) = VecInit(full_pred.map(_.target(pc))) 697b166c0eaSEaston Man def targets(pc: Vec[UInt]) = VecInit(pc.zipWithIndex.map { case (pc, idx) => full_pred(idx).target(pc) }) 698b166c0eaSEaston Man def allTargets(pc: Vec[UInt]) = VecInit(pc.zipWithIndex.map { case (pc, idx) => full_pred(idx).allTarget(pc) }) 699adc0b8dfSGuokai Chen def cfiIndex = VecInit(full_pred.map(_.cfiIndex)) 700adc0b8dfSGuokai Chen def lastBrPosOH = VecInit(full_pred.map(_.lastBrPosOH)) 701adc0b8dfSGuokai Chen def brTaken = VecInit(full_pred.map(_.brTaken)) 702adc0b8dfSGuokai Chen def shouldShiftVec = VecInit(full_pred.map(_.shouldShiftVec)) 703adc0b8dfSGuokai Chen def fallThruError = VecInit(full_pred.map(_.fallThruError)) 704fd3aa057SYuandongliang def ftbMultiHit = VecInit(full_pred.map(_.ftbMultiHit)) 705eeb5ff92SLingrui98 706adc0b8dfSGuokai Chen def taken = VecInit(cfiIndex.map(_.valid)) 707adc0b8dfSGuokai Chen 708adc0b8dfSGuokai Chen def getTarget = targets(pc) 709b166c0eaSEaston Man def getAllTargets = allTargets(pc) 71009c6f1ddSLingrui98 71109c6f1ddSLingrui98 def display(cond: Bool): Unit = { 712adc0b8dfSGuokai Chen XSDebug(cond, p"[pc] ${Hexadecimal(pc(0))}\n") 713adc0b8dfSGuokai Chen full_pred(0).display(cond) 71409c6f1ddSLingrui98 } 71509c6f1ddSLingrui98} 71609c6f1ddSLingrui98 71709c6f1ddSLingrui98class BranchPredictionResp(implicit p: Parameters) extends XSBundle with HasBPUConst { 718c6a44c35Smy-mayfly val s1 = new BranchPredictionBundle(isNotS3 = true) 719c6a44c35Smy-mayfly val s2 = new BranchPredictionBundle(isNotS3 = true) 720c6a44c35Smy-mayfly val s3 = new BranchPredictionBundle(isNotS3 = false) 72109c6f1ddSLingrui98 722c4a59f19SYuandongliang val s1_uftbHit = Bool() 723c4a59f19SYuandongliang val s1_uftbHasIndirect = Bool() 724c4a59f19SYuandongliang val s1_ftbCloseReq = Bool() 725c4a59f19SYuandongliang 726c2d1ec7dSLingrui98 val last_stage_meta = UInt(MaxMetaLength.W) 7273711cf36S小造xu_zh val last_stage_spec_info = new Ftq_Redirect_SRAMEntry 728c2d1ec7dSLingrui98 val last_stage_ftb_entry = new FTBEntry 729c2d1ec7dSLingrui98 730d2b20d1aSTang Haojin val topdown_info = new FrontendTopDownBundle 731d2b20d1aSTang Haojin 732b37e4b45SLingrui98 def selectedResp = { 733b37e4b45SLingrui98 val res = 73409c6f1ddSLingrui98 PriorityMux(Seq( 735*cf7d6b7aSMuzi (s3.valid(3) && s3.hasRedirect(3)) -> s3, 736*cf7d6b7aSMuzi (s2.valid(3) && s2.hasRedirect(3)) -> s2, 737*cf7d6b7aSMuzi s1.valid(3) -> s1 73809c6f1ddSLingrui98 )) 739b37e4b45SLingrui98 res 740b37e4b45SLingrui98 } 741adc0b8dfSGuokai Chen def selectedRespIdxForFtq = 74209c6f1ddSLingrui98 PriorityMux(Seq( 743*cf7d6b7aSMuzi (s3.valid(3) && s3.hasRedirect(3)) -> BP_S3, 744*cf7d6b7aSMuzi (s2.valid(3) && s2.hasRedirect(3)) -> BP_S2, 745*cf7d6b7aSMuzi s1.valid(3) -> BP_S1 74609c6f1ddSLingrui98 )) 747cb4f77ceSLingrui98 def lastStage = s3 74809c6f1ddSLingrui98} 74909c6f1ddSLingrui98 750c2d1ec7dSLingrui98class BpuToFtqBundle(implicit p: Parameters) extends BranchPredictionResp {} 75109c6f1ddSLingrui98 752803124a6SLingrui98class BranchPredictionUpdate(implicit p: Parameters) extends XSBundle with HasBPUConst { 753803124a6SLingrui98 val pc = UInt(VAddrBits.W) 754803124a6SLingrui98 val spec_info = new SpeculativeInfo 755803124a6SLingrui98 val ftb_entry = new FTBEntry() 756803124a6SLingrui98 757803124a6SLingrui98 val cfi_idx = ValidUndirectioned(UInt(log2Ceil(PredictWidth).W)) 758803124a6SLingrui98 val br_taken_mask = Vec(numBr, Bool()) 759cc2d1573SEaston Man val br_committed = Vec(numBr, Bool()) // High only when br valid && br committed 760803124a6SLingrui98 val jmp_taken = Bool() 76109c6f1ddSLingrui98 val mispred_mask = Vec(numBr + 1, Bool()) 762edc18578SLingrui98 val pred_hit = Bool() 76309c6f1ddSLingrui98 val false_hit = Bool() 76409c6f1ddSLingrui98 val new_br_insert_pos = Vec(numBr, Bool()) 76509c6f1ddSLingrui98 val old_entry = Bool() 76609c6f1ddSLingrui98 val meta = UInt(MaxMetaLength.W) 767abdbe4b7SLingrui98 val full_target = UInt(VAddrBits.W) 768edc18578SLingrui98 val from_stage = UInt(2.W) 76986d9c530SLingrui98 val ghist = UInt(HistoryLength.W) 77009c6f1ddSLingrui98 771803124a6SLingrui98 def is_jal = ftb_entry.tailSlot.valid && ftb_entry.isJal 772803124a6SLingrui98 def is_jalr = ftb_entry.tailSlot.valid && ftb_entry.isJalr 773803124a6SLingrui98 def is_call = ftb_entry.tailSlot.valid && ftb_entry.isCall 774803124a6SLingrui98 def is_ret = ftb_entry.tailSlot.valid && ftb_entry.isRet 775803124a6SLingrui98 776c89b4642SGuokai Chen def is_call_taken = is_call && jmp_taken && cfi_idx.valid && cfi_idx.bits === ftb_entry.tailSlot.offset 777c89b4642SGuokai Chen def is_ret_taken = is_ret && jmp_taken && cfi_idx.valid && cfi_idx.bits === ftb_entry.tailSlot.offset 778c89b4642SGuokai Chen 779803124a6SLingrui98 def display(cond: Bool) = { 78009c6f1ddSLingrui98 XSDebug(cond, p"-----------BranchPredictionUpdate-----------\n") 78109c6f1ddSLingrui98 XSDebug(cond, p"[mispred_mask] ${Binary(mispred_mask.asUInt)} [false_hit] $false_hit\n") 78209c6f1ddSLingrui98 XSDebug(cond, p"[new_br_insert_pos] ${Binary(new_br_insert_pos.asUInt)}\n") 78309c6f1ddSLingrui98 XSDebug(cond, p"--------------------------------------------\n") 78409c6f1ddSLingrui98 } 78509c6f1ddSLingrui98} 78609c6f1ddSLingrui98 78709c6f1ddSLingrui98class BranchPredictionRedirect(implicit p: Parameters) extends Redirect with HasBPUConst { 78809c6f1ddSLingrui98 // override def toPrintable: Printable = { 78909c6f1ddSLingrui98 // p"-----------BranchPredictionRedirect----------- " + 79009c6f1ddSLingrui98 // p"-----------cfiUpdate----------- " + 79109c6f1ddSLingrui98 // p"[pc] ${Hexadecimal(cfiUpdate.pc)} " + 79209c6f1ddSLingrui98 // p"[predTaken] ${cfiUpdate.predTaken}, [taken] ${cfiUpdate.taken}, [isMisPred] ${cfiUpdate.isMisPred} " + 79309c6f1ddSLingrui98 // p"[target] ${Hexadecimal(cfiUpdate.target)} " + 79409c6f1ddSLingrui98 // p"------------------------------- " + 7959aca92b9SYinan Xu // p"[robPtr] f=${robIdx.flag} v=${robIdx.value} " + 79609c6f1ddSLingrui98 // p"[ftqPtr] f=${ftqIdx.flag} v=${ftqIdx.value} " + 79709c6f1ddSLingrui98 // p"[ftqOffset] ${ftqOffset} " + 79809c6f1ddSLingrui98 // p"[level] ${level}, [interrupt] ${interrupt} " + 79909c6f1ddSLingrui98 // p"[stFtqIdx] f=${stFtqIdx.flag} v=${stFtqIdx.value} " + 80009c6f1ddSLingrui98 // p"[stFtqOffset] ${stFtqOffset} " + 80109c6f1ddSLingrui98 // p"\n" 80209c6f1ddSLingrui98 80309c6f1ddSLingrui98 // } 80409c6f1ddSLingrui98 805d2b20d1aSTang Haojin // TODO: backend should pass topdown signals here 806d2b20d1aSTang Haojin // must not change its parent since BPU has used asTypeOf(this type) from its parent class 807d2b20d1aSTang Haojin require(isInstanceOf[Redirect]) 808d2b20d1aSTang Haojin val BTBMissBubble = Bool() 809d2b20d1aSTang Haojin def ControlRedirectBubble = debugIsCtrl 810d2b20d1aSTang Haojin // if mispred br not in ftb, count as BTB miss 811d2b20d1aSTang Haojin def ControlBTBMissBubble = ControlRedirectBubble && !cfiUpdate.br_hit && !cfiUpdate.jr_hit 812d2b20d1aSTang Haojin def TAGEMissBubble = ControlRedirectBubble && cfiUpdate.br_hit && !cfiUpdate.sc_hit 813d2b20d1aSTang Haojin def SCMissBubble = ControlRedirectBubble && cfiUpdate.br_hit && cfiUpdate.sc_hit 814d2b20d1aSTang Haojin def ITTAGEMissBubble = ControlRedirectBubble && cfiUpdate.jr_hit && !cfiUpdate.pd.isRet 815d2b20d1aSTang Haojin def RASMissBubble = ControlRedirectBubble && cfiUpdate.jr_hit && cfiUpdate.pd.isRet 816d2b20d1aSTang Haojin def MemVioRedirectBubble = debugIsMemVio 817d2b20d1aSTang Haojin def OtherRedirectBubble = !debugIsCtrl && !debugIsMemVio 818d2b20d1aSTang Haojin 819*cf7d6b7aSMuzi def connectRedirect(source: Redirect): Unit = 820d2b20d1aSTang Haojin for ((name, data) <- this.elements) { 821d2b20d1aSTang Haojin if (source.elements.contains(name)) { 822d2b20d1aSTang Haojin data := source.elements(name) 823d2b20d1aSTang Haojin } 824d2b20d1aSTang Haojin } 825d2b20d1aSTang Haojin 82609c6f1ddSLingrui98 def display(cond: Bool): Unit = { 82709c6f1ddSLingrui98 XSDebug(cond, p"-----------BranchPredictionRedirect----------- \n") 82809c6f1ddSLingrui98 XSDebug(cond, p"-----------cfiUpdate----------- \n") 82909c6f1ddSLingrui98 XSDebug(cond, p"[pc] ${Hexadecimal(cfiUpdate.pc)}\n") 830c2ad24ebSLingrui98 // XSDebug(cond, p"[hist] ${Binary(cfiUpdate.hist.predHist)}\n") 83109c6f1ddSLingrui98 XSDebug(cond, p"[br_hit] ${cfiUpdate.br_hit} [isMisPred] ${cfiUpdate.isMisPred}\n") 832*cf7d6b7aSMuzi XSDebug( 833*cf7d6b7aSMuzi cond, 834*cf7d6b7aSMuzi p"[pred_taken] ${cfiUpdate.predTaken} [taken] ${cfiUpdate.taken} [isMisPred] ${cfiUpdate.isMisPred}\n" 835*cf7d6b7aSMuzi ) 83609c6f1ddSLingrui98 XSDebug(cond, p"[target] ${Hexadecimal(cfiUpdate.target)} \n") 83709c6f1ddSLingrui98 XSDebug(cond, p"[shift] ${cfiUpdate.shift}\n") 83809c6f1ddSLingrui98 XSDebug(cond, p"------------------------------- \n") 8399aca92b9SYinan Xu XSDebug(cond, p"[robPtr] f=${robIdx.flag} v=${robIdx.value}\n") 84009c6f1ddSLingrui98 XSDebug(cond, p"[ftqPtr] f=${ftqIdx.flag} v=${ftqIdx.value} \n") 84109c6f1ddSLingrui98 XSDebug(cond, p"[ftqOffset] ${ftqOffset} \n") 84209c6f1ddSLingrui98 XSDebug(cond, p"[stFtqIdx] f=${stFtqIdx.flag} v=${stFtqIdx.value}\n") 84309c6f1ddSLingrui98 XSDebug(cond, p"[stFtqOffset] ${stFtqOffset}\n") 84409c6f1ddSLingrui98 XSDebug(cond, p"---------------------------------------------- \n") 84509c6f1ddSLingrui98 } 84609c6f1ddSLingrui98} 847