1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend 18import chipsalliance.rocketchip.config.Parameters 19import chisel3._ 20import chisel3.util._ 21import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 22import utils._ 23import xiangshan._ 24import xiangshan.backend.fu.{PFEvent, PMP, PMPChecker,PMPReqBundle} 25import xiangshan.cache.mmu._ 26import xiangshan.frontend.icache._ 27 28 29class Frontend()(implicit p: Parameters) extends LazyModule with HasXSParameter{ 30 31 val instrUncache = LazyModule(new InstrUncache()) 32 val icache = LazyModule(new ICache()) 33 34 lazy val module = new FrontendImp(this) 35} 36 37 38class FrontendImp (outer: Frontend) extends LazyModuleImp(outer) 39 with HasXSParameter 40 with HasPerfEvents 41{ 42 val io = IO(new Bundle() { 43 val hartId = Input(UInt(8.W)) 44 val reset_vector = Input(UInt(PAddrBits.W)) 45 val fencei = Input(Bool()) 46 val ptw = new TlbPtwIO(6) 47 val backend = new FrontendToCtrlIO 48 val sfence = Input(new SfenceBundle) 49 val tlbCsr = Input(new TlbCsrBundle) 50 val csrCtrl = Input(new CustomCSRCtrlIO) 51 val csrUpdate = new DistributedCSRUpdateReq 52 val error = new L1CacheErrorInfo 53 val frontendInfo = new Bundle { 54 val ibufFull = Output(Bool()) 55 val bpuInfo = new Bundle { 56 val bpRight = Output(UInt(XLEN.W)) 57 val bpWrong = Output(UInt(XLEN.W)) 58 } 59 } 60 }) 61 62 //decouped-frontend modules 63 val instrUncache = outer.instrUncache.module 64 val icache = outer.icache.module 65 val bpu = Module(new Predictor) 66 val ifu = Module(new NewIFU) 67 val ibuffer = Module(new Ibuffer) 68 val ftq = Module(new Ftq) 69 70 val tlbCsr = DelayN(io.tlbCsr, 2) 71 val csrCtrl = DelayN(io.csrCtrl, 2) 72 val sfence = RegNext(RegNext(io.sfence)) 73 74 // trigger 75 ifu.io.frontendTrigger := csrCtrl.frontend_trigger 76 val triggerEn = csrCtrl.trigger_enable 77 ifu.io.csrTriggerEnable := VecInit(triggerEn(0), triggerEn(1), triggerEn(6), triggerEn(8)) 78 79 // bpu ctrl 80 bpu.io.ctrl := csrCtrl.bp_ctrl 81 bpu.io.reset_vector := io.reset_vector 82 83// pmp 84 val pmp = Module(new PMP()) 85 val pmp_check = VecInit(Seq.fill(4)(Module(new PMPChecker(3, sameCycle = true)).io)) 86 pmp.io.distribute_csr := csrCtrl.distribute_csr 87 val pmp_req_vec = Wire(Vec(4, Valid(new PMPReqBundle()))) 88 pmp_req_vec(0) <> icache.io.pmp(0).req 89 pmp_req_vec(1) <> icache.io.pmp(1).req 90 pmp_req_vec(2) <> icache.io.pmp(2).req 91 pmp_req_vec(3) <> ifu.io.pmp.req 92 93 for (i <- pmp_check.indices) { 94 pmp_check(i).apply(tlbCsr.priv.imode, pmp.io.pmp, pmp.io.pma, pmp_req_vec(i)) 95 } 96 icache.io.pmp(0).resp <> pmp_check(0).resp 97 icache.io.pmp(1).resp <> pmp_check(1).resp 98 icache.io.pmp(2).resp <> pmp_check(2).resp 99 ifu.io.pmp.resp <> pmp_check(3).resp 100 101 // val tlb_req_arb = Module(new Arbiter(new TlbReq, 2)) 102 // tlb_req_arb.io.in(0) <> ifu.io.iTLBInter.req 103 // tlb_req_arb.io.in(1) <> icache.io.itlb(1).req 104 105 val itlb_requestors = Wire(Vec(6, new BlockTlbRequestIO)) 106 itlb_requestors(0) <> icache.io.itlb(0) 107 itlb_requestors(1) <> icache.io.itlb(1) 108 itlb_requestors(2) <> icache.io.itlb(2) 109 itlb_requestors(3) <> icache.io.itlb(3) 110 itlb_requestors(4) <> icache.io.itlb(4) 111 itlb_requestors(5) <> ifu.io.iTLBInter 112 113 // itlb_requestors(1).req <> tlb_req_arb.io.out 114 115 // ifu.io.iTLBInter.resp <> itlb_requestors(1).resp 116 // icache.io.itlb(1).resp <> itlb_requestors(1).resp 117 118 io.ptw <> TLB( 119 //in = Seq(icache.io.itlb(0), icache.io.itlb(1)), 120 in = Seq(itlb_requestors(0),itlb_requestors(1),itlb_requestors(2),itlb_requestors(3),itlb_requestors(4),itlb_requestors(5)), 121 sfence = sfence, 122 csr = tlbCsr, 123 width = 6, 124 shouldBlock = true, 125 itlbParams 126 ) 127 128 icache.io.prefetch <> ftq.io.toPrefetch 129 130 val needFlush = RegNext(io.backend.toFtq.redirect.valid) 131 132 //IFU-Ftq 133 ifu.io.ftqInter.fromFtq <> ftq.io.toIfu 134 ftq.io.fromIfu <> ifu.io.ftqInter.toFtq 135 bpu.io.ftq_to_bpu <> ftq.io.toBpu 136 ftq.io.fromBpu <> bpu.io.bpu_to_ftq 137 //IFU-ICache 138 for(i <- 0 until 2){ 139 ifu.io.icacheInter(i).req <> icache.io.fetch(i).req 140 icache.io.fetch(i).req <> ifu.io.icacheInter(i).req 141 ifu.io.icacheInter(i).resp <> icache.io.fetch(i).resp 142 } 143 icache.io.stop := ifu.io.icacheStop 144 145 ifu.io.icachePerfInfo := icache.io.perfInfo 146 147 icache.io.csr.distribute_csr <> csrCtrl.distribute_csr 148 io.csrUpdate := RegNext(icache.io.csr.update) 149 150 icache.io.csr_pf_enable := RegNext(csrCtrl.l1I_pf_enable) 151 icache.io.csr_parity_enable := RegNext(csrCtrl.icache_parity_enable) 152 153 //IFU-Ibuffer 154 ifu.io.toIbuffer <> ibuffer.io.in 155 156 ftq.io.fromBackend <> io.backend.toFtq 157 io.backend.fromFtq <> ftq.io.toBackend 158 io.frontendInfo.bpuInfo <> ftq.io.bpuInfo 159 160 ifu.io.rob_commits <> io.backend.toFtq.rob_commits 161 162 ibuffer.io.flush := needFlush 163 io.backend.cfVec <> ibuffer.io.out 164 165 instrUncache.io.req <> ifu.io.uncacheInter.toUncache 166 ifu.io.uncacheInter.fromUncache <> instrUncache.io.resp 167 instrUncache.io.flush := false.B 168 io.error <> RegNext(RegNext(icache.io.error)) 169 170 icache.io.hartId := io.hartId 171 172 val frontendBubble = PopCount((0 until DecodeWidth).map(i => io.backend.cfVec(i).ready && !ibuffer.io.out(i).valid)) 173 XSPerfAccumulate("FrontendBubble", frontendBubble) 174 io.frontendInfo.ibufFull := RegNext(ibuffer.io.full) 175 176 // PFEvent 177 val pfevent = Module(new PFEvent) 178 pfevent.io.distribute_csr := io.csrCtrl.distribute_csr 179 val csrevents = pfevent.io.hpmevent.take(8) 180 181 val allPerfEvents = Seq(ifu, ibuffer, icache, ftq, bpu).flatMap(_.getPerf) 182 override val perfEvents = HPerfMonitor(csrevents, allPerfEvents).getPerfEvents 183 generatePerfEvent() 184} 185