1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend 18import org.chipsalliance.cde.config.Parameters 19import chisel3._ 20import chisel3.util._ 21import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.backend.fu.{PFEvent, PMP, PMPChecker,PMPReqBundle} 26import xiangshan.cache.mmu._ 27import xiangshan.frontend.icache._ 28 29 30class Frontend()(implicit p: Parameters) extends LazyModule with HasXSParameter { 31 override def shouldBeInlined: Boolean = false 32 33 val instrUncache = LazyModule(new InstrUncache()) 34 val icache = LazyModule(new ICache()) 35 36 lazy val module = new FrontendImp(this) 37} 38 39 40class FrontendImp (outer: Frontend) extends LazyModuleImp(outer) 41 with HasXSParameter 42 with HasPerfEvents 43{ 44 val io = IO(new Bundle() { 45 val hartId = Input(UInt(hartIdLen.W)) 46 val reset_vector = Input(UInt(PAddrBits.W)) 47 val fencei = Input(Bool()) 48 val ptw = new TlbPtwIO() 49 val backend = new FrontendToCtrlIO 50 val sfence = Input(new SfenceBundle) 51 val tlbCsr = Input(new TlbCsrBundle) 52 val csrCtrl = Input(new CustomCSRCtrlIO) 53 val csrUpdate = new DistributedCSRUpdateReq 54 val error = new L1CacheErrorInfo 55 val frontendInfo = new Bundle { 56 val ibufFull = Output(Bool()) 57 val bpuInfo = new Bundle { 58 val bpRight = Output(UInt(XLEN.W)) 59 val bpWrong = Output(UInt(XLEN.W)) 60 } 61 } 62 val debugTopDown = new Bundle { 63 val robHeadVaddr = Flipped(Valid(UInt(VAddrBits.W))) 64 } 65 }) 66 67 //decouped-frontend modules 68 val instrUncache = outer.instrUncache.module 69 val icache = outer.icache.module 70 val bpu = Module(new Predictor) 71 val ifu = Module(new NewIFU) 72 val ibuffer = Module(new IBuffer) 73 val ftq = Module(new Ftq) 74 75 val needFlush = RegNext(io.backend.toFtq.redirect.valid) 76 val FlushControlRedirect = RegNext(io.backend.toFtq.redirect.bits.debugIsCtrl) 77 val FlushMemVioRedirect = RegNext(io.backend.toFtq.redirect.bits.debugIsMemVio) 78 val FlushControlBTBMiss = Wire(Bool()) 79 val FlushTAGEMiss = Wire(Bool()) 80 val FlushSCMiss = Wire(Bool()) 81 val FlushITTAGEMiss = Wire(Bool()) 82 val FlushRASMiss = Wire(Bool()) 83 84 val tlbCsr = DelayN(io.tlbCsr, 2) 85 val csrCtrl = DelayN(io.csrCtrl, 2) 86 val sfence = RegNext(RegNext(io.sfence)) 87 88 // trigger 89 ifu.io.frontendTrigger := csrCtrl.frontend_trigger 90 val triggerEn = csrCtrl.trigger_enable 91 ifu.io.csrTriggerEnable := VecInit(triggerEn(0), triggerEn(1), triggerEn(6), triggerEn(8)) 92 93 // bpu ctrl 94 bpu.io.ctrl := csrCtrl.bp_ctrl 95 bpu.io.reset_vector := RegNext(io.reset_vector) 96 97// pmp 98 val prefetchPipeNum = ICacheParameters().prefetchPipeNum 99 val pmp = Module(new PMP()) 100 val pmp_check = VecInit(Seq.fill(coreParams.ipmpPortNum)(Module(new PMPChecker(3, sameCycle = true)).io)) 101 pmp.io.distribute_csr := csrCtrl.distribute_csr 102 val pmp_req_vec = Wire(Vec(coreParams.ipmpPortNum, Valid(new PMPReqBundle()))) 103 (0 until 2 + prefetchPipeNum).foreach(i => pmp_req_vec(i) <> icache.io.pmp(i).req) 104 pmp_req_vec.last <> ifu.io.pmp.req 105 106 for (i <- pmp_check.indices) { 107 pmp_check(i).apply(tlbCsr.priv.imode, pmp.io.pmp, pmp.io.pma, pmp_req_vec(i)) 108 } 109 (0 until 2 + prefetchPipeNum).foreach(i => icache.io.pmp(i).resp <> pmp_check(i).resp) 110 ifu.io.pmp.resp <> pmp_check.last.resp 111 112 val itlb = Module(new TLB(coreParams.itlbPortNum, nRespDups = 1, 113 Seq(false, false) ++ Seq.fill(prefetchPipeNum)(false) ++ Seq(true), itlbParams)) 114 itlb.io.requestor.take(2 + prefetchPipeNum) zip icache.io.itlb foreach {case (a,b) => a <> b} 115 itlb.io.requestor.last <> ifu.io.iTLBInter // mmio may need re-tlb, blocked 116 itlb.io.hartId := io.hartId 117 itlb.io.base_connect(sfence, tlbCsr) 118 itlb.io.flushPipe.map(_ := needFlush) 119 120 val itlb_ptw = Wire(new VectorTlbPtwIO(coreParams.itlbPortNum)) 121 itlb_ptw.connect(itlb.io.ptw) 122 val itlbRepeater1 = PTWFilter(itlbParams.fenceDelay, itlb_ptw, sfence, tlbCsr, l2tlbParams.ifilterSize) 123 val itlbRepeater2 = PTWRepeaterNB(passReady = false, itlbParams.fenceDelay, itlbRepeater1.io.ptw, io.ptw, sfence, tlbCsr) 124 125 icache.io.prefetch <> ftq.io.toPrefetch 126 127 128 //IFU-Ftq 129 ifu.io.ftqInter.fromFtq <> ftq.io.toIfu 130 ftq.io.toIfu.req.ready := ifu.io.ftqInter.fromFtq.req.ready && icache.io.fetch.req.ready 131 132 ftq.io.fromIfu <> ifu.io.ftqInter.toFtq 133 bpu.io.ftq_to_bpu <> ftq.io.toBpu 134 ftq.io.fromBpu <> bpu.io.bpu_to_ftq 135 136 ftq.io.mmioCommitRead <> ifu.io.mmioCommitRead 137 //IFU-ICache 138 139 icache.io.fetch.req <> ftq.io.toICache.req 140 ftq.io.toICache.req.ready := ifu.io.ftqInter.fromFtq.req.ready && icache.io.fetch.req.ready 141 142 ifu.io.icacheInter.resp <> icache.io.fetch.resp 143 ifu.io.icacheInter.icacheReady := icache.io.toIFU 144 ifu.io.icacheInter.topdownIcacheMiss := icache.io.fetch.topdownIcacheMiss 145 ifu.io.icacheInter.topdownItlbMiss := icache.io.fetch.topdownItlbMiss 146 icache.io.stop := ifu.io.icacheStop 147 148 ifu.io.icachePerfInfo := icache.io.perfInfo 149 150 icache.io.csr.distribute_csr <> DontCare 151 io.csrUpdate := DontCare 152 153 icache.io.csr_pf_enable := RegNext(csrCtrl.l1I_pf_enable) 154 icache.io.csr_parity_enable := RegNext(csrCtrl.icache_parity_enable) 155 156 icache.io.fencei := io.fencei 157 158 //IFU-Ibuffer 159 ifu.io.toIbuffer <> ibuffer.io.in 160 161 ftq.io.fromBackend <> io.backend.toFtq 162 io.backend.fromFtq <> ftq.io.toBackend 163 io.frontendInfo.bpuInfo <> ftq.io.bpuInfo 164 165 val checkPcMem = Reg(Vec(FtqSize, new Ftq_RF_Components)) 166 when (ftq.io.toBackend.pc_mem_wen) { 167 checkPcMem(ftq.io.toBackend.pc_mem_waddr) := ftq.io.toBackend.pc_mem_wdata 168 } 169 170 val checkTargetIdx = Wire(Vec(DecodeWidth, UInt(log2Up(FtqSize).W))) 171 val checkTarget = Wire(Vec(DecodeWidth, UInt(VAddrBits.W))) 172 173 for (i <- 0 until DecodeWidth) { 174 checkTargetIdx(i) := ibuffer.io.out(i).bits.ftqPtr.value 175 checkTarget(i) := Mux(ftq.io.toBackend.newest_entry_ptr.value === checkTargetIdx(i), 176 ftq.io.toBackend.newest_entry_target, 177 checkPcMem(checkTargetIdx(i) + 1.U).startAddr) 178 } 179 180 // commented out for this br could be the last instruction in the fetch block 181 def checkNotTakenConsecutive = { 182 val prevNotTakenValid = RegInit(0.B) 183 val prevNotTakenFtqIdx = Reg(UInt(log2Up(FtqSize).W)) 184 for (i <- 0 until DecodeWidth - 1) { 185 // for instrs that is not the last, if a not-taken br, the next instr should have the same ftqPtr 186 // for instrs that is the last, record and check next request 187 when (ibuffer.io.out(i).fire && ibuffer.io.out(i).bits.pd.isBr) { 188 when (ibuffer.io.out(i+1).fire) { 189 // not last br, check now 190 XSError(checkTargetIdx(i) =/= checkTargetIdx(i+1), "not-taken br should have same ftqPtr\n") 191 } .otherwise { 192 // last br, record its info 193 prevNotTakenValid := true.B 194 prevNotTakenFtqIdx := checkTargetIdx(i) 195 } 196 } 197 } 198 when (ibuffer.io.out(DecodeWidth - 1).fire && ibuffer.io.out(DecodeWidth - 1).bits.pd.isBr) { 199 // last instr is a br, record its info 200 prevNotTakenValid := true.B 201 prevNotTakenFtqIdx := checkTargetIdx(DecodeWidth - 1) 202 } 203 when (prevNotTakenValid && ibuffer.io.out(0).fire) { 204 XSError(prevNotTakenFtqIdx =/= checkTargetIdx(0), "not-taken br should have same ftqPtr\n") 205 prevNotTakenValid := false.B 206 } 207 when (needFlush) { 208 prevNotTakenValid := false.B 209 } 210 } 211 212 def checkTakenNotConsecutive = { 213 val prevTakenValid = RegInit(0.B) 214 val prevTakenFtqIdx = Reg(UInt(log2Up(FtqSize).W)) 215 for (i <- 0 until DecodeWidth - 1) { 216 // for instrs that is not the last, if a taken br, the next instr should not have the same ftqPtr 217 // for instrs that is the last, record and check next request 218 when (ibuffer.io.out(i).fire && ibuffer.io.out(i).bits.pd.isBr && ibuffer.io.out(i).bits.pred_taken) { 219 when (ibuffer.io.out(i+1).fire) { 220 // not last br, check now 221 XSError(checkTargetIdx(i) + 1.U =/= checkTargetIdx(i+1), "taken br should have consecutive ftqPtr\n") 222 } .otherwise { 223 // last br, record its info 224 prevTakenValid := true.B 225 prevTakenFtqIdx := checkTargetIdx(i) 226 } 227 } 228 } 229 when (ibuffer.io.out(DecodeWidth - 1).fire && ibuffer.io.out(DecodeWidth - 1).bits.pd.isBr && ibuffer.io.out(DecodeWidth - 1).bits.pred_taken) { 230 // last instr is a br, record its info 231 prevTakenValid := true.B 232 prevTakenFtqIdx := checkTargetIdx(DecodeWidth - 1) 233 } 234 when (prevTakenValid && ibuffer.io.out(0).fire) { 235 XSError(prevTakenFtqIdx + 1.U =/= checkTargetIdx(0), "taken br should have consecutive ftqPtr\n") 236 prevTakenValid := false.B 237 } 238 when (needFlush) { 239 prevTakenValid := false.B 240 } 241 } 242 243 def checkNotTakenPC = { 244 val prevNotTakenPC = Reg(UInt(VAddrBits.W)) 245 val prevIsRVC = Reg(Bool()) 246 val prevNotTakenValid = RegInit(0.B) 247 248 for (i <- 0 until DecodeWidth - 1) { 249 when (ibuffer.io.out(i).fire && ibuffer.io.out(i).bits.pd.isBr && !ibuffer.io.out(i).bits.pred_taken) { 250 when (ibuffer.io.out(i+1).fire) { 251 XSError(ibuffer.io.out(i).bits.pc + Mux(ibuffer.io.out(i).bits.pd.isRVC, 2.U, 4.U) =/= ibuffer.io.out(i+1).bits.pc, "not-taken br should have consecutive pc\n") 252 } .otherwise { 253 prevNotTakenValid := true.B 254 prevIsRVC := ibuffer.io.out(i).bits.pd.isRVC 255 prevNotTakenPC := ibuffer.io.out(i).bits.pc 256 } 257 } 258 } 259 when (ibuffer.io.out(DecodeWidth - 1).fire && ibuffer.io.out(DecodeWidth - 1).bits.pd.isBr && !ibuffer.io.out(DecodeWidth - 1).bits.pred_taken) { 260 prevNotTakenValid := true.B 261 prevIsRVC := ibuffer.io.out(DecodeWidth - 1).bits.pd.isRVC 262 prevNotTakenPC := ibuffer.io.out(DecodeWidth - 1).bits.pc 263 } 264 when (prevNotTakenValid && ibuffer.io.out(0).fire) { 265 XSError(prevNotTakenPC + Mux(prevIsRVC, 2.U, 4.U) =/= ibuffer.io.out(0).bits.pc, "not-taken br should have same pc\n") 266 prevNotTakenValid := false.B 267 } 268 when (needFlush) { 269 prevNotTakenValid := false.B 270 } 271 } 272 273 def checkTakenPC = { 274 val prevTakenFtqIdx = Reg(UInt(log2Up(FtqSize).W)) 275 val prevTakenValid = RegInit(0.B) 276 val prevTakenTarget = Wire(UInt(VAddrBits.W)) 277 prevTakenTarget := checkPcMem(prevTakenFtqIdx + 1.U).startAddr 278 279 for (i <- 0 until DecodeWidth - 1) { 280 when (ibuffer.io.out(i).fire && !ibuffer.io.out(i).bits.pd.notCFI && ibuffer.io.out(i).bits.pred_taken) { 281 when (ibuffer.io.out(i+1).fire) { 282 XSError(checkTarget(i) =/= ibuffer.io.out(i+1).bits.pc, "taken instr should follow target pc\n") 283 } .otherwise { 284 prevTakenValid := true.B 285 prevTakenFtqIdx := checkTargetIdx(i) 286 } 287 } 288 } 289 when (ibuffer.io.out(DecodeWidth - 1).fire && !ibuffer.io.out(DecodeWidth - 1).bits.pd.notCFI && ibuffer.io.out(DecodeWidth - 1).bits.pred_taken) { 290 prevTakenValid := true.B 291 prevTakenFtqIdx := checkTargetIdx(DecodeWidth - 1) 292 } 293 when (prevTakenValid && ibuffer.io.out(0).fire) { 294 XSError(prevTakenTarget =/= ibuffer.io.out(0).bits.pc, "taken instr should follow target pc\n") 295 prevTakenValid := false.B 296 } 297 when (needFlush) { 298 prevTakenValid := false.B 299 } 300 } 301 302 //checkNotTakenConsecutive 303 checkTakenNotConsecutive 304 checkTakenPC 305 checkNotTakenPC 306 307 ifu.io.rob_commits <> io.backend.toFtq.rob_commits 308 309 ibuffer.io.flush := needFlush 310 ibuffer.io.ControlRedirect := FlushControlRedirect 311 ibuffer.io.MemVioRedirect := FlushMemVioRedirect 312 ibuffer.io.ControlBTBMissBubble := FlushControlBTBMiss 313 ibuffer.io.TAGEMissBubble := FlushTAGEMiss 314 ibuffer.io.SCMissBubble := FlushSCMiss 315 ibuffer.io.ITTAGEMissBubble := FlushITTAGEMiss 316 ibuffer.io.RASMissBubble := FlushRASMiss 317 318 FlushControlBTBMiss := ftq.io.ControlBTBMissBubble 319 FlushTAGEMiss := ftq.io.TAGEMissBubble 320 FlushSCMiss := ftq.io.SCMissBubble 321 FlushITTAGEMiss := ftq.io.ITTAGEMissBubble 322 FlushRASMiss := ftq.io.RASMissBubble 323 324 io.backend.cfVec <> ibuffer.io.out 325 io.backend.stallReason <> ibuffer.io.stallReason 326 327 instrUncache.io.req <> ifu.io.uncacheInter.toUncache 328 ifu.io.uncacheInter.fromUncache <> instrUncache.io.resp 329 instrUncache.io.flush := false.B 330 io.error <> RegNext(RegNext(icache.io.error)) 331 332 icache.io.hartId := io.hartId 333 334 itlbRepeater1.io.debugTopDown.robHeadVaddr := io.debugTopDown.robHeadVaddr 335 336 val frontendBubble = PopCount((0 until DecodeWidth).map(i => io.backend.cfVec(i).ready && !ibuffer.io.out(i).valid)) 337 XSPerfAccumulate("FrontendBubble", frontendBubble) 338 io.frontendInfo.ibufFull := RegNext(ibuffer.io.full) 339 340 // PFEvent 341 val pfevent = Module(new PFEvent) 342 pfevent.io.distribute_csr := io.csrCtrl.distribute_csr 343 val csrevents = pfevent.io.hpmevent.take(8) 344 345 val perfFromUnits = Seq(ifu, ibuffer, icache, ftq, bpu).flatMap(_.getPerfEvents) 346 val perfFromIO = Seq() 347 val perfBlock = Seq() 348 // let index = 0 be no event 349 val allPerfEvents = Seq(("noEvent", 0.U)) ++ perfFromUnits ++ perfFromIO ++ perfBlock 350 351 if (printEventCoding) { 352 for (((name, inc), i) <- allPerfEvents.zipWithIndex) { 353 println("Frontend perfEvents Set", name, inc, i) 354 } 355 } 356 357 val allPerfInc = allPerfEvents.map(_._2.asTypeOf(new PerfEvent)) 358 override val perfEvents = HPerfMonitor(csrevents, allPerfInc).getPerfEvents 359 generatePerfEvent() 360} 361