1package xiangshan.frontend 2import utils.XSInfo 3import chisel3._ 4import chisel3.util._ 5import utils.PipelineConnect 6import xiangshan._ 7import xiangshan.cache._ 8import xiangshan.cache.prefetch.L1plusPrefetcher 9 10 11class Frontend extends XSModule with HasL1plusCacheParameters { 12 val io = IO(new Bundle() { 13 val icacheMemAcq = DecoupledIO(new L1plusCacheReq) 14 val icacheMemGrant = Flipped(DecoupledIO(new L1plusCacheResp)) 15 val l1plusFlush = Output(Bool()) 16 val fencei = Input(Bool()) 17 val ptw = new TlbPtwIO 18 val backend = new FrontendToBackendIO 19 val sfence = Input(new SfenceBundle) 20 val tlbCsr = Input(new TlbCsrBundle) 21 }) 22 23 val ifu = Module(new IFU) 24 val ibuffer = Module(new Ibuffer) 25 val l1plusPrefetcher = Module(new L1plusPrefetcher) 26 27 28 val needFlush = io.backend.redirect.valid 29 30 // from backend 31 ifu.io.redirect <> io.backend.redirect 32 ifu.io.cfiUpdateInfo <> io.backend.cfiUpdateInfo 33 // to icache 34 val grantClientId = clientId(io.icacheMemGrant.bits.id) 35 val grantEntryId = entryId(io.icacheMemGrant.bits.id) 36 ifu.io.icacheMemGrant.valid := io.icacheMemGrant.valid && grantClientId === icacheMissQueueId.U 37 ifu.io.icacheMemGrant.bits := io.icacheMemGrant.bits 38 ifu.io.icacheMemGrant.bits.id := Cat(0.U(clientIdWidth.W), grantEntryId) 39 l1plusPrefetcher.io.mem_grant.valid := io.icacheMemGrant.valid && grantClientId === l1plusPrefetcherId.U 40 l1plusPrefetcher.io.mem_grant.bits := io.icacheMemGrant.bits 41 l1plusPrefetcher.io.mem_grant.bits.id := Cat(0.U(clientIdWidth.W), grantEntryId) 42 io.icacheMemGrant.ready := Mux(grantClientId === icacheMissQueueId.U, 43 ifu.io.icacheMemGrant.ready, 44 l1plusPrefetcher.io.mem_grant.ready) 45 ifu.io.fencei := io.fencei 46 // to tlb 47 ifu.io.sfence := io.sfence 48 ifu.io.tlbCsr := io.tlbCsr 49 // from icache and l1plus prefetcher 50 io.l1plusFlush := ifu.io.l1plusFlush 51 l1plusPrefetcher.io.in.valid := ifu.io.prefetchTrainReq.valid 52 l1plusPrefetcher.io.in.bits := ifu.io.prefetchTrainReq.bits 53 val memAcquireArb = Module(new Arbiter(new L1plusCacheReq, nClients)) 54 memAcquireArb.io.in(icacheMissQueueId) <> ifu.io.icacheMemAcq 55 memAcquireArb.io.in(icacheMissQueueId).bits.id := Cat(icacheMissQueueId.U(clientIdWidth.W), 56 entryId(ifu.io.icacheMemAcq.bits.id)) 57 memAcquireArb.io.in(l1plusPrefetcherId) <> l1plusPrefetcher.io.mem_acquire 58 memAcquireArb.io.in(l1plusPrefetcherId).bits.id := Cat(l1plusPrefetcherId.U(clientIdWidth.W), 59 entryId(l1plusPrefetcher.io.mem_acquire.bits.id)) 60 io.icacheMemAcq <> memAcquireArb.io.out 61 // itlb to ptw 62 io.ptw <> ifu.io.ptw 63 // ifu to ibuffer 64 ibuffer.io.in <> ifu.io.fetchPacket 65 // backend to ibuffer 66 ibuffer.io.flush := needFlush 67 // ibuffer to backend 68 io.backend.cfVec <> ibuffer.io.out 69 70 // for(out <- ibuffer.io.out){ 71 // XSInfo(out.fire(), 72 // p"inst:${Hexadecimal(out.bits.instr)} pc:${Hexadecimal(out.bits.pc)}\n" 73 // ) 74 // } 75 76 77}