1package xiangshan.frontend 2import utils._ 3import chisel3._ 4import chisel3.util._ 5import chipsalliance.rocketchip.config.Parameters 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import xiangshan._ 8import xiangshan.cache._ 9import xiangshan.cache.prefetch.L1plusPrefetcher 10import xiangshan.backend.fu.HasExceptionNO 11import system.L1CacheErrorInfo 12 13 14class Frontend()(implicit p: Parameters) extends LazyModule with HasXSParameter{ 15 16 val instrUncache = LazyModule(new InstrUncache()) 17 18 lazy val module = new FrontendImp(this) 19} 20 21 22class FrontendImp (outer: Frontend) extends LazyModuleImp(outer) 23 with HasL1plusCacheParameters 24 with HasXSParameter 25 with HasExceptionNO 26{ 27 val io = IO(new Bundle() { 28 val icacheMemAcq = DecoupledIO(new L1plusCacheReq) 29 val icacheMemGrant = Flipped(DecoupledIO(new L1plusCacheResp)) 30 val l1plusFlush = Output(Bool()) 31 val fencei = Input(Bool()) 32 val ptw = new TlbPtwIO 33 val backend = new FrontendToBackendIO 34 val sfence = Input(new SfenceBundle) 35 val tlbCsr = Input(new TlbCsrBundle) 36 val csrCtrl = Input(new CustomCSRCtrlIO) 37 val error = new L1CacheErrorInfo 38 val frontendInfo = new Bundle { 39 val ibufFull = Output(Bool()) 40 } 41 }) 42 43 val ifu = Module(new IFU) 44 val ibuffer = Module(new Ibuffer) 45 val l1plusPrefetcher = Module(new L1plusPrefetcher) 46 val instrUncache = outer.instrUncache.module 47 48 val needFlush = io.backend.redirect_cfiUpdate.valid 49 50 // from backend 51 ifu.io.redirect <> io.backend.redirect_cfiUpdate 52 ifu.io.bp_ctrl <> io.csrCtrl.bp_ctrl 53 ifu.io.commitUpdate <> io.backend.commit_cfiUpdate 54 ifu.io.ftqEnqPtr <> io.backend.ftqEnqPtr 55 ifu.io.ftqLeftOne <> io.backend.ftqLeftOne 56 // to icache 57 val grantClientId = clientId(io.icacheMemGrant.bits.id) 58 val grantEntryId = entryId(io.icacheMemGrant.bits.id) 59 ifu.io.icacheMemGrant.valid := io.icacheMemGrant.valid && grantClientId === icacheMissQueueId.U 60 ifu.io.icacheMemGrant.bits := io.icacheMemGrant.bits 61 ifu.io.icacheMemGrant.bits.id := Cat(0.U(clientIdWidth.W), grantEntryId) 62 l1plusPrefetcher.io.mem_grant.valid := io.icacheMemGrant.valid && grantClientId === l1plusPrefetcherId.U 63 l1plusPrefetcher.io.mem_grant.bits := io.icacheMemGrant.bits 64 l1plusPrefetcher.io.mem_grant.bits.id := Cat(0.U(clientIdWidth.W), grantEntryId) 65 assert(RegNext(!l1plusPrefetcher.io.mem_grant.valid || (l1plusPrefetcher.io.mem_grant.ready && grantClientId === l1plusPrefetcherId.U))) 66 io.icacheMemGrant.ready := Mux(grantClientId === icacheMissQueueId.U, 67 ifu.io.icacheMemGrant.ready, 68 l1plusPrefetcher.io.mem_grant.ready) 69 ifu.io.fencei := io.fencei 70 71 72 instrUncache.io.req <> ifu.io.mmio_acquire 73 instrUncache.io.resp <> ifu.io.mmio_grant 74 instrUncache.io.flush <> ifu.io.mmio_flush 75 // to tlb 76 ifu.io.sfence := io.sfence 77 ifu.io.tlbCsr := io.tlbCsr 78 // from icache and l1plus prefetcher 79 io.l1plusFlush := ifu.io.l1plusFlush 80 l1plusPrefetcher.io.in.valid := ifu.io.prefetchTrainReq.valid 81 l1plusPrefetcher.io.in.bits := ifu.io.prefetchTrainReq.bits 82 l1plusPrefetcher.io.enable := RegNext(io.csrCtrl.l1plus_pf_enable) 83 val memAcquireArb = Module(new Arbiter(new L1plusCacheReq, nClients)) 84 memAcquireArb.io.in(icacheMissQueueId) <> ifu.io.icacheMemAcq 85 memAcquireArb.io.in(icacheMissQueueId).bits.id := Cat(icacheMissQueueId.U(clientIdWidth.W), 86 entryId(ifu.io.icacheMemAcq.bits.id)) 87 memAcquireArb.io.in(l1plusPrefetcherId) <> l1plusPrefetcher.io.mem_acquire 88 memAcquireArb.io.in(l1plusPrefetcherId).bits.id := Cat(l1plusPrefetcherId.U(clientIdWidth.W), 89 entryId(l1plusPrefetcher.io.mem_acquire.bits.id)) 90 io.icacheMemAcq <> memAcquireArb.io.out 91 // itlb to ptw 92 io.ptw <> ifu.io.ptw 93 // ifu to ibuffer 94 ibuffer.io.in <> ifu.io.fetchPacket 95 // backend to ibuffer 96 ibuffer.io.flush := needFlush 97 // ibuffer to backend 98 io.backend.cfVec <> ibuffer.io.out 99 // ifu to backend 100 io.backend.fetchInfo <> ifu.io.toFtq 101 102 io.error <> RegNext(RegNext(ifu.io.error)) 103 104 // for(out <- ibuffer.io.out){ 105 // XSInfo(out.fire(), 106 // p"inst:${Hexadecimal(out.bits.instr)} pc:${Hexadecimal(out.bits.pc)}\n" 107 // ) 108 // } 109 110 val frontendBubble = PopCount((0 until DecodeWidth).map(i => io.backend.cfVec(i).ready && !ibuffer.io.out(i).valid)) 111 XSPerfAccumulate("FrontendBubble", frontendBubble) 112 113 io.frontendInfo.ibufFull := RegNext(ibuffer.io.full) 114} 115