1package xiangshan.frontend 2 3import chisel3._ 4import chisel3.util._ 5import utils.PipelineConnect 6import xiangshan._ 7import xiangshan.utils.XSInfo 8 9class Frontend extends XSModule { 10 val io = IO(new Bundle() { 11 val backend = new FrontendToBackendIO 12 }) 13 14// val fakeIFU = Module(new FakeIFU) 15// val ibuffer= Module(new Ibuffer) 16 17// val needFlush = io.backend.redirectInfo.flush() 18 19// fakeIFU.io.redirect.valid := needFlush 20// fakeIFU.io.redirect.bits := io.backend.redirectInfo.redirect 21 22// ibuffer.io.in <> fakeIFU.io.fetchPacket 23// ibuffer.io.flush := needFlush 24 25// io.backend.cfVec <> ibuffer.io.out 26 27// for(out <- ibuffer.io.out){ 28// XSInfo(out.fire(), 29// p"inst:${Hexadecimal(out.bits.instr)} pc:${Hexadecimal(out.bits.pc)}\n" 30// ) 31// } 32 33 val ifu = Module(new IFU) 34 val fakeicache = Module(new FakeCache) 35 val ibuffer= Module(new Ibuffer) 36 37 val needFlush = io.backend.redirectInfo.flush() 38 39 ifu.io.redirectInfo <> io.backend.redirectInfo 40 fakeicache.io.in <> ifu.io.icacheReq 41 ifu.io.icacheResp <> fakeicache.io.out 42 43 ibuffer.io.in <> ifu.io.fetchPacket 44 ibuffer.io.flush := needFlush 45 46 io.backend.cfVec <> ibuffer.io.out 47 48 for(out <- ibuffer.io.out){ 49 XSInfo(out.fire(), 50 p"inst:${Hexadecimal(out.bits.instr)} pc:${Hexadecimal(out.bits.pc)}\n" 51 ) 52 } 53 54 55} 56