1package xiangshan.frontend 2import utils.XSInfo 3import chisel3._ 4import chisel3.util._ 5import utils.PipelineConnect 6import xiangshan._ 7import xiangshan.cache._ 8 9 10class Frontend extends XSModule { 11 val io = IO(new Bundle() { 12 val icacheMemAcq = DecoupledIO(new L1plusCacheReq) 13 val icacheMemGrant = Flipped(DecoupledIO(new L1plusCacheResp)) 14 val l1plusFlush = Output(Bool()) 15 val fencei = Input(Bool()) 16 val ptw = new TlbPtwIO 17 val backend = new FrontendToBackendIO 18 val sfence = Input(new SfenceBundle) 19 val tlbCsr = Input(new TlbCsrBundle) 20 }) 21 22 val ifu = Module(new IFU) 23 val ibuffer = Module(new Ibuffer) 24 25 26 val needFlush = io.backend.redirect.valid 27 28 // from backend 29 ifu.io.redirect <> io.backend.redirect 30 ifu.io.cfiUpdateInfo <> io.backend.cfiUpdateInfo 31 // to icache 32 ifu.io.icacheMemGrant <> io.icacheMemGrant 33 ifu.io.fencei := io.fencei 34 // from icache 35 io.l1plusFlush := ifu.io.l1plusFlush 36 io.icacheMemAcq <> ifu.io.icacheMemAcq 37 // itlb to ptw 38 io.ptw <> ifu.io.ptw 39 // ifu to ibuffer 40 ibuffer.io.in <> ifu.io.fetchPacket 41 // backend to ibuffer 42 ibuffer.io.flush := needFlush 43 // ibuffer to backend 44 io.backend.cfVec <> ibuffer.io.out 45 46 // for(out <- ibuffer.io.out){ 47 // XSInfo(out.fire(), 48 // p"inst:${Hexadecimal(out.bits.instr)} pc:${Hexadecimal(out.bits.pc)}\n" 49 // ) 50 // } 51 52 53}