1package xiangshan.frontend 2import utils.XSInfo 3import chisel3._ 4import chisel3.util._ 5import utils.PipelineConnect 6import xiangshan._ 7 8 9class Frontend extends XSModule { 10 val io = IO(new Bundle() { 11 val backend = new FrontendToBackendIO 12 }) 13 14 val ifu = Module(new IFU) 15 val fakeicache = Module(new FakeCache) 16 val ibuffer = if(EnableLB) Module(new LoopBuffer) else Module(new Ibuffer) 17 18 val needFlush = io.backend.redirect.valid 19 20 ifu.io.redirect <> io.backend.redirect 21 ifu.io.inOrderBrInfo <> io.backend.inOrderBrInfo 22 ifu.io.outOfOrderBrInfo <> io.backend.outOfOrderBrInfo 23 fakeicache.io.in <> ifu.io.icacheReq 24 ifu.io.icacheResp <> fakeicache.io.out 25 fakeicache.io.flush := ifu.io.icacheFlush 26 27 ibuffer.io.in <> ifu.io.fetchPacket 28 ibuffer.io.flush := needFlush 29 30 io.backend.cfVec <> ibuffer.io.out 31 32 // for(out <- ibuffer.io.out){ 33 // XSInfo(out.fire(), 34 // p"inst:${Hexadecimal(out.bits.instr)} pc:${Hexadecimal(out.bits.pc)}\n" 35 // ) 36 // } 37 38 39} 40